CHAPTER 1

BASIC OF LINUX
1.1 Objective of Using Linux

Linux has become an integral part of the VLSI (Very Large-Scale Integration) field due to
its versatility, reliability, and cost-effectiveness. Linux offers several advantages for VLSI
designers, including access to open-source tools and libraries, a powerful command-line
interface, and a highly customizable operating system. One of the primary objectives of
using Linux in the VLSI field is to facilitate the development of complex VLSI designs by
providing a robust and stable environment for designing, simulating, and verifying
integrated circuits. Linux provides access to a wide range of open-source EDA (Electronic
Design Automation) tools, such as SPICE (Simulation Program with Integrated Circuit
Emphasis), which are critical for VLSI designers to simulate and analyze the behavior of
electronic circuits. Additionally, Linux offers support for scripting languages, such as Perl
and Python, which are commonly used for automating repetitive tasks in the VLSI design
process. By using Linux, VLSI designers can leverage the power of open-source software
to create efficient and reliable designs, while minimizing the cost and time required to
develop and test their designs.

1.2 What is Linux?

Linux is an open-source operating system. Linux was designed to be like UNIX. It was
created by Linus Torvalds in 1991. It is written in C & C++ languages.

1.3 Why Linux?

It supports CLI and GUI modes. It’s also become the largest open-source software project
in the world. So, anyone can study, run, share and modify the software. The modified code
can also be redistributed and even sold but must be done under the same license. Traditional
operating systems – Unix, windows etc. which are proprietary, locked-down and delivered
as-is Linux run almost every computing platform available: mobile, tablets, server, desktops,
laptops etc.

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1.4 Features of Linux

Figure 1.1 Features of Linux

• Open-source philosophy: Linux is built on the open-source philosophy, which means that the
source code is freely available to anyone who wants to use or modify it. This has led to a vibrant
community of developers who contribute to the development and improvement of the operating
system.

• Customizability: Linux is highly customizable and can be tailored to meet the specific needs of
individual users or organizations. This makes it a popular choice for businesses and organizations
that require a customized operating system that can meet their specific requirements.

• Desktop Environment: Linux offers a wide range of desktop environments, such as GNOME,
KDE, and XFCE, which provide different user interfaces and functionality. Users can choose the
desktop environment that suits their needs and customize it further by installing themes, icons,
and other customization options.

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• Software: Linux offers a wide range of software that can be installed and customized to suit the
user's needs. Users can choose from different software packages for web browsing, office
productivity, media players, programming, and more.

• Kernel: The Linux kernel is the core component of the operating system that manages system
resources and provides access to hardware devices. Users can customize the kernel by selecting
specific features and options to optimize performance and functionality.

• Command-line Interface: Linux offers a powerful command-line interface that can be

customized to suit the user's needs. Users can create custom scripts, aliases, and shortcuts to
automate tasks and improve productivity.

• Security: Linux is considered to be more secure than other operating systems, such as Windows,
because of its built-in security features and the fact that the source code is open and can be audited
for security vulnerabilities.

• Stability and reliability: Linux is known for its stability and reliability, which makes it a popular
choice for servers and other critical systems that need to be up and running 24/7.Cost-effective:
Linux is free to use and distribute, which makes it a cost-effective alternative to proprietary
operating systems like Windows and macOS. This makes it a popular choice for individuals, small
businesses, and organizations that want to save on licensing costs.

• Multiuser: Linux allows multiple user to login and use the resources at a time.

• Multiprocessing and multi-tasking: It allows us to perform multiple processes as well as multiple

application at same time.

• Portability: Linux can be installed on any hardware architecture.

1.5 Layers of Linux OS

Kernel:

Kernel is the core of the Linux based operating system. It virtualizes the common hardware
resources of the computer to provide each process with its virtual resources. This makes the
process seem as if it is the sole process running on the machine. The kernel is also responsible for
preventing and mitigating conflicts between different processes. Different types of the kernel are:

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• Monolithic Kernel

• Hybrid kernels

• Exo kernels

• Micro kernels

Figure 1.2 Layers of Linux OS

System Library: These libraries can be specified as some special functions. These are applied for
implementing the operating system's functionality and don't need code access rights of the modules
of kernel.

Shell: It is an interface between the kernel and user. It can afford the services of kernel. It can take
commands through the user and runs the functions of the kernel. The shell is available in distinct
types of OS. These operating systems are categorized into two different types, which are the
graphical shells and command-line shells.

There are various types of shells:

• Bourne shell: Bourne shell was the first shell to appear on Unix systems.

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• Bash shell: bash means Bourne Again Shell. It is a default shell over several distributions of Linux
today. It is a sh-compatible shell.

• C shell: csh. C shell based on C programming language.

• Korn shell: ksh. Backward compatible with sh, but with some features of csh.

Hardware Layer: Linux operating system contains a hardware layer that consists of several
peripheral devices like CPU, HDD, and RAM.

System Utility: It provides the functionalities of an operating system to the user.

1.6 Linux Editors

Linux text editors can be used for editing text files, writing codes, updating user instruction files,
and more. A Linux system supports multiple text editors.

There are two types of text editors in Linux, which are given below:

• Command-line text editors such as Vi, nano, pico, and more.

• GUI text editors such as gedit (for Gnome), Kwrite, and more.

A text editor plays an important role while coding. So, it is important to select the best text editor.
A text editor should not only be simple but also functional and should be good to work with. A
text editor with IDE features is considered as a good text editor.

1.6.1 Command-Line Text Editors

Vi/VIM editor:

• Vim editor is one of the most used and powerful command-line based editor of the Linux system.

• By default, it is supported by most Linux distributions. It has enhanced functionalities of the old
Unix Vi editor.

• It is a user-friendly editor and provides the same environment for all the Linux distributions.

• It is also termed as programmer's editor because most programmers prefer Vi editor. To open a
file in vim editor, we need to use the command ‘vim filename’.
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It has two modes:

• Command Mode: The command mode allows us to perform actions on files. By default, it starts
in command mode. In this mode, all types of words are considered as commands. We can execute
commands in this mode.

• Insert Mode: The insert mode allows to insert text in file. To switch from command mode to
insert mode 'i' key and press the Esc key to exit from active mode.

Nano editor:

Nano is a straightforward editor. It is designed for both beginners and advanced users. It has many
customization features.

Some advanced features of a nano text editor are as following:

• It has highly customizable key bindings

• It supports syntax highlighting

• It has undo and redo options

• It provides full line display on the standard output

1.5.2 Basic Commands

cd : The “cd” command is used to change directory location. Without an argument, “cd” takes us
to our home directory.

ls: The “ls” command is used to list the files in a directory. Like many Linux commands, it can take
a number of “flags” as options to change the behavior of the command.

cat: cat is short for concatenate. The cat command takes one or more files and concatenates their
contents to standard output. It is used to create the file with content.

echo: echo is used to output arbitrary text to the terminal.

pwd: The pwd command stands for print working directory. It is one of the most basic and
frequently used commands in Linux. When invoked the command prints the complete path of the
current working directory.
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mkdir: In Linux systems, we can create new directories either from the command line or with the
help of our desktop’s file manager. The command that allows us to create directories also known
as folders is mkdir.

rmdir: rmdir command is used to remove empty directories from the filesystem in Linux. The
rmdir command removes each and every directory specified in the command line only if these
directories are empty. So, if the specified directory has some directories or files in it then this
cannot be removed by rmdir command.

touch command: It is used to create a file without any content. The file created using touch
command is empty. This command can be used when the user doesn’t have data to store at the time
of file creation.

cp: cp stands for copy. This command is used to copy files or group of files or directory. It creates
an exact image of a file on a disk with different file name. cp command require at least two
filenames in its arguments.

mv: mv stands for move. mv is used to move one or more files or directories from one place to
another in a file system like UNIX. It has two distinct functions firstly it renames a file or folder and
it also moves a group of files to a different directory. No additional space is consumed on a disk
during renaming. This command normally works silently means no prompt for confirmation.

rm: The rm command removes the entries for a specified file, group of files, or certain select files
from a list within a directory. User confirmation, read permission, and write permission are not
required before a file is removed when we use the rm command. However, we must have written
permission for the directory containing the file.

chmod: the chmod command is used to change the access mode of a file. The name is an
abbreviation of change mode. The references are used to distinguish the users to whom the
permissions apply i.e., they are list of letters that specifies whom to give permissions that is shown
in table 1.1. In table 1.2 it shows class like owner, group and others and in table 1.3 is the operator
used in chmod command.

head: The head command is a command-line utility for outputting the first part of files given to
it via standard input. It writes results to standard output. By default, head returns the first ten lines
of each file that it is given. The 'head -n' option displays specified number of lines.

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tail: Linux tail command is used to display the last ten lines of one or more files. Its main purpose
is to read the error message. By default, it displays the last ten lines of a file. Additionally, it is
used to monitor the file changes in real-time. It is a complementary command of the head command.

The 'tail -n' option displays specified number of lines.

Table 1.1 Chmod Permission and its Description

Operator Description

+ Adds the specified modes to the specified classes

- Removes the specified modes from the specified classes

= The modes specified are to be made the exact modes for the specified classes

Table 1.2 Chmod Class and its Description

Permissions Descriptions

R Permission to read the file

w Permission to write (or delete) file

x Permission to execute the file, or, in the case of a directory, search it.

Table 1.3 Chmod Operator and Description

Reference Class Description

u Owner/user File’s owner

g Group Users who are members of the file’s group

o Others Users who are neither the file’s owner nor members of the
file’s

a All All three of the above, same as ugo

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soft link and hard link: The ln command is used to create links between files. Basically, ln
command is used to create hard links and soft links for files in Linux. s option will creates a
symbolic link. Symbolic links make it easy to make some set of files appear to exist in multiple
locations without having to make separate copies. Hard links are most useful for keeping file
content in a single location by avoiding duplication of what might be a very large amount of data.

cal: cal command is a calendar command in Linux which is used to see the calendar of a specific
month or a whole year. By default, the cal command shows the current month calendar as output.

Table 1.4 Basic Linux Commands

Command Description
Date Used to display the system date and time
Cal Used to see the calendar of a specific month or a whole year
Whoami It displays the username of the current user when this command
is invoked
Pwd Prints the current working directory path, starting from the root
(/)
Cd Used to change the current working directory in Linux
Ls Lists information about directories and any type of files in the
working directory.
Mkdir Allows users to create or make new directories. mkdir stands for
“make directory
Rmdir Used to remove empty directories from the filesystem in Linux
Touch Used to create a file
Rm Removes each file specified on the command line
Cat Used to print content of a file onto the standard output stream
Chmod Allows you to change the permissions on a file using different
methods
Passwd Changes password for user accounts
Users Print all the user’s username
Useradd Used for adding/creating user accounts

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 1.7 VIM Commands

˃ Vi filename – opens file in vim editor

˃ :w – saves the file
˃ :q – it quits if there is no change in file
˃ :wq – it saves and quits the file
˃ :q! – it forcefully quits without saving the file
˃ :wq! – it forcefully saves and quits the file(if there is no write permission)
˃ i – insert mode (for insert any text)
˃ Shift + i – insert mode at the start of the line
˃ o - Add line after and will be in insert mode
˃ O - Add line before and will be in insert mode
˃ a - Move one character right and come into insert mode (Append after cursor position)
˃ Shift + a - Move at the end of the line and come into insert mode (Append at end of line)
˃ Shift + x – deletes character
˃ dw – deletes word
˃ dd – deletes entire line
˃ :2,5d – deletes from line 2 to 5
˃ Shift + d - Deletes line after cursor
˃ cw - Deletes word and come in to insert mode (change word)
˃ cc – Delete line and come in to insert mode (change line)
˃ Shift + c - Delete line from cursor position and come in to insert mode
˃ u – to undo last action
˃ gg - Go to the top of the file
˃ Shift + g - Go to the end of the file
˃ Shift + a - Go to end of line with insert mode
˃ $ - Go to the end of the line
˃ 0 or ^ - Go to the start of the line
˃ k – moves cursor upside
˃ j – moves cursor downside
˃ h – moves cursor leftside

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˃ l – moves cursor rightside
˃ /str - for str search in file (go to next search press n, go to previous search press Shift + n)
˃ :%s/str1/str2/g - Substitute at str1 with str2 in line
˃ :1,5s/str1/str2/g - Substitute at str1 with str2 in lines 1 to 5
˃ :%s/str1/str2/c - Substitute at str1 with str2 in line with confirmation
˃ :1,5s/str1/str2/gc - Substitute at str1 with str2 in lines 1 to 5 with confirmation
˃ :set nu - Show line number
˃ :set nonu - Remove line number
˃ :new file name - Open a new file in below the old file
˃ :vert new file_name - Open a new file in beside a old file
˃ Gvim file_1 file_2 –p - Will open all files in same tab
˃ yy – for copy
˃ p – for pasting after cursor
˃ Shift + p – for pasting before cursor
˃ r - Will replace single character
˃ Shift + r - Will allow to replace from cursor position

1.8 Advance Commands

1.8.1 Grep Command

Linux has a special family of command for handling search requirements, and the principal
member of this family is the grep command. grep scans its input for a pattern and displays
lines containing the pattern, the line numbers or filenames where the pattern occurs. The grep
filter searches a file for a particular pattern of characters and displays all lines that contain
that pattern. The pattern that is searched in the file is referred to as the regular expression
(grep stands for globally search for regular expression and print out). The command uses the
following syntax: grep options pattern filename(s)

The first argument is the pattern and remaining arguments are filenames.

˃ Grep - Use to search pattern into the file or output

˃ -c - This prints only a count of the lines that match a pattern

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˃ -h - Display the matched lines, but do not display the filenames.
˃ -l - Displays list of a filenames only.
˃ -n - Display the matched lines and their line numbers.
˃ -v - This prints out all the lines that do not matches the pattern
˃ -w - Match whole word
˃ -o - Print only the matched parts of a matching line, with each such part on a separate output
line.
˃ -An - Prints searched line and nlines after the result
˃ -Bn - Prints searched line and nlines before the result
˃ -Cn - Prints searched line and nlines after before the result
˃ Grep –E – It is used to grep multiple words from the file
˃ [#] – Search for commented lines and print it
˃ ^[^#] – Search for un-commented lines and print it
˃ find –name – Will search in present directories and sub directories

Figure 1.3 Execution of grep (switches) command

1.8.2 SED Command

sed command in UNIX stands for stream editor and it can perform lots of functions on file like
searching, find and replace, insertion or deletion. Though most common use of sed command
in UNIX is for substitution or for find and replace. By using sed, you can edit files even without
opening them, which is much quicker way to find and replace something in file, than first
opening that file in VI Editor and then changing it.
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• sed is a powerful text stream editor. Can do insertion, deletion, search

and replace(substitution).

• sed command in unix supports regular expression which allows it perform

complex pattern matching.

-n ‘2p’ <file> - Print the second line

-n ‘$p’ <file> - Print last line from <file>

-n ‘2,4p’ <file> - Print the specified range of line from <file>

-n ‘2p;4p’ <file> - Print only 2nd and 4th line from <file>

‘s/str1/str2/’ <file> - Print lines by replacing str1 with str2 from <file> first occurrence only.

‘s/str1/str2/g’ <file> - Print lines by replacing str1 with str2 from <file> all occurrences.

-e ‘s/str1/str2/’ -e ‘s/str3/str4/’ <file> - Multiple string replace

‘5d’ <file> - Print after deleting 5th row from <file>

‘5,7d’ <file> - Delete range of lines

-i ‘s/str1/str2/g’ <file> - Perform change in the original file <file>

‘5i str’ <file> - Adds str before line 5 and display

‘5a str’ <file> - Adds str after line 5 and display

Figure 1.4 Execution of sed (switches) command

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1.8.3 CUT Command

The cut command in UNIX is a command for cutting out the sections from each line of files
and writing the result to standard output. It can be used to cut parts of a line by byte position,
character and field. Basically, the cut command slices a line and extracts the text. It is necessary
to specify option with command otherwise it gives error. If more than one file name is provided,
then data from each file is not precedes by its file name.

The cut command in UNIX is a command for cutting out the sections from each line of files
and writing the result to standard output. It can be used to cut parts of a line by byte position,
character and field. Basically, the cut command slices a line and extracts the text

Table 1.5 cut command

1.8.4 AWK Command

awk is a scripting language tool used for manipulating data and generating reports. The awk
command programming language requires no compiling and allows the user to use variables,
numeric functions, string functions, and logical operators.

Awk is a utility that enables a programmer to write tiny but effective programs in the form of
statements that define text patterns that are to be searched for in each line of a document and
the action that is to be taken when a match is found within a line.

awk is mostly used for pattern scanning and processing. It searches one or more files to see if
they contain lines that match the specified patterns and then perform the associated actions.

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1.9 Shell Scripting
Shells accept command as input from users and execute them. Till now we have seen that we
were writing the commands in linux terminal, and we were getting the output on the terminal.
There are some tasks that need to be performed again and again, or we need to use a bunch of
commands. In this case, we need to use shell scripting. A set of commands to perform a task is
called shell script. Shell script is a computer program designed to be run by Unix/Linux shell.
All the commands are executed sequentially. Some tasks like manipulation, program
execution, user interaction, automation of task etc. can be done using shell script.

1.9.1 Uses of Shell

Script Shell script is useful for repetitive tasks that may be time consuming to execute by typing
one line at a time.

These tasks may include:

• Commands that we need to execute frequently

• Manipulating files

• System admins use shell scripting for routine backups

• System monitoring

Advantages:

• Simple and efficient

• Same syntax as CLI

• Interactive Debugging

Disadvantages:

• Prone to errors

• Slow execution speed

• Not well suited for large and complex tasks

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• Compatibility problem

1.9.2 Creating a Shell Script

First, we need to create a file with extensions .sh. Then in the file, we need to write a shebang
(#!) character followed by /bin/bash. The shebang is the program loader's first instruction when
executing the file, and the characters indicate which interpreter to run when reading the script.

#! directs the program loader to load an interpreter for the code in the file. /bin/bash the Bash
interpreter's location. The comments start with '#' symbol.

To run the shell script

• The file must have execute permissions.

• The script can be run in command line using sh filename or ./filename.

1.9.3 Shell Scripting Commands

Table 1.6 Shell Scripting Argument Commands

Commands / Description / Use

Symbol

# Use to add comment in shell script echo Use to print data on

Terminal

$var Use to call variable in shell script ($)

read Use to read data entered by user in Terminal

$# Use to show total number of Arguments used in shell script

$1, $2, …, $9 Arguments can be used in shell script (can be called by $n)

If-else Conditional handling

If-elif-else Conditional handling multiple

; Use end the statement and you can write another command in same
line

str1 = str2 Use for string comparison operation (str1 equal to str2)

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 str1 != str2 Use for string comparison operation (str1 not equal to str2)

n1 -eq n2 Use for numeric comparison operation (n1 equal to n2)

n1 -ne n2 Use for numeric comparison operation (n1 not equal to n2)

n1 -gt n2 Use for numeric comparison operation (n1 greater than n2)

n1 -ge n2 Use for numeric comparison operation (n1 greater than or equal to
n2)

n1 -lt n2 Use for numeric comparison operation (n1 less than n2)

n1 -le n2 Use for numeric comparison operation (n1 less than equal to n2)

|| Logical OR condition

&& Logical AND condition

$? Store the return value of function

1.9.4 While Loop

The while loop enables you to execute a set of commands repeatedly until some condition
occurs. It is usually used when you need to manipulate the value of a variable repeatedly.
Syntax:

while [ condition ]; do

# statements # commands

Done

1.9.5 If-Elif-Else Statement

It is a control statement, and it Allows shell to make correct decision out of several conditions.

Syntax:

if [ expression1 ] then
statement1

elif [ expression2 ] then

else fi

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1.9.6 For Loop
The for loop operate on lists of items. It repeats a set of commands for every item in a list.

Syntax: for variable in 1 2 3 4 5 .. N do

command1

command2

command
done

1.9.7 Case Statement

Case statement in shell scripts is used when a decision has to be made against multiple choices.
In other words, it is useful when an expression has the possibility to have multiple values. This
methodology can be seen as a replacement for multiple if-statements in a script.

Syntax:
case EXPRESSION in

Pattern_Case_1) STATEMENTS;;

Pattern_Case_2) STATEMENTS;;

Pattern_Case_N) STATEMENTS;;

*) STATEMENTS;;

esac

1.9.8 Functions
A function is a collection of statements that execute a specified task. Its main goal is to break
down a complicated procedure into simpler subroutines that can subsequently be used to
accomplish the more complex routine. Functions can accept arguments, perform operations,
and return a value. There are two types of functions in shell scripting: functions with arguments
and functions without arguments. Also, there are functions that return a value.

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Figure 1.21 Function in Shell Script

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 CHAPTER 2

PERL SCRIPTING

2.1 Objective of using Perl

Perl is a scripting language that is commonly used in various fields, including VLSI (Very
Large-Scale Integration) design. In VLSI, Perl is used for a variety of tasks, including:

• Design automation: Perl scripts can automate repetitive tasks in VLSI design, such as layout
generation, netlist parsing, and verification.

• Simulation and analysis: Perl scripts can be used to analyze and simulate VLSI designs, such
as timing analysis and power analysis.

• Data processing: Perl can be used for processing and manipulating large volumes of data
generated by VLSI tools and simulations.

• Customization: Perl can be used to customize VLSI tools and flows, allowing designers to
create their own design and analysis environments.

The objective of using Perl in VLSI is to improve the efficiency and accuracy of the design
process. By automating repetitive tasks, analyzing designs, and processing data more
effectively, designers can create better designs in less time. Perl's flexibility and ability to
integrate with other tools make it a popular choice in the VLSI community.

Perl was designed to make the process of extracting, manipulating, and reporting on text-based
data more efficient and straightforward. Its syntax is concise and expressive, making it ideal
for tasks such as text processing, system administration, web development, and more.

2.2 Introduction

Perl is a high-level, interpreted programming language that was first developed by Larry
Wall in 1987. Perl is a general-purpose language that can be used for a wide range of tasks,
from simple text manipulation to web development and network programming. Perl is known
for its flexibility, power, and expressiveness, as well as its strong support for regular
expressions and string manipulation.

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Perl has a large and active community of users and developers, who have created a vast
collection of modules and libraries that can be used to extend the language and add new
features. Perl is widely used in the world of web development, particularly in the creation of
CGI scripts, and it is also popular in system administration and automation tasks.

Perl code is typically written in plain text files and is then interpreted by the Perl interpreter.
Perl is available on a wide range of platforms, including Windows, macOS, Linux, and many
other Unix-like systems.

Figure 2.1 Basic Perl Interpreter

• Perl is a high-level, general-purpose, interpreted, dynamic programming language. It was

introduced by Larry Wall in 1987. Perl language was specially designed for text editing.

• It is widely used for a variety of purposes including Linux system administration, network
programming, web development, etc.

• Perl is an interpreted language, which means that your code can be run as is, without a
compilation stage that creates a non-portable executable program.

2.2.1 Benefits of Perl:

• Automation of the things done in computer system related to job.

• PERL or Python can be used to make these efficient.

• Every job across domains has some kind of repetitive work, that needs to be done manually.
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• PERL can automate all these aspects, so that we can spend time on other important aspects
of the job. Checking the testcase pass/fail status makes report out of it in different formats like
xls, html, word, etc.

• Reduce manual effort, human errors.

• Scripts are reusable.

• There is huge resource of PERL modules (pre-implemented libraries) which makes it easy to
any kind of jobs across different work domains (VLSI/Embedded/Software/etc).

• Generating complete Test Bench (TB) using a spreadsheet input.

• We get an XLS with design block name, interface names, type of interface clock name, and
clock frequency. Using this we can generate complete TB.

• Setting up Regression, analyzing regression outputs, creating report.

• Generating register model (SV & UVM) using spreadsheet input.

• In SOC verification, map tarmac.log with MPF file and come up with a log file which, details
the C code that is executing at a specific time.

• Front end RTL/Testbench code compilation and simulation flows.

• Running tests in regressions, analyzing failures, debug automation.

• Connectivity checks , netlist parsing, automatic generation/modification any RTL

module/stubs etc.

• Synthesis, P&R tools interfacing and back end flow.

• Several project management utilities - regression pass rates, trends, bug charts etc - that helps
in tracking projects.

• Anything else that is repetitive and can be automated.

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2.2.2 Applications of Perl Language for VLSI:

Figure 2.2 Perl application

2.3 Features

Powerful regular expression supports pattern matching and substitution.

Extensive built-in library of functions and modules for various tasks.

• Platform independence, making it suitable for cross-platform development.

• Object-oriented programming features for creating reusable and modular code.

• Comprehensive documentation and a large community of users and contributors.

2.4 Perl Basics

There are two ways of running a Perl script: at the command line and from a text file. For very
short scripts, you can just type the whole program at the command line and watch the computer
run it. For longer scripts (and ones you would like to reuse), you create a plain-text document
with the program code and then tell the Perl interpreter to run this program, usually on the
command line.

Perl scripts/programs are plain-text documents (generally ASCII), usually with the extension
.pl, though this isn't strictly necessary. You can write scripts in any word processor, though I
recommend that you not use MS Word or another processor that by default saves documents
in some binary (i.e., non-plain text) format.

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2.4.1 Perl Shebang:

• The #! syntax is used in scripts to indicate an interpreter for execution under UNIX / Linux
operating systems.

• The directive must be the first line in the Linux shell script and must start with shebang #!.

• You can add argument after the shebang characters, which is optional. Make sure the
interpreter is the full path to a binary file. For example: /bin/bash.

• This is not necessary on many systems, but when it is, it is, so it's a good habit to get into.
The purpose of this line is to tell the server which version of Perl to use, by pointing to the
location in the server directory of the Perl executable.

2.4.2 Single and Double Quotes in Perl:

There is an important difference in single and double quotes. Only double quotes interpolate
variables and special characters such as newlines \n, whereas single quote do not interpolate
any variable or special character. Check below example where we are using $a as a variable to
store a value and later print that value.

Example 1:

#!/usr/bin/perl

$a = 10;

print “VLSI Society of India\n";

print ‘VLSI Society of India= $a\n';

Figure 2.3 Basic Perl Script with quotes operation

24
return; for Perl it is the semicolon. All lines of code in Perl must end with one of the two things:
a semicolon or curly braces.

The identification of perl scripts can be done using the file extension. The files having
extension of .pl and .pm are an example of perl scripts.

2.5 Data Types

Perl is a loosely typed language and there is no need to specify a type for your data while using
it in your program. The Perl interpreter will choose the type based on the context of the data
itself.

Perl has three basic data types: scalars, arrays of scalars, and hashes of scalars, also known as
associative arrays. Here is a little detail about these data types.

• Scalar: Scalars are simple variables. They are preceded by a dollar sign ($). A scalar is either
a number, a string, or a reference.

• Arrays: Arrays are ordered lists of scalars that you access with a numeric index, which starts
with 0. They are preceded by an "at" sign (@).

• Hashes: Hashes are unordered sets of key/value pairs that you access using the keys as
subscripts. They are preceded by a percent sign (%)

2.5.1 Scalar

A scalar is a single unit of data. That data might be an integer number, floating-point, a
character, a string, a paragraph, or an entire web page. Simply saying it could be anything, but
only a single thing.

String Operations:-

2.5.1.1 Concatenation

To concatenate the string use dot(.) operator. In the following example we are concatenating

three strings, $str1, white space and $str2.

25
$str1 = “eitra";

$str2 = “einfochips";

$mystr= $str1 . " " . $str2;

print "$mystr\n";

Output: eitra einfochips

2.5.1.2 Repetition:

$str = "Cherry";

$mystr = $str x 4;

print "$mystr\n";

Output: CherryCherryCherryCherry

2.5.1.3 Getting the substring – substr() function:

The substr() function is used for getting a substring from a given string.

# This is our original string

my $str = "I know who you are, I will find you";

print "My original String is: $str\n";

# substring -starting from 8th char till the end of string

my $substr1 = substr($str, 7);

print "My First substring is: $substr1\n";

# substring -starting from 8th char and length of 11

my $substr2 = substr($str, 7, 11);

print "My Second substring is: $substr2\n";

26
 Figure 2.4 Perl Script for Substring

2.5.1.4 String replace:

This same function can be used for replacing a part of string with the new content. Lets take
an example to understand this:

# This is our original string

my $str = "I know who you are, I will find you";

print "My original String is: $str\n";

my $newstr= substr($str, 7, 11, "you are the killer");

print "My updated String is: $str\n";

Figure 2.5 Perl Script for String Replace

2.5.1.5 Length of string :

my $str = "I know who you are, I will find you";

print "length of string is:", length($str);

27
2.5.1.6 String comparison:

my $str = "hello";

my $str2 = "hello";

if ($str eq $str2){

print "str and str2 are same\n";

Output:

str and str2 are same

2.5.1.7 Conversion Between Numbers and Strings:

$string = "43";

$number = 28;

$result = $string + $number;

print $result;

Output:

71

• Value of $string is converted to an integer and added to the value of $number.

• Result of the addition, 71, is assigned to $result.

• Scope of a variable –Access Modifiers

• Declare a scalar in anywhere in the program. But need to specify an access modifier

28
2.5.2 Perl – Arrays

• An array is a variable that stores an ordered list of scalar values.

• Array variables are preceded by an "at" (@) sign.

• To refer to a single element of an array, you will use the dollar sign ($) with the variable
name followed by the index of the element in square brackets.

Example 1:

#!/usr/bin/perl

@ages = (21, 22, 23);

@names = ("mitul", "kiran", "disha");

print "\$ages[0] = $ages[0]\n";

print "\$ages[1] = $ages[1]\n";

print "\$ages[2] = $ages[2]\n";

print "\$names[0] = $names[0]\n";

print "\$names[1] = $names[1]\n";

print "\$names[2] = $names[2]\n";

Figure 2.6 Perl Script for Array

29
2.5.2.1 Sequential Arrays:

Sequential arrays are those where you store data sequentially. Suppose you want to store 1-10
numbers or alphabets a-z in an array. Instead of typing all the letters, you can try something
like below

@numbers= (1..10);

print @numbers;

print "\n";

@char=(a..z);

print @char;

Output:

12345678910

abcdefghijklmnopqrstuvwxyz

Arrays Size:

$size = @array;

Print $size

2.5.2.2 Push, Pop, shift, unshift for Perl arrays:

These functions can be used in Perl to add/delete to array elements.

Perl Push: adds array element at the end of an existing array.

Perl Pop: removes the last element from an array.

Perl Shift: removes the first element from an array.

Perl Unshift: adds an element at the beginning of an array.

30
2.5.2.3 Slicing Array Elements:

You can also extract a "slice" from an array - that is, you can select more than one item from

an array in order to produce another array.

#!/usr/bin/perl

@days = qw/Mon Tue Wed Thu Fri Sat Sun/;

@weekdays = @days[3,4,5];

print "@weekdays\n";

Output:

Thu Fri Sat

2.5.2.4 Splice Array Elements

Figure 2.7 Perl Script for Array with Splice

Figure 2.8 Perl Array Output

31
2.5.3 Hash

A hash is a set of key/value pairs. Hash variables are preceded by a percent (%) sign. To refer
to a single element of a hash, you will use the hash variable name followed by the "key"
associated with the value in curly brackets.

Figure 2.9 Perl Script for Hash

Figure 2.10 Perl Hash Output

2.6 Conditional Statements:

Perl conditional statements help in the decision making, which require that the programmer
specifies one or more conditions to be evaluated or tested by the program, along with a
statement or statements to be executed if the condition is determined to be true, and
optionally, other statements to be executed if the condition is determined to be false. The
number 0, the strings '0' and “”, the empty list () , and undef are all false in a Boolean context
and all other values are true. Negation of a true value by ! or not returns a special false value.

32
If…else statement:

An if statement consists of a Boolean expression followed by one or more statements.

Figure 2.11 Perl Conditional Statement block diagram

Figure 2.12 Perl If-Else Conditional Statement

Figure 2.13 Perl If-Else output

unless...else statement:

An unless statement consists of a Boolean expression followed by one or more statements.

(Opposite of ‘if else’ statements).

33
 Figure 2.14 Perl Unless-Else Conditional Statement

Figure 2.15 Perl Unless-Else Output

switch statement:

switch statement: A switch statement allows a simple way of comparing a variable value
against various conditions.

2.7 Control Loops in Perl

A loop statement allows us to execute a statement or group of statements multiple times and
following is the general form of a loop statement in most of the programming languages.

Figure 2.16 Perl Control loops block diagram

34
2.7.1 While Loop

A while loop statement in the Perl programming language repeatedly executes a target

statement as long as the given condition is true.

Syntax:

while(condition)

statement(s);

Here statement(s) may be a single statement or a block of statements. The condition may be
any expression. The loop iterates while the condition is true. When the condition becomes
false, program control passes to the line immediately following the loop.

Figure 2.17 Perl While and Until loop

Figure 2.18 Perl while & Until loop output

35
 Figure 2.19 Perl Do while and Do Until loop

Figure 2.20 Perl Do while and Do Until loop Output

2.7.2 For and foreach loop

Figure 2.21 Perl For loop

Figure 2.22 Perl For loop Output

36
For each statement can be used in the same way as for; the main difference is we don’t have
any condition check and incrementing in this.

Figure 2.23 Perl Foreach loop Output

Figure 2.24 Perl Foreach loop Output

2.8 Operator

Table 2.1 symbols of Perl

37
2.8.1 Ternary operator

Figure 2.25 Perl Ternary operator

Figure 2.26 Perl Ternary Operator Output

Example:

my $x=10;

my $y=2;

my $z;

$z=$x+$y;

print ("Add of $x and $y is $z \n");

$z=$x-$y;

print ("Sub of $x and $y is $z \n");

$z=$x*$y;

print ("Mul of $x and $y is $z \n");

$z=$x/$y;

print ("Div of $x and $y is $z \n");

$z=$x**$y;

print ("Exp of $x and $y is $z \n");

$z=$x%$y;
38
print ("Mod of $x and $y is $z \n");

Figure 2.27 Perl Ternary Operator Output

2.8.2 Logical & bit-wise operators:

Figure 2.27 Perl Logical & bitwise operator

Figure 2.28 Perl Logical & bitwise operator Output

39
2.9 Regular Expressions

Perl regular expression is strong enough in matching the string patterns within a statements
or group of statements.

A regular expression is a string of characters that defines the pattern or patterns you are

viewing. The syntax of regular expressions in Perl is very similar to what you will find
within other regular expression supporting programs, such as sed, grep, and awk.

The basic method for applying a regular expression is to use the pattern binding operators =~
and !~. The first operator is a test and assignment operator.

Regular expressions are mostly used in text parsing, pattern matching and much more based
on the requirement.

There are three regular expression operators within Perl:

• Match Regular Expression - m//

• Substitute Regular Expression - s///

• Translate Regular Expression - tr///

The forward slashes in each case act as delimiters for the regular expression (regex) that we
are specifying. We can also use any other delimiter in place of forward slash.

2.9.1 Match Operator:

The match operator, m//, is used to match a string or statement to a regular expression. We can
use any combination of naturally matching characters to act as delimiters for the expression.
For example, m{}, m(), and m>< are all valid. We can omit m from m// if the delimiters are
forward slashes, but for all other delimiters we must use the m prefix.

The entire match expression, that is the expression on the left of =~ or !~ and the match

operator, returns true (in a scalar context) if the expression matches

The match operators are used to match a string within some statement or in a variable.

40
my $var="Hello this is perl";

if($var=~m/perl/){

print "true";

} else{

print "False";

Output: True

2.9.2 Substitution Operator:

This operator can be used for searching and replacing any character with either null or some
other character.

#!/bin/perl

my $str="Einfochips pvt. Ltd. is University";

$str=~s/University/Service base company/gi;

print "$str\n";

Figure 2.29 Perl Substitute Operator Output

2.9.3 Translation Operator:

This is similar to Substitution, but it does not use any perl regular expressions, rather we can
directly pass the value or a word which we want to replace.

#!/bin/perl

my $str=10001;

$str=~tr/0/1;

print "$a\n";

41
Output:

11111

2.10 File handling

n Perl, file handling is the process of creating, reading, writing, updating, and deleting files.
Perl provides a variety of built-in functions and modules that make it easy to work with files.

Here’s an introduction to file handling in Perl:

File modes:

When opening a file in Perl, you need to specify a file mode, which determines how the file
can be accessed. There are three main file modes:

1. Read mode (<): Opens the file for reading. The file must already exist.

2. Write mode (>): Opens the file for writing. If the file does not exist, it will be created.

If the file already exists, its contents will be truncated.

3. Append mode (>>): Opens the file for writing, but appends new data to the end of the

file instead of overwriting its contents. If the file does not exist, it will be created.

File handling functions:

Here are some of the most commonly used built-in file-handling functions in Perl:

1. open(): Opens a file and returns a file handle.

2. close(): Closes a file handle.

3. print(): Writes data to a file.

4. read(): Reads data from a file.

5. seek(): Moves the file pointer to a specific location in the file.

6. tell(): Returns the current position of the file pointer.

7. stat(): Returns information about a file, such as its size, owner, and permissions.
42
 Table 2.2 file handling operator

Read:

Figure 2.30 Perl Read Operation

Figure 2.31 Perl Read Operation Output

Write:

43
 Figure 2.32 Perl Write Operation

Figure 2.33 Perl Write Operation Output

append:

Figure 2.34 Perl Append Operation

Figure 2.35 Perl Append Operation Output

read-write:

Figure 2.36 Perl Read-Write Operation

44
 Figure 2.37 Perl Read-Write Operation Output

read-append:

Figure 2.38 Perl Read-Append Operation Output

Figure 2.39 Perl Read-Append Operation Output

2.11 Command Line Arguments

• Command-Line arguments are inputs to the program, provided by the user on program

execution.

• Perl has a special array @ARGV that contains the list of command-line arguments

given to the program at execution.

• script to add, multiple and divide using CLA.

#!/bin/perl

45
$sum=0;

$mul=1;

$div=1; $sum=$ARGV[0]+$ARGV[1]; print "sum is $sum\n";

$mul=$ARGV[0]*$ARGV[1]; print "multiplicaton is $mul\n"; $div=$ARGV[0]/$ARGV[1];
print "Division is $div\n";

Output

Figure 2.40 Perl Read-Append Operation Output

Subroutine, Module and Packages

2.11.1 Subroutine:

• A Perl function or subroutine is a group of statements that together perform a specific task.

• So the user puts the section of code in function or subroutine so that there will be no need to
write code again and again.

• In Perl, the terms function, subroutine, and method are the same but in some programming
languages, these are considered different.

• The word subroutines is used most in Perl programming because it is created using

keyword sub.

• Whenever there is a call to the function, Perl stop executing all its program and jumps to the
function to execute it and then returns back to the section of code that it was running earlier.
One can avoid using the return statement.

perl subroutine to calculate square of a:

#!/bin/perl

sub multi

{
46
$res=$_[0];

$square=$res*$res;

print "$square\n";

multi(3);

Output:

2.11.2 PERL Modules

• A module in Perl is a collection of related subroutines and variables that perform a set

of programming tasks.

• Various Perl modules are available on the Comprehensive Perl Archive Network

(CPAN).

• These modules cover a wide range of categories such as network, CGI, XML

processing, databases interfacing, etc.

2.11.3 PERL Packages

• Perl package is a collection of code which resides in its own namespace.

• Perl module is a package defined in a file having the same name as that of the package and
having extension .pm.

• Two different modules may contain a variable or a function of the same name.

• Any variable which is not contained in any package belongs to the main package.

• Therefore, all the variables being used, belong to the ‘main’ package. With the declaration
of additional packages, it is maintained that variables in different packages do not interfere
with each other.

Example: PERL module to calculate average of two numbers.

47
Perl Module:

#!/bin/perl package avg;

sub average

$num1=$_[0];

$num2=$_[1];

$avg=($num1+$num2)/2;

print "average value is :$avg\n";

1;

Main file:

#!/bin/perl use avg;

$a=5;

$b=35;

avg::average($a,$b);

Output:

average value is : 2

48
 CHAPTER 3
VERILOG
3.1 Introduction
Verilog, an influential hardware description language (HDL), has become an essential tool
for engineers and designers working in digital design. Originating in the mid-1980s, it has
since established itself as an industry standard for modeling and simulating digital systems,
contributing significantly to the design and verification of complex integrated circuits and
digital systems. The primary purpose of Verilog lies in facilitating the description, modeling,
and simulation of digital circuits at various levels of abstraction. This encompasses
everything from high-level behavioral modeling to low-level gate-level implementation,
allowing designers to express complex hardware functionalities and behaviors effectively.
Verilog's key features include its inherent concurrency, enabling multiple statements and
processes to execute simultaneously, and its support for modularity through the use of
modules. Modules encapsulate reusable hardware components, promoting hierarchical design
and facilitating the creation of complex systems by composing smaller, reusable building
blocks. Furthermore, Verilog supports both behavioral and structural modeling paradigms,
allowing designers to describe system functionality using procedural constructs and
interconnect hardware components explicitly. In terms of verification, Verilog's simulation
capabilities are crucial for ensuring correctness, functionality, and performance before
physical implementation.
Its widespread adoption spans across ASIC and FPGA design, digital system design in
various sectors like telecommunications and consumer electronics, as well as its use in
education and research for teaching digital design concepts and conducting research in areas
such as computer architecture and embedded systems. In essence, Verilog remains a pivotal
language in the digital design domain, continuing to drive advancements in technology and
innovation within the electronics industry.

49
3.2 Verilog basic
Verilog Notation:
1. Verilog is:
• Case sensitive
• Based on the programming language C

2. Comments:
• Single Line // [end of line]
• Multiple Line /* */
3. List element separator: (,)
4. Statement terminator: (;)
5. Binary Values for Constants and Variables:
• 0
• 1
• X,x - Unknown
• Z,z – High impedance state (open circuit)
6. Identifier Examples:
• Scalar: A, C, RUN, stop, m, n
• Vector: sel[0:2], f[0:5], ACC[31:0], SUM[15:0]
7. Constants:
• n’b[integer]:
1’b1 = 1;
8’b1 = 000000001,;

• n’h[integer]:
8’hA9 = 10101001;
16’hf1 = 0000000011110001; Verilog Operators:
Verilog has three operator types Unary, Binary, and Ternary.
1. Unary: Appear before the operand. Ex. Y = ~x;
2. Binary: Appear between two operands. Ex. Y = x || y
3. Ternary: Two separate operators appear to separate three operands Ex. Z = (a < b) ? x
: y;

50
3.3 Data Type
Value Set:
Verilog supports four values and eight strengths to model the functionality of real hardware.
The four value levels are listed in given table:
Table 3.1 Values use by Identifier
Value Level Condition in Hardware Circuits

0 Logic zero , false condition

1 Logic one , true condition
x Unknown logic value
z High impedance, floating state

Strength Levels:
In addition to logic values, strength levels are often used to resolve conflicts between drivers
of different strengths in digital circuits. Value levels 0 and 1 can have the strength levels
listed in given table.
Table 3.2 Strength Level
Strength Level Type Degree

supply Driving strongest

strong Driving

pull riving

large Storage

weak Driving

medium Storage

small Storage

highz High Impedance weakest

If two signals of unequal strengths are driven on a wire, the stronger signal prevails. For
example, if two signals of strength strong1 and weak0 contend, the result is resolved as a
51
 strong1. If two signals of equal strengths are driven on a wire, the result is unknown. If two
signals of strength strong1 and strong0 conflict, the result is an x.
1. Nets:
• Nets represent connections between hardware elements. Just as in real circuits, nets
have values continuously driven on them by the outputs of devices that they are connected to.
• Nets are declared primarily with the keyword wire.
Ex. wire a; //one-bit value as a single net.
wire [5:0] a; //net as a vector.

2. Reg:
• Registers represent data storage elements. Registers retain value until another value is
placed onto them.

• means a variable that can hold a value. Unlike a net, a register does not need a driver.
Values of registers can be changed anytime in a simulation by assigning a new value to the
register.
Ex. reg reset; // declare a variable reset that can hold its value

3. Vectors:
• Nets or reg data types can be declared as vectors (multiple bit widths). If bit width is not specified,
the default is scalar (1-bit).
Ex. wire a; // scalar net variable, default 1 bit wire [7:0] bus; // 8-bit bus reg [0:40]
virtual_addr; // Vector register, virtual address 41 bits wide

4. Integer:
• An integer is a general purpose register data type used for manipulating quantities.
• Integers are declared by the keyword integer.
• The default width for an integer is the host-machine word size, which is
implementation-specific but is at least 32 bits.
• Registers declared as data type reg store values as unsigned quantities, whereas integers
store values as signed quantities.
Ex.

52
 Integer counter; //integer counter of 32 bit

5. Real:
• Real number constants and real register data types are declared with the keyword real.
They can be specified in decimal notation (e.g., 3.14) or in scientific notation (e.g., 3e6, which
is 3 x 106 ). Real numbers cannot have a range declaration, and their default value is 0. When
a real value is assigned to an integer, the real number is rounded off to the nearest integer.
Ex.
real delta=3.4; //to store real values

6. Time:
• Verilog simulation is done with respect to simulation time.
• A special time register data type is used in Verilog to store simulation time. A time
variable is declared with the keyword time.
• `timescale is a compiler directive in Verilog.
• Timescale specifies the time unit and time precision of a module that follow it.
`timescale 1ps / 1ps Ex.
`timescale 1ns/1ps Module timescale_check1; reg[31:0]rval; initial begin rval=20;
#10.566601 rval=10;
#10.980003 rval=55;
#15.674 rval=0;
#5.0000001 rval=250;
#5.67891224 rval=100; end
initial begin
$monitor("TimeScale1ns/1ps:Time=%0t,rval=%d\n",$realtime,rval);
#100;
$finish; end endmodule

53
 Fig 3.1 Output Of Data type $time

7. Array:
• Arrays are allowed in Verilog for reg, integer, time, real, realtime and vector data types.
• Multi-dimensional arrays can also be declared with any number of dimensions.
• Arrays of nets can also be used to connect ports of generated instances.
• Each element of the array can be used in the same fashion as a scalar or vector net.
• Arrays are accessed by <array_name> [<subscript>]. For multi-dimensional arrays,
indexes need to be provided for each dimension.

Some examples of declaration of an array

1. integer //An array of 8 count variables
count[0:7];
2. reg bool[31:0]; //Array of 32 one-bit Boolean
register variables
3. time //Array of 100 time checkpoint
chk_point[1:100]; variables
4. reg [4:0] //Array of 8 port_ids; each
port_id[0:7]; port_id is 5 bits wide
5. integer //Two dimensional array of
matrix[4:0][0:255]; integers
6. wire [7:0] //Declare an array of 8 bit vector
w_array2 [5:0]; wire
7. wire //Declare an array of single bit
w_array1[7:0][5:0]; wires

8. Strings:
• A string is a set of characters that are typically mentioned within double-quotes (” “).

54
• Each character in a string requires 1 byte to store.
• Strings can be stored in reg.
• The width of the register variables must be large enough to hold the string.
• If the width of the register is greater than the size of the string, Verilog fills bits to the
left of the string with zeros.
Ex. reg [8*18:1] string_value; // Declare a variable 18 bytes wide Initial begin string_value =
"Hello Verilog World"; // String can be stored

3.4 Operators in Verilog:

Operators are of three types, unary, binary, and ternary. Unary operators precede the operand.
Binary operators appear between two operands. Ternary operators have two separate operators
that separate three operands.

3.4.1 Arithmetic Operators:

These perform arithmetic operations. The + and - can be used as either unary (-z) or binary (x- y)
operators.
+ (addition)
- (subtraction)
* (multiplication)
/ (division)
% (modulus)

3.4.2 Relational Operators:

Relational operators compare two operands and return a single bit 1or 0. These operators
synthesize into comparators.
< (less
than)
<= (less
than or
equal
to)
> (greater
than)
>= (greater
than or

55
 equal
to)
== (equal
to)
!= (not
equal
to)
3.4.3 Bit-wise Operators:
Bit-wise operators do a bit-by-bit comparison between two operands.
~ (bitwise NOT)
& (bitwise AND)
| (bitwise OR)
^ (bitwise XOR)
~^ or ^~ (bitwise XNOR)

3.4.4 Reduction Operators:

Reduction operators operate on all the bits of an operand vector and return a single-bit value.
These are the unary (one argument) form of the bit-wise operators above.
& (reduction AND)
| (reduction OR)
~& (reduction NAND)
~| (reduction NOR)
^ (reduction XOR)
~^ or ^~ (reduction XNOR)

3.4.5 Logical Operators:

Logical operators return a single bit 1 or 0. They are the same as bit-wise operators only for
single bit operands. They can work on expressions, integers or groups of bits, and treat all
values that are nonzero as “1”. Logical operators are typically used in conditional (if...else)
statements since they work with expressions.
! (logical NOT)
&& (logical AND)
|| (logical OR)

56
3.4.6 Shift Operators:
Shift operators shift the first operand by the number of bits specified by the second operand.
Vacated positions are filled with zeros for both left and right shifts.
<< (shift left)
>> (shift right)

3.4.7 Concatenation Operator:

The concatenation operator combines two or more operands to form a larger vector. {}
(concatenation)

3.4.8 Conditional Operator:

Conditional operator is like those in C/C++. They evaluate one of the two expressions based
on a condition. It will synthesize to a multiplexer (MUX).
(cond) ? (result if cond true) : (result if cond alse)

3.5 Loops & Conditional Statements in Verilog

There are four looping statements in Verilog: while, for, repeat and forever. The syntax of these
loops is very similar to the syntax of loops in C programming language. All looping statements
can appear only inside an initial or always block. Loops may contain delay expressions.

3.5.1 While loop

The keyword while is used to specify this loop. The while loop executes until the while-
expression becomes false. If the loop is entered when the while-expression is false, the loop is
not executed at all. If multiple statements, they must be grouped typically using keywords
begin and end.

To avoid combinational feedback during synthesis, a while loop must be broken with an
@(posedge/negedge clock) statement .For simulation a delay inside the loop will suffice.
Syntax: while (expression) begin
... statements ...
end

57
3.5.2 For loop
Similar to for loops in C/C++, they are used to repeatedly execute a statement or block of
statements. If the loop contains only one statement, the begin ... end statements may be omitted.
The keyword for is used to specify this loop. The for loop contains three parts:
• An initial condition.
• A check to see if the terminating condition is true.
• A procedural assignment to change value of the control variable. Syntax:
for (count =value1;count </<=/>/>=value2;count = count +/-step) begin
... statements ...
end
3.5.3 Repeat loop
The keyword repeat is used for this loop. The repeat construct executes the loop a fixed number
of times. A repeat construct cannot be used to loop on a general logical expression. A repeat
construct must contain a number, which can be a constant, a variable or a signal value.
Syntax: repeat(number_of_times) begin
... statements ....
end

3.5.4 Forever loop

The keyword forever is used to express this loop. The loop does not contain any expression
and executes forever until the $finish task is encountered. The loop is equivalent to a while
loop with an expression that always evaluates to true, e.g., while (1). A forever loop can be
exited by use of the disable statement.

Syntax: forever begin

... statements ...
end

3.5.5 if .. else Statement

Conditional statements are used for making decisions upon certain conditions. These
conditions are used to decide whether or not a statement should be executed.

58
Keywords if and else are used for conditional statements. Each true_statement or false
statement can be a single statement or a block of multiple statements. A block must be grouped,
typically by using keywords begin and end. A single statement need not be grouped.
Syntax:
if (expression)
begin
... statements ...
End

3.5.6 case Statement

The nested if-else-if can become complicated if there are too many alternatives. A shortcut to
achieve the same result is to use the case statement. The keywords case, endcase, and default
are used in the case statement.
A block of multiple statements must be grouped by keywords begin and end. The expression
is compared to the alternatives in the order they are written. For the first alternative that
matches, the corresponding statement or block is executed. If none of the alternatives match,
the default_statement is executed. The default_statement is optional. Placing multiple default
statements in one case statement is not allowed. The case statements can be nested.
Syntax:
case (expression) alternative1: statement1; alternative2: statement2; alternative3:
statement3; default: default_statement; endcase

3.5.7 casex Statement

In casex(a) the case choices constant “a” may contain z, x or ? which are used as don’t cares
for comparison. With case the corresponding simulation variable would have to match a tri-
state, unknown, or either signal. In short, case uses x to compare with an unknown signal.
Casex uses x as a don’t care which can be used to minimize logic. Syntax is same as case.

3.5.8 casez Statement

casez is the same as casex except only ? and z (not x) are used in the case choice constants as
don’t cares. casez is favored over casex since in simulation, an inadvertent x signal, will not
be matched by a 0 or 1 in the case choice. Syntax is same as case.

59
3.6 Modelling Techniques:

Verilog HDL modeling language supports three kinds of modeling styles:

1. Gate-level Modeling
2. Dataflow Modeling
3. Behavioral Modeling
The Gate-level and Dataflow modeling are used to model combinatorial circuits whereas the
Behavioral modeling is used for both combinatorial and sequential circuits.

3.6.1 Gate Level Modeling

The gates supported are multiple-input, multiple output, tristate, and pull gates. The multiple-
input gates supported are: and, nand, or, nor, xor, and xnor whose number of inputs are two or
more, and has only one output. The multiple-output gates supported are buf and not whose
number of outputs is one or more, and has only one input. The language also supports modeling
of tri-state gates which include bufif0, bufif1, notif0, and notif1. These gates have one input,
one control signal, and one output.
Example 1:
and #5 A1(Out, in1, in2); // the rise and fall delays are 5 units and #(2,5) A2(out2, in1, in2);
// the rise delay is 2 unit and the fall delay is 5 units notif1 #(2, 5, 4) A3(out3, in2, ctrl1); //the
rise delay is 2, the fall delay is 5, and the turnoff delay is 4 unit
Example 2:
module gates ( input a, b, output c, d); buf (c, a, b); // c is the output, a and b are inputs not
(d, a, b); // d is the output, a and b are inputs endmodule

3.6.2 Dataflow Modeling

Dataflow modeling style is mainly used to describe combinational circuits. The basic
mechanism used is the continuous assignment. In a continuous assignment, a value is assigned
to a data type called net. The syntax of a continuous assignment is assign [delay] LHS_net =
RHS_expression;

Where LHS_net is a destination net of one or more bit, and RHS_expression is an expression
consisting of various operators.

60
Example:
// Dataflow description of 2-to-1 line multiplexer module mux2x1_df (A,B,select,OUT);
input A,B,select; output OUT; assign OUT=select ? A:B; //select is 1 OUT is A & select is
0 OUT is B endmodule

3.6.3 Behavioral Modeling

Behavioral modeling is used to describe complex circuits. It is primarily used to model
sequential circuits but can also be used to model pure combinatorial circuits. The
mechanisms (statements) for modeling the behavior of a design are:
• initial Statements
• always Statements
Behavioral description uses the keyword always followed by a list of procedural assignment
statements. The target output of the procedural assignment statement must be of the reg data
type. The behavioral description of 2-to-1 line multiplexer in HDL is given below.

Example:
// Behavioral description of 2-to-1 line multiplexer module mux2x1_bh (A,B,select,OUT);
input A,B,select; output OUT; reg OUT;
always @(select or A or B) begin if (select==1)
OUT=A;
else
OUT=B;
end
endmodule

3.7 Blocking and Non-Blocking Procedural Assignments

If there are multiple assignment statements in the procedural block in verilog then they can be
done in two different ways
1. Blocking using =
2. Non Blocking using <=

61
3.7.1 Blocking Assignments
Blocking assignment statements are executed in the order they are specified in a sequential
block. A blocking assignment will not block execution of statements that follow in a parallel
block.
In the example below the first time statement to get executed is q1 = d followed by another
two statements.

initial begin q1=d; q2=q1; q3=q2;

end Example:
reg x, y, z;
reg [15:01 reg_a, reg_b; integer count;
//All behavioral statements must be inside an initial or always block initial begin x = 0; y = 1;
z = 1; //Scalar assignments count = 0; //Assignment to integer variables reg_a = 16'b0; reg_b
= reg_a; //initialize vectors
#15 reg_a[2]=1'b1; //Bit select assignment with delay
#10 reg_b[15:13] = {x, y, z} //Assign result of concatenation to part select of a vector count =
count + 1; //Assignment to an integer (increment) end

In Example , the statement y = 1 is executed only after x = 0 is executed. The behavior in a

particular block is sequential in a begin-end block if blocking statements are used, because the
statements can execute only in sequence. The statement count = count + 1 is executed last. The
simulation times at which the statements are executed are as follows:
All statements x = 0 through reg_b = reg_a are executed at time 0.
Statement reg_a[2] = 0 at time = 15
Statement reg b[15:13] = (x, y, z) at time = 25 Statement count = count + 1 at time = 25.

Since there is a delay of 15 and 10 in the preceding statements, count = count + 1 will be
executed at time = 25 units Note that for procedural assignments to registers, if the right-hand
side has more bits than the register variable, the right-hand side is truncated to match the width
of the register variable. The least significant bits are selected and the most significant bits are
discarded. If right-hand side has fewer bits, zeros are filled in the most significant bits of the
register variable.

62
3.7.2 Non-Blocking Assignments
Nonblocking assignments allow scheduling of assignments without blocking execution of the
statements that follow in a sequential block. A < operator is used to specify nonblocking
assignments. Note that this operator has the same symbol as a relational operator,
less_than_equal_to. The operator <= is interpreted as a relational operator in an expression and
as an assignment operator in the context of a nonblocking assignment. To illustrate the behavior
of nonblocking statements and its difference from blocking statements, let us consider
Example, convert some blocking assignments to nonblocking assignments, and observe the
behavior.

reg x, y, z:
reg [15:0] reg_a, reg_b; integer count;
//All behavioral statements must be inside an initial or always block initial begin Initial begin
x = 0; y = 1; z= 1; //Scalar assignments count = 0; //Assignment to integer variables reg_a =
16'b0; reg_b=reg_a; //Initialize vectors reg_a[2] <= 15 1'b1; //Bit select assignment with
delay reg_b[15:13] <= 10 (x, y, z); //Assign result of concatenation
//to part select of a vector count <= count + 1; //Assignment to an integer (increment) end

In this example the statements x = 0 through reg_b=reg_a are executed sequentially at time 0.
Then, the three nonblocking assignments are processed at the same simulation time.
1. reg_a[2]=0 is scheduled to execute after 15 units (ie., time = 15)
2. reg b[15:13]=(x, y, z) is scheduled to execute after 10 time units (ie., time= 10)
3. count count+ 1 is scheduled to be executed without any delay (ie., time = 0)

Thus, the simulator schedules a nonblocking assignment statement to execute and continues to
the next statement in the block without waiting for the nonblocking statement to complete
execution. Typically, nonblocking assignment statements are executed last in the time step in
which they are scheduled, that is, after all the blocking assignments in that time step are
executed.

63
3.8 Tasks and Functions
3.8.1 Introduction
A designer is frequently required to implement the same functionality at many places in a
behavioral design.Verilog provides tasks and functions to break up large behavioral designs
into smaller pieces. Tasks and functions allow the designer to abstract Verilog code that is used
at many places in the design. To develop good program, the commonly used parts should be
abstracted into routines and the routines must be invoked instead of repeating the code.

3.8.2 Tasks
Tasks are used in all programming languages, generally known as procedures or subroutines.
Tasks are declared with the keywords task and endtask. Tasks can include timing delays, like
posedge, negedge, # delay and wait. Tasks can have any number of inputs and outputs.

The variables declared within the task are local to that task. The order of declaration within the
task defines how the variables passed to the task by the caller are used. Tasks can take, drive
and source global variables, when no local variables are used. When local variables are used,
basically output is assigned only at the end of task execution.

Tasks can call another task or function. Tasks can be used for modeling both combinational
and sequential logic. A task must be specifically called with a statement, it cannot be used
within an expression as a function can.

Example: task four_one; output y; input [3:0] i; input [1:0] s; y=((~s[0]&~s[1]&i[0]) |

(s[0]&~s[1]&i[1]) | (~s[0]&s[1]&i[2]) | (s[0]&s[1]&i[3])); endtask

module sixteen_one(i[15:0],s[3:0],y); input wire [15:0] i; input wire [3:0] s;

output reg y; reg [3:0] v;

always@* begin four_one(v[0],i[3:0],s[1:0]); four_one(v[1],i[7:4],s[1:0]);

four_one(v[2],i[11:8],s[1:0]); four_one(v[3],i[15:12],s[1:0]); four_one(y,v[3:0],s[3:2]);
end
endmodule
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3.8.3 Functions
Functions are declared with the keywords function and endfunction. Functions are defined in
the module in which they are used.

Functions cannot include timing delays, like posedge, negedge, # delay, which means that
functions should be executed in "zero" time delay.

Functions can have any number of inputs but only one output. The variables declared within
the function are local to that function. The order of declaration within the function defines how
the variables passed to the function by the caller are used.

Functions can take, drive, and source global variables when no local variables are used. When
local variables are used, basically output is assigned only at the end of function execution.

Functions can be used for modeling combinational logic. Functions can call other functions
but cannot call tasks.

Example:
module four_one(i[3:0],s[1:0],y); input [3:0] i; input [1:0] s; output y; assign
y=((~s[0]&~s[1]&i[0]) | (s[0]&~s[1]&i[1]) | (~s[0]&s[1]&i[2]) |
(s[0]&s[1]&i[3])); endmodule

module sixteen_one(i[15:0],s[3:0],y); input [15:0] i; input [3:0] s; output y; wire [3:0] v;

four_one f1(i[3:0],s[1:0],v[0]); four_one f2(i[7:4],s[1:0],v[1]); four_one

f3(i[11:8],s[1:0],v[2]); four_one f4(i[15:12],s[1:0],v[3]); four_one f5(v[3:0],s[3:2],y);
endmodule

65
 CHAPTER 4
DESIGN FOR TESTABILITY
4.1 Introduction to DFT

What is DFT?

• It is a set of techniques used in the design phase of an integrated circuit (IC) or a system to
make it easier to test for manufacturing defects, functional correctness, and performance once
it's produced.

• The main goal of DFT is to ensure that the chip can be easily tested for faults, ensuring the
highest possible yield and reliability. Without proper testability design, detecting
manufacturing defects or functional failures during the testing phase could be difficult or
impossible, leading to costly errors.

Why we do DFT?

• Manufacturing Quality: DFT ensures that defects due to process variations or manufacturing
defects can be caught.

• Cost Efficiency: Without testability features, it can be very expensive or even impossible to
validate a complex chip after manufacturing.

• Design Debugging: DFT techniques help identify which parts of the design are causing
failures, making it easier to debug and fix issues.

Table 4.1 Advantages and disadvantages of DFT

Advantages Disadvantages
It reduces time for testing of DFT increases power, area, timing and
manufactured chips. packing pins.

Some techniques in DFT give fault Tools like ATE (Automatic Test
coverage to 90% to 99% at least. Equipment) are very costly.

It can save the overall cost of the chip. DFT adds complication to the design
flow.

66
 4.2 Testing
˃ Structural Testing: A more practical approach to select specific test patterns based on
circuit structural information and a set of fault models. This approach called structural
testing.
Structural testing save times and improves test efficiency, as the total number of test patterns
is decreased because the test vectors target specific faults that would result from defects in
the manufactured circuit.
˃ Exhaustive / Functional Testing: If the CUT is an n-input combinational logic circuit , we
can apply all 2^n possible input patterns for testing stuck at faults. However, this example of
applying all possible input test patterns to an n-input combinational logic circuit also
illustrates the basic idea of functional testing. This testing is used to test small part of circuit.

4.2.1 Testing Factors

˃ Test coverage can be defined the percentage of the design’s logic (or functionality)
that is exercised during testing.
𝑁𝑜 𝑜𝑓 𝑓𝑎𝑢𝑙𝑡𝑠 𝑑𝑒𝑡𝑒𝑐𝑡𝑒𝑑
Test Coverage=𝑇𝑜𝑡𝑎𝑙 𝑛𝑜 𝑜𝑓 𝑑𝑒𝑡𝑒𝑐𝑡𝑎𝑏𝑙𝑒 𝑓𝑎𝑢𝑙𝑡𝑠 x 100

˃ Fault coverage can be defined as the percentage of detectable faults that are identified
by the test patterns.
𝑁𝑜 𝑜𝑓 𝑓𝑎𝑢𝑙𝑡𝑠 𝑑𝑒𝑡𝑒𝑐𝑡𝑒𝑑
Fault Coverage= 𝑇𝑜𝑡𝑎𝑙 𝑛𝑜 𝑜𝑓 𝑓𝑎𝑢𝑙𝑡𝑠
x 100

˃ Yield can be defined as percentage of fabricated chips that are functional out of the
total chips fabricated.
𝑵𝒐 𝒐𝒇 𝑨𝒄𝒄𝒆𝒑𝒕𝒆𝒅 𝑷𝒂𝒓𝒕𝒔
Yield= x 100
𝑻𝒐𝒕𝒂𝒍 𝒏𝒐 𝒐𝒇 𝒑𝒂𝒓𝒕𝒔 𝒇𝒂𝒃𝒓𝒊𝒄𝒂𝒕𝒆𝒅

˃ Reject rate can be defined as the percentage of fabricated chips that fail testing and
are discarded.
𝑁𝑜 𝑜𝑓 𝑓𝑎𝑢𝑙𝑡𝑦 𝑝𝑎𝑟𝑡𝑠 𝑝𝑎𝑠𝑠𝑖𝑛𝑔 𝑓𝑖𝑛𝑎𝑙 𝑡𝑒𝑠𝑡
Reject Rate= 𝑇𝑜𝑡𝑎𝑙 𝑛𝑜 𝑜𝑓 𝑝𝑎𝑟𝑡𝑠 𝑝𝑎𝑠𝑠𝑖𝑛𝑔 𝑓𝑖𝑛𝑎𝑙 𝑡𝑒𝑠𝑡 x 100

67
 4.3 Fault Models
˃ Fault models are essential for generating and evaluating test vectors, as real defects in VLSI
circuits can be highly diverse.
˃ A good fault model should:
o Accurately reflect the behavior of defects.
o Be computationally efficient for fault simulation and test pattern generation.

4.3.1 Types of Fault Model

1. Stuck-At Faults
The stuck-at fault is a logical fault model that has been used successfully for decades. A
stuck-at fault affects the state of logic signals on lines in a logic circuit, including primary
inputs (PIs), primary outputs (POs), internal gate inputs and outputs, fanout stems (sources),
and fanout branches. A stuck-at fault transforms the correct value on the faulty signal line to
appear to be stuck at a constant logic value, either a logic 0 or a logic 1, referred to as stuck-
at-0 (SA0) or stuck-at-1 (SA1), respectively.
For example,

Fig 4.1 And gate as stuck at 1

Table 4.2 And gate truth table with stuck at 1

2. Transistor Faults
At the switch level, a transistor can be stuck-open or stuck-short, also referred to as stuck-off

68
 or stuck-on, respectively. The stuck-at fault model cannot accurately reflect the behavior of
stuck-open and stuck-short faults in CMOS logic circuits because of the multiple transistors
used to construct CMOS logic gates.
For example,
In a two-input CMOS NOR gate, if transistor N2 is stuck-open, the output fails to transition
correctly, requiring a two-vector test for detection.
Stuck-short faults create a continuous path from VDD to VSS, leading to excessive power
consumption, detectable by IDDQ testing

Fig 4.3 Two input CMOS NOR gate

3. Bridging Faults
A short between two elements is commonly referred to as a bridging fault.
˃ Types of Bridging Faults:
1. Wired-AND Bridging Fault
• When two signals are shorted together, the output behaves as an AND function.
• Example: If A and B are shorted and one of them is 0, the output is forced to 0.
2. Wired-OR Bridging Fault
• The output behaves as an OR function when two signals are shorted.
• Example: If A and B are shorted and one of them is 1, the output is forced to 1.

69
 Fig 4.4 Bridging Fault Models

4. Delay Faults
˃ Signal propagation delay causes timing violations.
˃ A delay fault causes excessive delay along a path such that the total propagation delay falls
outside the specified limit.
˃ Delay faults have become more prevalent with decreasing feature size.
˃ Example: In a path-delay fault test, a delay fault causes a transition at the output later than
expected, which could lead to timing violations.

4.4 Design For Testibility Basics

The testability of digital circuits, especially sequential ones, becomes increasingly difficult as
complexity grows due to numerous internal states and lengthy input/output sequences needed
for testing. While early ad hoc design-for-testability (DFT) techniques offered some localized
improvements, they lacked consistency, predictability, and scalability. In contrast, structured
DFT methods provide a systematic and automatable approach that integrates well into the
design flow. One of the most effective structured DFT techniques is scan design, which
simplifies testing, improves fault coverage, and is widely supported by EDA tools.
4.4.1 Ad Hoc Approach
The ad hoc approach to Design for Testability (DFT) uses practical design and modification
guidelines aimed at improving testability, often based on experience. It involves replacing
poor design practices with better ones. One common technique is test point insertion, and
several other methods are discussed in the table.

70
 Table 4.3 Typical Ad hoc DFT Techniques
Code Description
A1 Insert test points
A2 Avoid asynchronous set/reset for storage elements
A3 Avoid combinational feedback loops
A4 Avoid redundant logic
A5 Avoid asynchronous logic
A6 Partition a large circuit into small blocks

4.4.1.1 Test Point Insertion

˃ Test point insertion (TPI) is a commonly used ad hoc DFT technique for improving the
controllability and observability of internal nodes.
˃ Testability analysis is typically used to identify the internal nodes where test points should be
inserted, in the form of control or observation points.
➢ Observation Points:
o Improve observability by capturing internal signals.
o Implemented using MUX and D Flip-Flops.
➢ Control Points:
o Improve controllability by modifying internal signals.
o Implemented using MUX-based structures.

Fig 4.5 Observation Point Insertion

71
 Fig 4.6 Control Point Insertion

4.4.2 Structured Approach

˃ Scan design, the most widely used structured DFT methodology, attempts to improve
testability of a circuit by improving the controllability and observability of storage elements
in a sequential design.
˃ Scan Design is a widely used structured DFT methodology.
˃ Benefits of structured DFT:
o Easier to integrate into the design flow.
o More predictable results compared to ad hoc techniques.
o Easier automation using Electronic Design Automation (EDA) tools.
For Example:
Assume that a stuck-at fault f in the combinational logic requires the primary input
X3, flip-flop FF2, and flip-flop FF3 to be set to 1 and 0 respectively, to capture
the fault effect into FF1.

72
 Fig 4.7 Difficulty in testing a sequential circuit.

From this example, we understood that main difficulty in testing a sequential

circuit stems from the fact that it is difficult to control and observe the internal
state of the circuit.

4.5 Scan Cell Designs

˃ A scan cell is a modified flip-flop that supports both normal and test operations.
˃ The first input, data input, is driven by the combinational logic of a circuit, while the second
input, scan input, is driven by the output of another scan cell to form one or more shift
registers called scan chains.
˃ As there are two input sources in a scan cell, a selection mechanism must be provided to
allow a scan cell to operate in two different modes:
o normal/capture mode
o shift mode.
˃ In normal/capture mode, data input is selected to update the output. In shift mode, scan input
is selected to update the output.
˃ Three widely used scan cell designs are:
1. Muxed- D scan
2. Clocked-scan
3. Level-sensitive scan design (LSSD).

73
 4.5.1 Muxed-D scan
˃ This scan cell is composed of a D flip-flop and a multiplexer. The multiplexer uses a scan
enable (SE) input to select between the data input (DI) and the scan input (SI).
˃ In normal/capture mode, SE is set to 0. The value present at the data input DI is captured into
the internal D flip-flop when a rising clock edge is applied.
˃ In shift mode, SE is set to 1. The SI is now used to shift in new data to the D flip-flop while
the content of the D flip-flop is being shifted out.

Fig 4.8 Edge triggered Muxed-d scan cell

Fig 4.9 Sample Wave form

Level-Sensitive muxed-D scan cell

˃ This scan cell is composed of a multiplexer, a D latch, and a D flip-flop.
˃ Again, the multiplexer uses a scan enable input SE to select between the data input DI and the
scan input SI.
˃ However, in this case, shift operation is conducted in an edge-triggered manner, while normal
operation and capture operation are conducted in a level-sensitive manner.

74
 Fig 4.10 Level Sensitive muxed-d scan cell

4.5.2 Clocked Scan cell

An edge-triggered clocked-scan cell can also be used to replace a D flip-flop in a scan
design. Similar to a muxed-D scan cell, a clocked-scan cell also has a data input DI and a
scan input SI; however, in the clocked-scan cell, input selection is conducted using two
independent clocks, data clock DCK and shift clock SCK.
In normal/capture mode, the data clock DCK is used to capture the value present at the data
input DI into the clocked-scan cell. In shift mode, the shift clock SCK is used to shift in new
data from the scan input SI into the clocked-scan cell.

Fig 4.11 Clocked Scan cell and its sample wave form

75
 4.5.3 LSSD Scan Cell
While muxed-D scan cells and clocked-scan cells are generally used for edgetriggered, flip-
flop-based designs, an LSSD scan cell is used for level-sensitive, latch-based designs.
˃ Structure:
Uses two latches (Master L1 and Slave L2) instead of flip-flops, with three non-overlapping
clocks (A, B, C).
˃ Working Principle:
Normal Mode:
o System clock (C) latches data into L1, then clock B latches it into L2 for normal operation.
Shift Mode:
o Clocks A and B are used to shift scan data through the latches.

Fig 4.12 LSSD scan cell and its sample waveform

4.6 Scan Architecture

These scan architectures include :
▪ Full-scan design :
All storage elements are converted into scan cells and combinational ATPG is used for test
generation.
▪ Partial-scan design :

76
 A subset of storage elements is converted into scan cells and sequential ATPG is typically
used for test generation.

4.6.1 Full Scan Design

˃ Full-scan design replaces all storage elements with scan cells.
˃ Scan cells are configured into one or more shift registers (scan chains) during testing.
˃ This allows control over all inputs and observability of all outputs.
˃ Converts a complex sequential test problem into a simpler combinational test.
˃ During scan mode, test data is shifted into scan cells and propagated through combinational
logic.
˃ Test responses are shifted out for analysis.

4.6.1.1 Muxed-D Full Scan Design

➢ Primary Inputs (PIs): Directly controlled from external sources.
➢ Pseudo Primary Inputs (PPIs): Scan cell outputs, set serially through scan chains.
➢ Primary Outputs (POs): Directly observable external outputs.
➢ Pseudo Primary Outputs (PPOs): Scan cell inputs, observed serially through scan chains.
➢ Shift Mode (SE = 1): Load test vector’s PPI values into the scan chain.
➢ Hold Cycle: SE = 0 to prepare for capture mode.
➢ Capture Mode (SE = 0): Capture combinational logic’s response.
➢ Second Hold Cycle: SE = 1 to prepare for observation.
➢ Shift Out: Shift out captured response while loading the next pattern. Ensures all storage
elements are controllable and observable for fault detection.

77
 Fig 4.13 muxed-D full-scan circuit and test operations

4.6.1.2 Clocked Full Scan Design

➢ Similar to muxed-D full-scan but differs in control mechanism.
➢ Uses two independent clocks instead of a Scan Enable (SE) signal:
➢ SCK (Shift Clock): Loads test patterns during Shift Mode.
➢ DCK (Data Clock): Captures test responses during Capture Mode.
➢ Mode switching is controlled by SCK and DCK timing rather than an SE signal.

Fig 4.14 Clocked full scan circuit

4.6.1.3 LSSD Full Scan Design

➢ LSSD scan cells typically consist of:
➢ Master Latch (L1) – A two-port D-latch for normal data capture.
➢ Slave Latch (L2) – Another D-latch, used for scan operations.
➢ Three Clocks (C, A, B):
➢ C: System clock for normal operations.
➢ A: Scan shift clock (controls shifting of scan data into L1).
➢ B: Scan shift clock (transfers data from L1 to L2).
Modes of Operation
➢ Normal Mode: Clock C latches data into L1, then transfers to L2 to drive logic.
➢ Scan Mode: Clock A loads scan data into L1, Clock B transfers it to L2, shifting data from
SI to SO.
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 Fig 4.15 LSSD full scan circuit

4.6.2 Partial Scan Design

➢ Unlike full-scan design, only a subset of storage elements are replaced with scan cells.
➢ Used before full-scan designs became dominant.
➢ The main disadvantage is that it can result in lower fault coverage and longer test generation
time than a full-scan design.
➢ Three types of partial scan design:
1. Functional partitioning
2. Pipelined or feed-forward partial-scan design
3. Balanced partial-scan design

4.6.2.1 Functional Partitioning

Divides the circuit into:
➢ Data Path Portion: Performance-critical; storage elements here are often not replaced with
scan cells to avoid delays.
➢ Control Portion: Less timing-sensitive; storage elements here can be replaced with scan
cells.
➢ Advantage: Balances fault coverage improvement while minimizing performance
degradation.

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 4.6.2.2 Pipelined or feed-forward partial-scan design
➢ Focuses on eliminating sequential feedback loops by selectively replacing specific storage
elements with scan cells.
➢ The goal is to create a feedback-free sequential circuit for simpler Automatic Test Pattern
Generation (ATPG).

Fig 4.16 Pipelined partial scan design

Challenges:
➢ Designs may contain self-loops or small loops. Breaking all loops can increase area
overhead.
Optimized Approach:
➢ Breaking only large feedback loops minimizes area overhead while maintaining high fault
coverage.
➢ Fault coverage as high as over 95% can be achieved by replacing roughly 25 to 50% of all
storage elements with scan cells for a small design.

4.6.2.3 Balanced Partial Scan Design

˃ This approach sets a target sequential depth to simplify the test generation process for
pipelined or feed-forward partial-scan designs.
˃ To achieve this, selected storage elements are replaced with scan cells, reducing the number
of sequential elements in the circuit.
˃ By keeping the sequential depth small, combinational ATPG can be applied using multiple
time frames, leading to higher fault coverage and improved test efficiency.

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 Conclusion

ASIC design is a methodology of cost and size reduction of an electronic circuit, product or
system through miniaturization and integration of individual components and their
functionality into a single element. As the number of gates or transistors doubles after every
18 months and is growing to extremely high densities per IC. So, the channel length is
decreasing due to each stage in asic design flow need to be performed precisely and perfectly.
Learning each stage in brief will help to analyze easily. Synthesis is an important step that
helps to generate the gate level netlist from RTL code.

Now DFT is much needed, as the node technology is decreasing in size due to that chance of
having faults and defect increases. So DFT is used to add additional pins and logic in the circuit
to make the chip controllable and observable. At the time of testing, we can test the circuit
easily due to these test points. Scan insertion is the first step that is used in DFT. It basically
generates the scan input pins and scan chains in the circuit. Even in this process report were
generated for pre-DRC and post DRC which will show the number and types of violation
present in the design before and after scan insertion respectively. Other reports such as scan
configuration will show all the scan insertion details chain count, max length etc. The netlist
generated from it is used for further processing in ATPG.

Additional knowledge of scripting languages like Shell script and Perl is helpful in Asic
Industry for easily accessing the tools. And as linux is an open-source platform so all the tools
are compatible with it. I can conclude that from this training I have learnt the ASIC Flow and
DFT in detail with perquisites of scripting language.

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 References

BOOKS:
[1] Design For Testability: VLSI test principles And Architecture. Laung- Terng Wang
[2] Verilog HDL: A guide to Digital Design and Synthesis. Samir Palnitkar
WEB RESOURCES:
[1] Linux commands
www.javatpoint.com/linux-commands
[2] Shell Scripting
www.geeksforgeeks.org/introduction-linux-shell-shell-scripting/
[3] Perl Scripting
www.geeksforgeeks.org/perl-tutorial-learn-perl-with-examples/
[4] DFT Basics
https://youtube.com/playlist?list=PLZjlBaHNchvOFBWBAtAP9exwQgYpKqsO4&si=eG
mjvNY_-sYakG-A

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