Crack DFT Interviews at

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50 Interview Questions for Roles like

DFT Engineer,
ASIC Verification with DFT exposure,
SoC Design Engineers with testability experience.

Prasanthi Chanda
Q1: How do you handle unknowns (X values) during scan insertion?
Company : Intel

Answer :
We use X-bounding techniques like X-masking cells, X-safe design, or X-
bounding flip-flops to prevent X propagation to scan outputs. X-sources
are typically tri-states, analog macros, or uninitialized memory blocks.

Question Asked in Real Interview scenario :

"We’re working on a mixed-signal SoC and seeing Xs during scan
simulations from an analog IP. How would you debug and mitigate that?"

Q2: What is the difference between stuck-at and transition fault

models, and why is transition fault testing important?
Company : Qualcomm

Answer :
Stuck-at faults assume static 0/1 faults. Transition faults check for timing-
related issues by modeling slow-to-rise or slow-to-fall defects. Transition
fault testing is critical for detecting timing-related manufacturing defects
in deep submicron nodes.

Question Asked in Real Interview scenario :

"Your ATPG stuck-at coverage is 99%, but transition coverage is only 85%.
What does that indicate? What’s your approach?"

Q3: How do you deal with clock domain crossings during scan
stitching?
Company : AMD

Answer :
Avoid stitching flip-flops across asynchronous domains. Use multiple scan
chains, lockup latches, and maintain clock grouping. CDC paths are tested
separately using functional test or dedicated logic.
Question Asked in Real Interview scenario :
"We have a design with 4 asynchronous clock domains. How will you
ensure proper scan chain integrity and testability?"

Q4: Explain the concept of test point insertion and its effect on
observability and controllability.
Company : NVIDIA

Answer :
Test points (control or observe points) are inserted to improve fault
coverage by increasing controllability of hard-to-reach nodes and
observability of unobservable outputs. ATPG tools suggest locations based
on fault simulation data.

Question Asked in Real Interview scenario :

"You’ve implemented scan, but coverage is stuck at 89%. What's your
strategy to push it over 95%?"

Q5: How do you generate a low-power scan architecture?

Company : Apple

Answer :
Use scan cell reordering, multi-bit scan chains, gating scan enable, and
retaining state retiming to reduce switching during scan shift. Avoid high
toggling nets using vector-aware ATPG.

Question Asked in Real Interview scenario :

"During post-silicon testing, we observed overheating during scan shifts.
What could be the cause and how can you optimize for power?"
Q6: What are the types of compression techniques used in scan
architecture?
Company : Texas Instruments (TI)

Answer :
Scan compression uses test response compactors (MISR) and stimulus
decompressors (LFSR, Xpress). Techniques include time compression, space
compression, and hybrid BIST/DFT approaches.

Question Asked in Real Interview scenario :

"We want to reduce scan test time by 5x without losing coverage. What’s
your suggestion?"

Q7: Describe how you would test a memory block embedded in

your SoC.
Company : Broadcom

Answer :
Use Built-In Self Test (BIST) with March algorithms. Memory BIST includes
controller, pattern generator, and comparator. BIST can be integrated
using Memory BIST tools (like MBISTArchitect).

Question Asked in Real Interview scenario :

"Our SRAM blocks are not directly accessible from scan. How would you
test them?"

Q8: What is boundary scan, and where is it applied?

Company : STMicroelectronics

Answer :
Boundary Scan (JTAG, IEEE 1149.1) allows testing interconnects between
chips on a PCB. It's used for board-level testing and debugging using TAP
controllers.
Question Asked in Real Interview scenario :
"In a multi-chip module, we want to test IO connectivity without probes.
How can we do that?"

Q9: Explain the importance of chain balancing in scan insertion.

Company : Synopsys

Answer :
Chain balancing ensures scan chains have equal length, which improves
test performance by reducing skew, scan test time, and power imbalance
during scan shift.

Question Asked in Real Interview scenario :

"Your design has 10 chains, but one has 300 FFs while another has 100.
What impact will this have?"

Q10: What are the key challenges in implementing logic BIST?

Company : MediaTek

Answer :
Challenges include area overhead, test coverage of random-pattern-
resistant faults, diagnosis capability, and integration of BIST controller with
minimal performance impact.

Question Asked in Real Interview scenario :

"We want to go for a logic BIST solution for our networking ASIC. What are
the tradeoffs?"

Q11: What are X-tolerant compactors and why are they needed in
scan compression?
Company : Marvell

Answer :
X-tolerant compactors like MISR with X-mask logic allow partial
compaction even if unknown values (X) are present in some scan outputs.
They avoid masking entire test patterns.
Question Asked in Real Interview scenario :
"We’re using compressed scan with a compactor but observe test escapes
due to Xs. How do you solve it?"

Q12: What is a launch-on-capture and launch-on-shift in transition

fault testing?
Company : Broadcom

Answer :
Launch-on-capture (LOC): First vector is loaded via scan, second is
applied using functional clock to capture real timing behavior.
Launch-on-shift (LOS): Second transition is created during scan shift.
LOC is more timing-accurate, while LOS is easier to implement but less
realistic.

Question Asked in Real Interview scenario :

"We see transition test failures in LOC mode but not in LOS mode. What
might be the reason?"

Q13: How do you implement scan insertion in an SoC with multiple

clock domains and power domains?
Company : NXP Semiconductors

Answer :
Use clock grouping, separate scan chains per domain, and clock
muxing.
Insert isolation cells and level shifters where required.
Ensure DFT constraints (SDF, clocks, resets) handle domain-specific
behavior.

Question Asked in Real Interview scenario :

"How would you handle scan insertion across 3 voltage islands and 4 clock
domains in an automotive chip?"
Q14: How does DFT interact with power-aware design?
Company : Infineon

Answer :
DFT must comply with power domains and retention strategies.
Use power-aware scan stitching, power intent files (UPF), and ensure
scan chains don't cross domains without handling.
Validate with power-aware ATPG simulation.

Question Asked in Real Interview scenario :

"We observe functional issues post-silicon when power domains are turned
off. Could DFT be the cause?"

Q15: How do you validate DFT logic in gate-level simulations?

Company : Cadence

Answer :
Use DFT testbenches, scan pattern simulations, SDF timing annotation, and
assertions to validate scan chains, reset behavior, and test coverage.

Question Asked in Real Interview scenario :

"How would you verify a stuck-at ATPG vector works correctly on your
netlist?"

Q16: What’s the role of a lock-up latch in scan chain design?

Company : Samsung

Answer :
Lock-up latches handle clock skew between flip-flops in different clock
domains during scan shift. They prevent data corruption due to hold-time
violations.

Question Asked in Real Interview scenario :

"You see scan chain failures during shift in an asynchronous domain. What
could fix it?"
Q17: What causes low coverage in ATPG and how would you
improve it?
Company : ARM

Answer :
Common reasons: sequential depth, unreachable logic, X-blockages,
redundant logic.
Fixes: Test point insertion, partial scan, removing redundant logic,
better constraints.

Question Asked in Real Interview scenario :

"Why does ATPG coverage drop after synthesis? How do you push it back
up?"

Q18: What is a stuck-open fault model and where is it used?

Company: Intel

Answer :
Stuck-open faults occur in CMOS pass transistors, especially in domino
logic or transmission gates. Requires two-pattern testing (test + observe)
and is less common in scan-based flow.

Question Asked in Real Interview scenario :

"We’re seeing failures in precharge logic post-silicon. Could DFT have
missed something?"

Q19: How would you test IOs and pads that are bidirectional?
Company : Analog Devices

Answer :
Use Boundary Scan (JTAG) with bidirectional cell support, or isolate
bidirectional behavior using muxed IO test logic. Some pads may need
functional mode testing.
Question Asked in Real Interview scenario :
"The bidirectional pads are not covered in scan. What’s your strategy to
ensure they’re tested?"

Q20: How do you handle DFT for an analog/mixed-signal IP

embedded in a digital SoC?
Company : Texas Instruments

Answer:
Use DFT hooks to enable DC/AC parametric tests.
Use analog BIST (ABIST) or digitally wrapped ADC/DAC test logic.
Apply DFT-on-AMS IPs to bring analog visibility to digital test infra.

Question Asked in Real Interview scenario :

"Our chip has embedded ADCs and PLLs. Can we scan-test them?"

Q21: How do you handle scan chain diagnosis post-silicon?

Company : Qualcomm

Answer :
Use fail logs from ATE, correlate failing vectors with ATPG patterns,
and apply diagnostic tools (like Tessent Diagnosis or Sherlock) to trace
the failure back to a net/FF/gate.

Question Asked in Real Interview scenario :

"We’re seeing consistent chain break at bit 1432. What’s your step-by-step
debug approach?"

Q22: How do you verify MBIST logic after insertion?

Company : Micron

Answer :
Simulate MBIST controller with memory model in DFT sim mode using
March tests, check pass/fail flags, and validate integration with
testbenches + assertion checks.
Question Asked in Real Interview scenario :
"MBIST is passing in RTL sim but failing in gate sim. What could be wrong?"

Q23: What is the use of compressed ATPG patterns, and how do

they reduce test cost?
Company : NVIDIA

Answer:
Compressed ATPG patterns reduce test time by reusing a small set of
vectors with decompressors.
They cut pattern count, test data volume, and tester time, significantly
saving test cost.

Question Asked in Real Interview scenario :

"Our test cost is high due to a long test program. What’s the quickest fix
without impacting coverage?"

Q24: What is a fault dictionary and where is it used?

Company : Broadcom

Answer :
A fault dictionary maps failing responses to potential fault candidates.
Used for post-silicon debug and diagnosis.
Helps narrow down physical fault locations during yield analysis.

Question Asked in Real Interview scenario :

"Our chip is failing random vectors. Can we trace that to a layout defect
somehow?"
Q25: What is the difference between hard and soft macros in DFT
context?
Company : MediaTek

Answer :
Hard macro: Pre-characterized, often with pre-inserted DFT (black-box
view).
Soft macro: Synthesizable RTL with DFT insertion possible.
You must treat hard macros as DFT black boxes with wrapper scan
support.

Question Asked in Real Interview scenario :

"We’ve got a third-party DDR PHY. How do you handle DFT for it in our top-
level scan plan?"

Q26: How is fault simulation used to measure DFT quality?

Company: Intel

Answer:
Run fault simulation on ATPG patterns to evaluate fault coverage for
various models (stuck-at, transition, bridging).
It highlights untested faults, helps with pattern efficiency analysis.

Question Asked in Real Interview scenario :

"Your stuck-at coverage report says 98.7%. How was this number
calculated?"

Q27: How do you manage DFT in hierarchical or partitioned

designs?
Company: AMD

Answer:
Use DFT abstraction (black-box wrappers) for lower blocks, perform
modular ATPG, and integrate at top with scan chain concatenation or
retargeting using tools like TestMAX or Tessent.
Question Asked in Real Interview scenario :
"We’re taping out a 10M-gate SoC with 8 blocks. How will you handle ATPG
and scan stitching efficiently?"

Q28: What is a test collar and why is it used?

Company : Renesas

Answer:
A test collar is wrapper logic around a hard macro or analog IP that
allows integration into scan flow.
It usually includes test enable muxes, scan wrappers, and output
observe logic.

Question Asked in Real Interview scenario :

"We have a non-scannable IP from a third-party vendor. How do we test it
in scan?"

Q29: What is LBIST and when should it be used?

Company : STMicroelectronics

Answer:
Logic Built-In Self-Test (LBIST) enables in-field, at-speed logic testing
using pseudo-random patterns from an LFSR, analyzed using a MISR.
Used in automotive, aerospace, and mission-critical designs for self-
test.

Question Asked in Real Interview scenario :

"We need in-field logic self-test as per ISO 26262. What's your plan?"

Q30: Explain stuck-at fault simulation vs stuck-at fault grading.

Company : Texas Instruments

Answer:
Stuck-at fault simulation: Applies patterns and checks how many faults
are detected.
 Fault grading: Evaluates a pattern set against a fault list, showing what
% is covered, and where to improve.
Used to validate ATPG quality.

Question Asked in Real Interview scenario :

"Can you prove to me that your 98% stuck-at coverage isn’t just a tool
claim but verified?"

Q31: How do you handle test mode conflicts in a design with

multiple IPs?
Company : AMD

Answer :
Implement a test mode controller that arbitrates scan enable, test
enable, and reset signals across IPs.
Use test modes isolation muxes and define safe test modes per IP.

Question Asked in Real Interview scenario :

"Two IPs assert scan_en high during functional mode. How do you ensure
test mode doesn’t interfere with functional logic?"

Q32: What is the role of constraints in ATPG and how do you define
them?
Company : Synopsys

Answer :
Constraints guide ATPG to avoid false paths, uncontrollable signals,
and X sources.
Include reset values, blackboxes, clocking rules, and known unknowns
(X) to improve realistic test generation.

Question Asked in Real Interview scenario :

"Our ATPG tool is marking many flops untestable. What should you check
in the constraint file?"
Q33: What is Scan Shift Power and how do you reduce it?
Company : Apple

Answer :
Scan shift power is dynamic power during scan shifting due to toggling
of scan elements.
Reduce it using low-power scan (LPS), shift ordering, clustering, and
multi-cycle shift.

Question Asked in Real Interview scenario :

"We’re hitting IR drop violations during scan shift. How would you bring it
down?"

Q34: What’s the difference between stuck-at fault and transition

fault in terms of test pattern generation?
Company : AMD

Answer:
Stuck-at: Tests static logic faults using single vector per fault.
Transition fault: Tests delay faults using two vectors (launch & capture).
Requires timing-aware ATPG.

Question Asked in Real Interview scenario :

"Why do we have more patterns and longer run-time for transition ATPG
than stuck-at?"

Q35: What is a scan collar and how is it different from a test collar?
Company: TSMC

Answer:
A scan collar wraps the core logic around I/O cells to integrate them into
scan chains. A test collar wraps an entire IP block (like a macro or
memory).
Scan collar: flip-flops around I/Os.
Test collar: scan wrapper around block.
Question Asked in Real Interview scenario :
"How do you test a soft IP block that has asynchronous I/Os?"

Q36: What is test point insertion and how does it help in DFT?
Company : AMD

Answer:
Insert controllability/observability points in design to make hard-to-
test nodes more testable.
Improves ATPG coverage, reduces pattern count, and resolves
sequential depth issues.

Question Asked in Real Interview scenario :

"We’re stuck at 91% coverage. Any technique to get >95% without huge
pattern inflation?"

Q37: What is launch-off-shift and what are the major issues with it?
Company : Infineon

Answer:
Launch-off-shift applies second vector while shifting scan; issues:
May not represent real timing
Risk of clock skew & glitches
Hard to correlate to functional behavior
Use only in non-critical paths or when test time is highly constrained.

Question Asked in Real Interview scenario :

"Our LOS transition testing fails at-speed. What factors could cause this?"
Q38: How do you verify the coverage of LBIST?
Company : STMicroelectronics

Answer :
Use LBIST fault simulation on generated PRPG patterns.
Simulate against stuck-at, transition, or bridging faults.
Use tools like Tessent LBIST Analyzer or Mentor LBISTSim.

Question Asked in Real Interview scenario :

"We implemented LBIST with 256 patterns, but how do we prove it’s
covering logic effectively?"

Q39: What is a bridging fault and how do ATPG tools detect it?
Company : Texas Instruments

Answer:
A bridging fault is modeled as a short between two signals.
ATPG tools simulate dominant/dominant or dominant/AND behaviors
to generate distinguishing vectors.

Question Asked in Real Interview scenario :

"We suspect a short between two nets. Can ATPG help us generate a
targeted test for it?"

Q40: How do you ensure DFT readiness during RTL freeze?

Company : Intel

Answer:
Run early DFT lint, check for scan rule compliance, DFT DRCs
Insert DFT hooks, ensure DFT test modes are architected
Sign off scan chain connectivity, clock/reset muxing, and test logic
gates before freeze
Question Asked in Real Interview scenario :
"The RTL is frozen. Later, DFT violations are seen during synthesis. How do
you prevent this in future projects?"

Q41: What is the difference between logic BIST and memory BIST?
Company : NXP Semiconductors

Answer:
Logic BIST (LBIST): Targets random logic blocks using PRPG/MISR.
Memory BIST (MBIST): Targets memories (RAMs) using march
algorithms like March C-, March LR, etc.
MBIST handles address, data, and control buses, while LBIST works on
combinational/sequential logic.

Question Asked in Real Interview scenario :

"You’ve implemented both LBIST and MBIST in a mixed-signal SoC. How do
they differ structurally and functionally?"

Q42: What causes X-propagation issues in scan and how to fix

them?
Company : Infineon

Answer:
Caused by uninitialized flops, analog blocks, tri-states, or gated clocks.
Fix by:
Initializing X-sources
Masking unknowns in ATPG constraints
Using X-blocking cells or gating clocks correctly

Question Asked in Real Interview scenario :

"Our ATPG patterns are aborting due to unmodeled Xs. What will you
check?"
Q43: What is clock domain crossing (CDC) in DFT and how do you
handle it?
Company : Broadcom

Answer :
CDC in DFT refers to scan chains or test paths spanning multiple clock
domains.
Handled by:
Clock domain grouping
Inserting safe synchronizers or clock muxes
Using asynchronous test modes or retiming scan chains

Question Asked in Real Interview scenario :

"Scan fails when traversing between PLL-generated clocks. How do you
debug CDC issues in DFT?"

Q44: How do you implement chain repair in scan design?

Company : Intel

Answer:
Insert spare scan flip-flops and mux-based bypass paths for rerouting
in case of stuck chains.
Use e-fuses or programmable registers to control routing.

Question Asked in Real Interview scenario :

"Production yield is dropping due to scan chain failures. How will you add
repair without major redesign?"
Q45: How is test compression integrated into ATPG flow?
Company : Cadence

Answer:
Add on-chip decompressors (input) and compressors (output)
ATPG patterns are generated aware of compression architecture (e.g.,
EDT)
Requires tools like Synopsys DFTMAX or Tessent TestKompress

Question Asked in Real Interview scenario :

"We’re using a 10x compression architecture. What changes in pattern
generation and scan stitching?"

Q46: What is a stuck-open fault and how is it tested?

Company : Micron

Answer:
A stuck-open fault is when a transistor fails to conduct due to broken
path.
Tested using two-vector sequences to detect missing transitions, often
modeled as bridging or dynamic faults.

Question Asked in Real Interview scenario :

"We’re in a CMOS process with known stuck-open issues. How do you
handle this during ATPG?"

Q47: Explain the need for multiple test modes in complex SoCs.
Company : MediaTek

Answer:
Each test mode (e.g., MBIST, LBIST, scan, JTAG, functional test) requires
unique muxing, clocking, and power configurations.
Used to isolate domains, reduce conflicts, and parallelize test.
Question Asked in Real Interview scenario :
"In your SoC, there are 5 test modes. Why not unify them into one test
mode?"

Q48: How do you generate constraints for black-box macros in

ATPG?
Company : NXP Semiconductors

Answer:
Use black-box models with I/O direction, X-handling rules, and timing
exceptions.
Define masking and set known values to prevent X-propagation.

Question Asked in Real Interview scenario :

"Your block has multiple encrypted macros. How do you prevent them
from degrading ATPG coverage?"

Q49: What is a partial-scan design and when is it used?

Company : NVIDIA

Answer:
Scan only a subset of flops to reduce area/power impact.
Used when full scan is not feasible (e.g., due to area, power, or test
time constraints).
Requires careful selection using controllability/observability analysis.

Question Asked in Real Interview scenario :

"Due to area limits, you can scan only 80% of flops. How do you decide
which to scan?"
Q50: How do you debug scan shift failures in silicon?
Company : NXP Semiconductors

Answer:
Steps:
Use shift pattern readback
Probe using Scan Diag or LBIST analysis
Cross-check chain order, mux config, stuck-at nets
Analyze clock tree integrity

Question Asked in Real Interview scenario :

"Scan reads out incorrect data in one domain. What tests and techniques
do you use to localize the fault?"
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