DF SUMMER 2022 PAPER SOLUTION

Q1 (A) List out various logic families. Also list characteristics of digital IC
(3M)
ANS

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Characteristics of Digital IC
1. Threshold Voltage
 It is defined as that voltage at the input of a gate switch causes
a change in state of output from one logic level to other
2. Propagation Delay
𝑡 +𝑡
 Propagation Delay : tp = 1 2
2

3. Fan in

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 4. Fan out
5. Power Dissipation
6. Noise Immunity
7. Power Supply
8. Operating Temperature
9. Figure of Merit

Q1 (B) What is Signal? Explain different types of signals (4M)

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Signal
 A signal is defined as any physical or virtual quantity that varies with
time or space or any other independent variables
 Graphically, independent variables represented by horizontal axis of X

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– axis and depend variable is represented by vertical axis or y – axis
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 Mathematically , a signal is a function of one or more than one

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independent variables
Types of Signals
1. Single Variable Signal
 It depends on single independent variable. It either varies
linearly or non – linearly depending on expression of signal
 Example :
S(x) = x + 5
S(x) = x2 + 5 where x is variable
S(t) = cos(ωt + ϴ) where t is variable
2. Two Variable Signal
 A two variable signal varies with change in two independent
variables
 Example
S(x, y) = 2x + 5y

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Q1 (C) Implement following Boolean Function
a) F(A, B, C, D) = ∑(𝟏, 𝟑, 𝟔)
b) F(A, B, C) = ∏(𝟐, 𝟑, 𝟓) (7M)

ANS
a) F(A, B, C, D) = ∑(𝟏, 𝟑, 𝟔)
3 variables = 3 – 1 = 2 22 = 4 input supply require

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b) F(A, B, C) = ∏(𝟐, 𝟑, 𝟓)
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Q2 (A) Perform binary subtraction using 2’s complement (0111)2 – (1101)2

ANS

 1 s complement of 1101 is
0 0 1 0
+ 1
0 0 1 1
 Adding
0 0 1 1
+0 0 1 1
1 0 1 0
 1s complement of 1010 = 0101
0 1 0 1

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+
0 1 1 0
1 aa
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2s complement : 0110

Q2 (B) Convert decimal number 250.5 to base 4 & base 8 (4M)

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 base 4
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4 250 2
4 62 2
4 15 3
3 3
Fractional part = 0.5 × 4 = 2
Ans : (3322.2)4

 base 8
8 250 2
8 31 7
3 3
Fractional part = 0.5 × 8 = 4
Ans : (372.4)8

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Q2(C) Design combinational circuit that convert 8 – 4 – 2 – 1 code to
BCD (7M)

ANS

Truth Table
Decimal 8 4 2 1 BCD
Digit A B C D W X Y Z
0 0 0 0 0 0 0 0 0 0
7 1 0 1 1 1 0 0 0 1
6 2 0 1 1 0 0 0 1 0
5 3 0 1 0 1 0 0 1 1
4 4 0 1 0 0 0 1 0 0
11 5 1 0 1 1 0 1 0 1
10 6 1 0 1 0 0 1 1 0

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9 7 1 0 0 aa 1 0 1 1 1
8 8 1 0 0 0 1 0 0 0
15 9 1 1 1 1 1 0 0 1
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Don’t care : 1, 2, 3, 12, 13, 14

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W = AB + ACIDI X = BIC + BID + BCIDI

Y = CI D + CDI Z = CI D + D
Z=D

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So,
W = AB + ACIDI
X = BIC + BID + BCIDI
Y = CID + CDI
Z=D

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OR Q2(C) Explain various logic gates (7M)

ANS

1. AND Gate

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Boolean Expression : Y = A. B
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2. OR Gate
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 It is gate in which output goes to level. When any one or more

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inputs go to level 1. That means output goes to 0 level only when

all inputs are at 0 level

 Boolean Expression : Y = A + B

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3. NOT Gate
 A NOT gate has one input & one output. Output is complement
of input

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̅
 Boolean Expression : Y = 𝑨
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4. NAND Gate
 This basic logic gate is combination of AND & NOT gates

 Boolean Expression : Y = ̅̅̅̅̅

𝑨. 𝑩

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5. NOR Gate
 This gate is combination of OR & NOT gate

 Boolean Expression : Y = ̅̅̅̅̅̅̅̅

𝑨+𝑩

6. Exclusive OR Gate (XOR Gate)

 In an XOR gate, output of a two – inputs XOR gate attains state 1
if one adds only input attain state 1

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7. Exclusive NOR Gate (XNOR Gate)

 In XNOR gate, output is state 1 where both inputs are same,
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that is, both 0 or both

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Q3(A) Compare Half Adder & Full Adder (3M)

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Half Adder Full Adder

Half adder is a combination circuit Full Adder is combinational circuit
that adds two 1 – bit digits that adds three one bit digits
The previous carry is not used The previous carry is used
In half adder there are two input In Full Adder there are three input
bits bits
Sum = a ⊕ b Sum = a ⊕ b ⊕ . Cin
Carry = a * b Carry = (a * b) + (Cin * (a ⊕ b))
It consists of one EX – OR gate & It consists of two EX – OR, two
one AND gate AND gate & one OR gate

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It is used in calculators, computers, It is used in multiple bit addition,
digital measuring devices etc aa
digital processor etc
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Q3(B) Explain NAND gate as universal gate (4M)

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NAND gate as universal gate

 A universal gate is a logic gate which can implement any Boolean
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Function without need to use any other type of logic gates

 The NOR gate & NAND gate are universal gate
 The below diagram is of two input NAND gate. The first part is an
AND gate & second part is dot after it represents a NOT gate

NAND gate as universal gate

a) NOT gate
 In order to get NOT function from NAND gate all input of NAND
gate shorted & it becomes one input

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b) AND gate
 AND gate is realised by inverting output of NAND gate

c) OR gate
 Logic circuit for OR gates from NAND gate is shown in figure ( ).

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d) NOR gate
 NOR gate can be made by inverting output of OR gate

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e) EX – OR gate
 Boolean Expression for EX – OR gate : Y = A𝐵̅ + 𝐴̅B

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f) EX – NOR gate

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Q3(C) Implement 2 – bit magnitude comparator (7M)
ANS
2 – bit magnitude comparator
 A comparator used to compare two binary number each of two bits is
called 2 – bit magnitude comparator
 It consists of four input & three output to generate less than, equal to
and greater than between two binary numbers
 Figure

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 Truth Table
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For Y1 (A > B) :

Y1 = A1A0 ̅̅̅̅
𝑩𝟎 + A0̅̅̅̅
𝑩𝟏 ̅̅̅̅
𝑩𝟎 + A1 ̅̅̅̅
𝑩𝟏

For Y2 (A = B) :

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For Y3 (A < B)

Y3 = ̅̅
𝑨̅̅𝟎 B1 B0 + ̅̅
𝑨̅̅𝟏 B1 + ̅̅
𝑨̅̅𝟏 ̅̅
𝑨̅̅𝟎 B0

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OR : Q3(A) Simplify Boolean Function using K – map

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F(A, B, C, D) = ABCIDI + ABCID + ABCDI + ABICDI (3M)

ANS

F(A, B, C, D) = ABCIDI + ABCID + ABCDI + ABICDI

Simplification of Boolean Function

F = ABCI + ACDI

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OR Q3(B) Explain 4 – bit binary parallel adder (4M)

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4 – bit binary parallel adder

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 4 bit parallel adder is designed using 4 Full Adder : FA0, FA1, FA2, FA3
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 Full Adder FA0 adds A0, B0 along with carry Cin generate sum S0 &
carry bit C1 & this carry bits connected to FA1
 FA1 accepts this carry C1 & adds with its inputs A1 & B1 to generate
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sum S1 & carry C2. This bit C2 is connected to FA2

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 This process continues till last full adder FA ‘n’ accepts to carry bit
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Cin & adds with its input An & Bn to generate final output along with
last carry bit Cout

OR Q3(C) Explain Minterm & Maxterm (7M)

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Minterm
 Complimented or uncomplimentary form of k variable product term
is called the minterm. It means did the mean term is the product
term and the variables are its factors
 Variables are in the complemented or uncomplimentary form

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  For example : function with 2 variables, there are four possible
combinations i.e 𝐴̅ 𝐵̅ , 𝐴̅ B, A𝐵̅ and AB. This product term is called
min term. It is also called standard product or fundamental product
 If in min term the value of variable becomes 1, It is in the
uncomplicated form & if value becomes 0 it is in complicated form
 Min term is shown by m & suffix , min – terms of 3 variables
functions is expressed by m0, m1, m2, m3, m4, m5, m6 & m7
 Suffix shows decimal number equivalent to the minterm
 For example, equivalent binary number of min term A𝐵̅ C is 101
which represent decimal number 5
Decimal A B C Min term
Equivalent
0 0 0 0 ̅𝑩
𝑨 ̅𝑪̅
1 0 0 1 ̅𝑩
𝑨 ̅C
2 0 1 0 ̅ 𝑩𝑪
𝑨 ̅

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3 0 1 aa 1 ̅ 𝑩𝑪
𝑨
4 1 0 0 A𝑩̅𝑪̅
5 1 0 1 A𝑩̅𝑪
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6 1 1 0 AB𝑪 ̅
7 1 1 1 ABC
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Maxterm
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 Sum terms of key variables with complements or uncomplemented

form is called max term which means max term is sum term and its
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variables are its factor

 Variables are in the complimented or uncomplimented form. For
example, a function with 2 variables A & B has four possible
combinations such as 𝐴̅ + 𝐵̅, 𝐴̅ + B, A + 𝐵̅ and A+ B
 This sum terms is called max term. If value of variable is 0 it is
uncomplicated form & if its value is 1 it is in complicated form
 Max terms of three variables are shown in M0, M1, M2, M3, M4, M5,
M6 & M7
 For example equivalent binary number of max term 𝐴̅ + ̅̅̅̅̅ 𝐵 + 𝐶̅ is
110, it represents decimal number 6

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Q4(A) Give difference between Sequential & Combinational Circuit (3M)

ANS

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Sequential Circuit Combinational Circuit
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In this memory element is also In this only logic gates are used.
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used in addition to logic gates No memory element is used
In output at any instant is Output at any instant depends
dependent also on past condition only on input conditions at that
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of output i.e addition to condition instant

of that instant
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Design is difficult due to presence Design is simple due to absence of

of memory element memory element
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Comparatively less hardware is More hardware is required

needed
Cost is less Cost is more as hardware is
needed

Q4(B) Explain look – ahead carry generator (4M)

ANS
 The adder carry propagation delay while performing other arithmetic
operations like multiplication & division as it uses several adder or
subtraction steps
 A carry look – ahead adder reduces propagation delay by introducing
more complex hardware

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  In this design the ripple carry design is suitably transferred such that
carry logic or fixed group of bits of adder is reduced to two level logic
 Circuit

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 Truth Table
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Q4(C) Explain J – K Flip Flop (7M)

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J – K Flip Flop
 In RS FF condition S = R = 1 is prohibited because state of output. This
is limitation of SR FF
 In JK FF this limitation is removed this means that condition J = K = 1
is not prohibited

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 JK FF is realised by connecting two 3 – input AND gates in SR FF. One
input of each AND gate is joined together and it is connected to clock
 J & K input are applied to gates A & B respectively, 𝑄̅ is connected to
one input of AND gate A , Q output is connected to one input of AND
gate B

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 When both J & K are at 0 level both the gates A & B are disabled
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output of both gates is 0. So both S & R are also level so there is no
effect of clock signal that means that if clock is 0 level or 1 level FF
remains in level state
 When J = 0 and K = 1 , state A is disabled so output so input is 0. At
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this time if FF is set state (Q = d). This 1 is given to input of given B so

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when clock becomes 1, gate B is enabled and its output becomes 1 so

R becomes 1 so as S = 0 and R = 1, FF sets
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 But if would have been when J = 0 and K = 0 gate would not have
enabled & flip flop would have remained in reset state only. In short,
FF is not in reset state when J = 0 and K = 1 resets when clock
becomes 1. It remains in reset state if it is already in reset state

 When J = 01 and K = 0 gate B is disabled and its output becomes 0 so

R = 0 if at this time and 𝑄̅ = 1 gate A enables when clock becomes 1.
So becomes 1 and FF sets i.e Q = 1 but at this time if Q = 1 & 𝑄̅ = 0

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  When J = K = 1 if at that time Q = 1 then 𝑄̅ = 0, A disables and S
becomes 0. Two input of gate R and so when clock becomes 1 gate, B
enables. So R becomes 1 so FF resets i.e Q becomes 0

State Transition diagram of J – K Flipflop

Truth Table
Qn J K Qn+1

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0 0 0 0
0
0
0
1
1
0
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1
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0 1 1 1
1 0 0 1
1 0 1 0
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1 1 0 1
1 1 1 0
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Excitation table for J – K Flip Flop

Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Characteristics equation of JK Flip Flop

̅
Qn+1 = QnJ + Qn 𝑲

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OR Q4(A) Explain NAND SR Latch (3M)

ANS
 Latches are basics storage elements set operate with signal levels.
Latches constructed by clock transition are Flip – Flops
 Latches are local sensitive
 SR Latch
 They are also known as preset & clear latch. The SR latch forms
basic building blocks of all either types of flip – flops
Q QI State
1 0 Set
0 1 Reset

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 Circuit Diagram
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 Case 1 : S = R = 1
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 If Q = 1, Q & R input for 2nd NAND gate are both 1

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 If Q = 0, Q & R input for 2nd NAND gates are 0 & 1 respectively

 Case 2 : S = 0, R = 0
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 As S = 0, output of 1st NAND gate Q = 1 (set state). In 2nd NAND

gate as Q & R inputs are 1, QI = 0
 Case 3 : S = 1 , R = 0
 As R = 0, output of 2nd NAND gate, QI = 1 in 1st NAND gate as Q &
S input are 1, Q = 0 (reset)
 Case 4 : S = 0 , R = 0
 When S = R = 0 both Q & QI becomes 1 which is not allowed so
input condition is prohibited
 Truth Table
S R Output
1 1 No change
0 1 1
1 0 0
0 0 Invalid state

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OR Q4(B) Explain Clock Triggering mechanism (4M)

ANS
 Following are two possible types of Triggering that are used in sequential
circuit
1. Level Triggering
2. Edge Triggering

1) Level Triggering
 There are two levels namely Logic High & Logic Low in clock signal.
Following are two types of level triggering
a) Positive Level Triggering
b) Negative Level Triggering
 Positive Level Triggering

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 If sequential circuit is operated with clock signal when it is in
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logic high, then that type of triggering is known as positive
level triggering
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 It is highlighted in above figure
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 Negative Level Triggering

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 If sequential circuit is operated with clock signal when it is in

logic low, then type of triggering is known as negative level
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triggering
 It is highlighted in above figure

2) Edge Triggering
 There are two types of transitions that occurs in clock signal. That
means, clock signal transitions either from logic low to logic high
or logic high to logic low
 Following are two types of edge triggering based on transitions of
clock signal
a) Positive Edge Triggering
b) Negative Edge Triggering

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  Positive Edge Triggering
 If sequential circuit is operated with clock signal that is
transitioning from logic low to logic high, then that type of
triggering is known as positive edge triggering. It is also
called as rising edge triggering

 Negative Edge Triggering

 If sequential circuit is operated with clock signal that is
transitioning from logic high to logic low, then that type of
triggering is known as negative edge triggering. It is also
called as falling edge rising

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OR Q4(C) What is race around condition? How to solve it? (7M)
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Race – Around Condition

 For J – K Flip Flop, if J = K = 1 and if clk = 1 for long period of time
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then output Q will toggle as long as the clock remains high which
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makes the output unstable or uncertain

 This is called a race around condition in JK flip flop
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 We can overcome this problem by making clock = 1 for very less

duration
 The circuit used to overcome race around condition is called Master
Slave J – K Flip Flop

Solution
1) Clock pulse width should be less than propagation delay i.e Tp < Δt
2) Delayed line is connected in series with the feedback connection
3) Edge Triggered JK FF is used instead of level triggered JK FF
4) JK Master Slave FF is used

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Master Slave J – K Flip Flop
 Here 2 JK flip flops are connected in series
 The first JK flip flop is called the master and the other is called Slave
 Output from the master is connected to the two inputs of slave
whose output is feedback to inputs of the master
 The circuit also has an inverter other than 2 flip flops
 The clock pulse & inverter are connected because of which flip flops
gets an inverted clock pulse
 In other words, if Cp = 0 for master flip flop then Cp = 1 for slave flip
flop and vice – versa

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Working
 When the clock pulse goes high the slave isolated J & K inputs can
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affect the state of the system. The slave flip flops isolated when the
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clock goes low

 When does CP goes back to the information is transmitted from the
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master flip flop to the slave flip flop and output is obtained
 As the master flip flop is positive triggered inter response first and
the slave later
 The master goes to the K– input of slave. When both inputs J = 0 and
K = 1 and also QI = 1. In this case the slave copies the master as clock
forces slave to reset
 The master goes to the J input of slave. When both J = 1 and K = 0,
Q = 1. The clock is set to the negative transition of clock
 There is a state of toggle when both J = 1 and K = 1 on negative
transition of clock slave toggles and master toggles on positive
transition of clock
 Both the flip flop are disabled when both J = 0 and K = 0 and Q is
unchanged

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Q5(A) Classify different types of Digital to Analog Convertor (3M)

ANS

 A digital to analog convertor (DAC) converts digital input signal into

analog output signal
 The digital signal is represented with binary code which is
combination of bits 0 and 1
 Diagram

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 A digital to analog (DAC) consists of number of binary inputs and
single output
 In general, number of binary inputs of DAC will be power of two
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 Types of DACs
1) Weighted Resistor DAC
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2) R – 2R ladder DAC
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Q5(B) Compare static RAM & dynamic RAM (4M)

ANS
SRAM DRAM
Constructed of tiny capacitors that Constructed of circuit similar to D
leak electricity flip – flop
Requires a recharge every few Holds its constraints as long as
milliseconds to maintains its data power is available
Inexpensive Expensive
Slower than DRAM Faster than SRAM
Can store memory bits per chip Cannot store memory bits per chip
Uses less power Uses more power
Generate less heat Generates more heat

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Q5(C) List different types of ROM. Also explain (7M)

ANS

ROM
 ROM stands for Read – Only Memory. It is non volatile memory that
is used to store important information which is used to operate
system
 As its name refers to read only memory we can only read programs &
data stored on it
 It is also primary memory unit of computer system
 It contains some electronic fuses that can be programmed for piece
of specific information
 The information stored in ROM in binary format. It is also known as

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permanent memory aa
 Features
 ROM is non volatile memory
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 Information stored in ROM is permanent

 Information & programs stored on it we can only read
 Information & programs are stored on ROM in binary format
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 It is used in start – up process of computer

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 Types of ROM
1) PROM : Programmable Read Only Memory
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2) EPROM : Erasable Programmable Read Only Memory

3) EEPROM : Electrically Erasable Programmable Read Only
Memory
4) MROM : Masked Read Only Memory
5) Flash Memory

Q5(A) Discuss application of shift register (3M)

ANS
Applications of Shift Register
 Shift Register is used as parallel to serial converter which converts
parallel data into serial data. It is utilized at transmitter section after
analog to digital converter ADC block

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  Shift Register is used as serial to parallel converter which converts
serial data into parallel data. It is utilized at receiver section & ones.
Hence, it is used as sequence generator
 Shift Registers are also used as counters. There are 2 types of
counters based on type of output from right most D Flip – Flop is
connected to serial input
1) Ring counter
2) Johnson Ring Counter

OR Q5(B) Explain working of Counter (4M)

ANS

 A special type of sequential circuit used to connect pulse is known as

counter or collection of flip – flops where clock signal is applied is

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known as counter aa
 The counter is one of widest applications flip – flop based on clock
pulse, output of counter contains predefined state. The number of
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pulse can be counted using output of counter

 The main properties of counter are timing sequencing & counting
counter works in two modes
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1) Up Counter
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2) Down Counter
 Types of Counter
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1) Asynchronous Counter
2) Synchronous Counter

1. Asynchronous Counter
 Asynchronous Counter is asynchronous sequencing circuit. Its
main feature is that clock pulse terminals of interval. Flip – Flop
are not all connected. Therefore, flipping time of each flip – flop
is not uniform & its output may produce interfaces glitches, but
its circuit is simple

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 2. Synchronous Counter
 Synchronous Counter refers to cumulative value of measured
value which is characterised by greatly increasing working
frequency of counter

OR Q5(C) Describe operation of D/A Converter with Binary – Weighted

Resistors (7M)

ANS
 A DAC is an electronic circuit that takes in digital data as input &
transforms it into output analog signal
 It is actually output voltage proportional to binary code given at DAC
input & then used to drive various circuits

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Binary Weighted Resistors DAC
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 It is type of DAC that transforms particular binary code into an
equivalent analog signals. If binary code given at input terminal is
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altered continuously, output will change as well. This type consists of
weighted resistors whose values are kept as multiples of two &
inverted summing operational amplifier which results in output signal
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180 degree phase shift

 The reference voltage is either generated internal is provided to DAC
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converter to decide maximum output voltage of converter

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 Before discussing transfer function of binary – weighted resistors DAC

we should be families with resolution & full scale output voltage
 DAC Resolution = 2n
 Step Size = Vref/2n
𝑽𝒓𝒆𝒇 (𝟐𝒏 −𝟏)
 Full Scale Output Voltage =
𝟐𝒏

 Working
 The configuration uses summing amplifier whose output
voltage is proportional to sum of voltages applied at input

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 𝑹𝒇 𝑹𝒇 𝑹𝒇 𝑹𝒇
Vout = {( ) 𝑽𝟎 + ( ) 𝑽𝟏 + ( ) 𝑽𝟐 + ⋯ ( ) 𝑽𝒏−𝟏 }
𝑹𝟎 𝑹𝟏 𝑹𝟐 𝑹𝒏−𝟏

 Circuit
 If resistors with precise values are connected to each of input
voltage to scale gain, it starts working as DAC. All input volts are
connected in same reference voltage. So formula becomes

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