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Digital System Design-Module02-Hierarchical Modeling Concepts

The document outlines the hierarchical modeling concepts in digital system design, focusing on top-down and bottom-up design methodologies. It explains the structure of modules in Verilog, the four levels of abstraction, and the components necessary for simulating digital designs, including stimulus blocks. Additionally, it provides examples of design implementation and testing through testbench code.

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Muhammad Faizan
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© © All Rights Reserved
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Digital System Design-Module02-Hierarchical Modeling Concepts

The document outlines the hierarchical modeling concepts in digital system design, focusing on top-down and bottom-up design methodologies. It explains the structure of modules in Verilog, the four levels of abstraction, and the components necessary for simulating digital designs, including stimulus blocks. Additionally, it provides examples of design implementation and testing through testbench code.

Uploaded by

Muhammad Faizan
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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MIRPUR UNIVERSITY OF SCIENCE AND TECHNOLOGY (MUST), MIRPUR

DEPARTMENT OF ELECTRICAL ENGINEERING


DIGITAL SYSTEM DESIGN
EE-474

Module No. 02 : Hierarchical Modeling Concepts

Engr. Jabbar Younis


Lecturer

Date: October 26, 2020


Learning Objectives

• Understand top-down and bottom-up design methodologies for digital design

• Explain differences between modules and module instances in Verilog

• Describe four levels of abstraction - - behavioral, data flow , gate level, switch
level – to represent the same module

• Describe components required for the simulation of a digital design. Describe a


stimulus block and a design block. Explain two methods of applying the stimulus

Digital System Design EE-474 (Summer 2020) 3


Lecture 1: Key Points

• Design Methodologies

• Modules

• Instances

• Components of simulation

• Stimulus Block

• Trends in HDLs

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Design Methodologies

• Two basic types of digital design methodology:

• Top-Down design methodology

• Bottom-up design methodology

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Top-Down Methodology
• We define the top-level block and identify the sub-blocks
• Sub-blocks subdivided until we reach leaf cells
• Leaf cells that can not be further subdivided

Digital System Design EE-474 (Summer 2020) 6


Bottom-up Methodology
• We identify the building blocks available to us
• Bigger cells are build using these building blocks
• These cells then used for higher level blocks to make top-level block

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Example: 4-bit Ripple Carry Counter

• Ripple carry counter made of negative edge-triggered toggle flip-flops (T-FFs)


• Each T-FF made up from negative edge-triggered D-fliflops (D-FF) and inverters

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Example: 4-bit Ripple Carry Counter

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Modules

• Verilog provides the concept of a module


• Module is a basic building block in Verilog
• Can be an element or collection of lower level design blocks
• Provides necessary functionality to higher level blocks through port
interface (inputs and outputs)
• In Verilog module is declared by keyword module
• endmodule keyword must appear at the end of module definition

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Modules

• Each module must have a module name, an input and output


terminal list
• Typical syntax of module in Verilog is as follows:

Digital System Design EE-474 (Summer 2020) 11


Levels of Abstraction in Verilog

• Verilog is both a behavioral and a structural language


• Internals of each module can be described at four levels of
abstraction
• Behavioral or algorithmic level
• Dataflow level
• Gate Level
• Switch Level

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Levels of Abstraction in Verilog

• Behavioral or algorithmic level


• Highest level of abstraction
• Module can be designed without concern for the hardware implementation details
• Dataflow level
• Module designed by specifying dataflow, how it flows between hardware registers
• Gate Level
• Module implemented in terms of logic gates and interconnects between these gates
• Switch Level
• Lowest level of abstraction in Verilog. Module implemented in terms of switches, storage
nodes and interconnections between them

Digital System Design EE-474 (Summer 2020) 13


Instances

• Module provides a template from which actual objects can be created


• Each object has its own name, variables and parameters
• Process of creating objects from module template is called
instantiation
• Objects created are called instances

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Instances (Example)

Digital System Design EE-474 (Summer 2020) 15


Stimulus Block

• Design must be tested, once it is completed


• Functionality can be tested by applying stimulus and such a block is
called stimulus block
• Also known as testbench
• Two styles of stimulus application

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Stimulus Block

• In first, style,the stimulus block instantiates the design block and


directly derives the signal

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Stimulus Block

• In second style, both stimulus and design blocks are instantiated in a


top-level dummy module

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Example

Top Block

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Example

Sub-Block 1

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Example

Sub-Block 2

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Example

Simulation Waveform

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Example

Simulation Waveform

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Example

Test-bench code:

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Example

Test-bench code:

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Example

Output:

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References

• VERILOG HDL”-A guide to digital design and synthesis by Samir


Palnitkar, Prentice Hall Publisher

Digital System Design EE-474 (Summer 2020) 27


End of Lecture

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