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CH_2 Bus interconnection system

The document discusses bus interconnection systems, emphasizing their critical role in communication architecture and overall system performance. It covers various aspects such as bus types, arbitration methods, timing, and design elements that influence data transfer and efficiency. The importance of bus design in optimizing speed, power consumption, and cost in complex systems is highlighted throughout the chapter.

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CH_2 Bus interconnection system

The document discusses bus interconnection systems, emphasizing their critical role in communication architecture and overall system performance. It covers various aspects such as bus types, arbitration methods, timing, and design elements that influence data transfer and efficiency. The importance of bus design in optimizing speed, power consumption, and cost in complex systems is highlighted throughout the chapter.

Uploaded by

amanuel
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter

BUS INTERCONNECTION SYSTEM


Two(2)
COMPILED BY ABEL H. [email protected] 1
INTRODUCTION
❖Communication is the most critical aspect affecting system performance.
❖Communication architecture consumes up to 50% of total on-chip power.
❖Communication architecture design, customization, exploration,
verification and implementation takes up the largest chunk of a design
cycle.
❖Communication Architectures in complex systems significantly affects
performance, power, cost & time-to-market.
❖Bus is made of wires shared by multiple units with logic to provide an
orderly use of the bus.

COMPILED BY ABEL H. [email protected] 2


BUS INTERCONNECTION SYSTEM
❖The simplest and most common way of interconnecting various parts of
the computer. To achieve a reasonable speed of operation, a computer
must be organized so that all its units can handle one full word of data at
a given time. A group of lines that serve as a connecting port for several
devices is called a bus. In addition to the lines that carry the data, the
bus must have lines for address and control purpose. Simplest way to
interconnect is to use the single bus as shown.

COMPILED BY ABEL H. [email protected] 3


CONT.
❖In interconnection system Devices can be Masters or Slaves.
❖Arbiter determines - which device will control the bus.
❖Bus protocol is a set of rules for transmitting information between two
or more devices over a bus.
❖Bus bridge connects two buses, which are not of the same type having
different protocols.
❖Buses may be unified or split type (address and data).

COMPILED BY ABEL H. [email protected] 4


PERFORMANCE
❖The most important measure of the performance of a computer is how
quickly it can execute programs. The speed with which a computer
executes program is affected by the design of its hardware. For best
performance, it is necessary to design the compiles, the machine
instruction set, and the hardware in a coordinated way.
❖Just as the elapsed time for the execution of a program depends on all
units in a computer system, the processor time depends on the hardware
involved in the execution of individual machine instructions. This hardware
comprises the processor and the memory which are usually connected by
the bus.

COMPILED BY ABEL H. [email protected] 5


SYSTEM BUS
❖is a collection of wires through which data is transmitted from one unit to
another in computer system (CPU, memory, and I/O devices). It is further
divided in to three logical units, namely the address bus, data bus, and
control bus.
❖Control bus It is responsible for making CPU, memory, and I/O devices
work together as a functional system, carrying signals that report the
status (ready, not ready), or read write control signals between various
units.
❖Address bus It informs the CPU about the location of the data residing
in the memory.
❖Data bus it transfers the actual data between the processor, memory,
and the I/O devices.
COMPILED BY ABEL H. [email protected] 6
BUS DESIGN ELEMENTS
1. bus types
A. Dedicated Bus A line is permanently assigned either to one function ,
or a specified computer component.
E.g. The use of separate dedicated address and data line.
B. Multiplexed Bus using the same lines for multiple purposes.
E.g. Address and data information my transmitted over the same set of
lines. At the beginning of the data transfer the address is placed on the
bus and the address valid control line is activated.

COMPILED BY ABEL H. [email protected] 7


CONT.
Arbitration: deciding who gets access to the bus, for driving the
transaction. It is decided centrally by the bus master/controller. And there
is always one master device per bus.
2. Method of Arbitration
A. Centralized:
a single hardware device called the bus master/controller or arbiter
allocate time on the bus. The device might be a separate or a part of a
processor.
B. Distributed: There is no centralized controller. Each module contains
assess control logic and the module act together.
COMPILED BY ABEL H. [email protected] 8
CONT.
Arbitration Mechanism
A. Daisy Chain(Chaining)
steps: 1. if bus not busy, make request
2. Master activates bus grant
3. if device gets bus grant, mark bus busy.

advantage disadvantage
1. simple 1. Hardwired priority
2. only three extra lines 2. poor fault tolerance
COMPILED BY ABEL H. [email protected] 9
CONT. (ARBITRATION MECHANISM)
B. Polling
Steps:1. if not busy, make bus request.
2. master polls by placing device Id on polling lines(Master decides priority).
3. if device gets bus grant, mark bus busy.

Advantage disadvantage
1. No disadvantage of daisy chain 1. extra polling line
2. Dynamic priority 2. Polling delay
COMPILED BY ABEL H. [email protected] 10
CONT. (ARBITRATION MECHANISM)
C. Independent Request
Steps: 1. if not busy, make bus request.
2. master decides who gets access, and indicates through grant line.
3. if device gets bus grant, make bus busy.

Adv disadvantage
1. Fast 1. 2n lines for n devices
2. Dynamic priority
COMPILED BY ABEL H. [email protected] 11
CONT.
3. Timing
A. synchronous Timing
❖Bus includes a clock line upon which a clock transmits a regular sequence
of alternating 1’s and 0’s. a single 1-0 transition is referred to as a clock
cycle or bus cycle. All the other devices on the bus can read the clock line.
❖All events start at the beginning of a clock cycle.
B. Asynchronous Timing
❖The occurrence of one event on a bus follows and depends on the
occurrence of previous event. Harder to implement and text than
synchronous timing.
COMPILED BY ABEL H. [email protected] 12
CONT. BUS DESIGN ELEMENTS
4. Bus Width
❖The width of data bus has an impact on the system performance. The wider
the data bus, the greater number of bit transferred at one time.
❖The wider the address bus, the greater range of location that can be
referenced.
5. Data Transfer Type
a. Read-Modify-Write: A read followed immediately by a write to the same
address.
b. Read-After-Write: Consisting of a write followed immediately by a read
from the same address.
6. Block Data Transfer
❖One Address cycle followed by n data cycles. First data item to or from
specified address. Remaining data items to or from subsequent addresses.
COMPILED BY ABEL H. [email protected] 13
END OF CHAPTER TWO COA

COMPILED BY ABEL H. [email protected] 14

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