Internship Report
Internship Report
(Deemed to be University)
School of Engineering & Technology
Department of Electronics and Communication Engineering
CIRCULAR
To: Dr. Pratima Mehta, Associate Professor, ECE Deptt, SET, MRIIRS
Copy to: All HoD, MRIIRS– Please attend the STC as scheduled above.
All Deans For kind information
Director (IQAC) For kind information
PVCs, MRIIRS For kind information
PS to VC-MRIIRS For kind information
Manav Rachna International Institute of Research and Studies
(Deemed to be University)
School of Engineering & Technology
Department of Electronics and Communication Engineering
BY-
- Manmath prasad
Panda- BMM-01
- Sahil Sharma
-BEE-01
- Neha Sharma
-BEE-06
- Shivangi
Sharma -
BEC-25174
(Maharishi
Dayanand
University
Rohtak) Manav Rachna International Institute of
- Ayushi Nagrota Research and Studies
- BEC-L1 (Deemed to be University)
School of Engineering & Technology
Department of Electronics and Communication Engineering
Acknowledgment
K-Map
A pictorial method that is utilised to minimise various
Boolean expressions without using the Boolean algebra
theorems along with the equation manipulations.
4 TO 1 MULTIPLEXER CIRCUIT
DIAGRAM
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
Inputs Outputs
A B S (Sum) C (Carry)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Full Adder
A full adder is a digital circuit that performs
addition. A full adder adds three one-bit
binary numbers, two operands and a carry
bit.
Full adder Block & Circuit Diagram
Full adder Truth Table
Inputs Outputs
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Encoder
An Encoder is a combinational circuit that
performs the reverse operation of a Decoder.
It has a maximum of 2^n input lines and 'n'
output lines, hence it encodes the
information from 2^n inputs into an n-bit
code. It will produce a binary code equivalent
to the input, which is active High.
Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
E A1 A0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
Sequential Circuit
The sequential circuit is a special type of circuit
that has a series of inputs and outputs. The outputs
of the sequential circuits depend on both the
combination of present inputs and previous
outputs.
Flip Flops
Block diagram
Truth Table
Circuit Diagram
D-Flip Flop
Block diagram
Truth Table
Circuit Diagram
Block diagram
Truth Table
Circuit Diagram
T Flip Flop
Block diagram
Truth Table
Circuit Diagram
STICK DIAGRAM
Layout of circuit
VLSI design aims to translate circuit concepts onto silicon. stick
diagrams are a means of capturing topography and layer
information using simple diagrams. Stick diagrams convey layer
information through colour codes (or monochrome encoding). Acts
as an interface between symbolic circuit and the actual layout.
Green – PMOS -
n difference(nmos)
Yellow- SOURCE- UPPER
p difference ( pmos)
SIDE
DRAIN
–BELOW
NMOS - DRAIN
– ON UPPER SIDE
SOURCE- BELOW
SIDE
AIM- To draw the stick diagram layout circuit of
following-
1. NOR
2. NOT
3. {A+B+C} COMPLEMENT
4. {(A+B) C} Complement
5. (A B C) Complement
1.NOR
2. NOT
3.{A+B+C} COMPLEMENT
4.{(A+B) C} Complement
5.(A B C) Complement
PROGRAM NO. 1
Program:
module and_2(a, b, s);
input a, b;
output s;
assign s=a&b;
End module
PROGRAM NO. 2
Program:
module nand_2(a, b,s);
input a,b;
output s;
assign s=a~&b;
Endmodule
PROGRAM NO. 3
Program:
module or_2(a,b,s);
input a,b;
output s;
assign s=a||b;
Endmodule
PROGRAM NO. 4
Program:
module nor_2(a,b,s);
input a,b;
output s;
assign s=a~||b;
Endmodule
PROGRAM NO. 5
Program:
module not_2(a,b,s);
input a,b;
output s;
assign s=a~b;
Endmodule
PROGRAM NO. 6
Program:
module xor_2(a,b,s);
input a,b;
output s;
assign s=a^b;
Endmodule
PROGRAM NO. 7
Program:
module xnor_2(a,b,s);
input a,b;
output s;
assign s=a~^b;
Endmodule
PROGRAM NO. 8
Program:
module halfadder(a,b,s,c);
input a,b;
output s,c;
assign s=a^b;
assign c= a&b ;
Endmodule
PROGRAM NO.9
Program:
module fulladder (a,b,c,s,z);
input a,b,c;
output s,z;
assign s=a^b^c;
assign c=a&b||a&c||b&c;
Endmodule
PROGRAM NO.10
Program:
module SR_ff(s,r,clk,rst_n,q,qbar);
input s,r,clk,rst_n;
output q,qbar;
reg q,qbar;
always@(posedge clk)
begin
if(!rst_n);
q<=0;
else
begin
case(s,r);
2'00:q<=q;
2'01:q<=0;
2'10:q<=1;
2'11:q=x;
endcase
end
end
assign qbar=~q;
Endmodule
PROGRAM NO.11
input clk,dr,j,k;
output q,qbar;
reg q,qbar;
reg t=1'b0;
begin
if(clk)
t<=1'b0;
else
case({k,j})
2'b00:t<=t;
2'b01:t<=1'b1;
2'b10:t<=1'b0;
2'b11:t=~t;
default:t<=t;
endcase
end
always@(*)
begin
q<=t;
qbar<=~t;
end
Endmodule
PROGRAM NO.12
Program:
module D_FF(din,en,q);
input din,en;
output q;
reg q;
reg t=1'b0;
always@(en or din)
begin
if(en)
q<=din;
else
q<=1b’0;
End
Endmodule
PROGRAM NO.13
input[3:0]in;
input[1:0]sel;
output out;
reg out;
always@(in or sel)
begin
if(in)
case(sel)
2'b00: out<=in[0];
2'b01: out<=in[1];
2'b10: out<=in[2];
2'b11: out<=in[3];
default: out<=1'b0;
endcase
else
out<=1'b0;
end
Endmodule
Result:
PROGRAM NO. 14
Program:
module decoder_24(in,en,out);
input[1:0]in;
input en;
output[3:0]out;
and[0] (~in[0],~in[1],en,out[0]);
and[1](in[0],~in[1],en,out[1]);
and[2](~in[0],in[1],en,out[2]);
and[3](in[0],in[1],en,out[3]);
Endmodule