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How-to

This document provides a detailed guide for implementing the UIO module in a project using the ZCU102 Evaluation Board with specific software prerequisites. It outlines steps for creating interrupt input pins, configuring GPIO settings, modifying device tree source files, and testing the setup. Additionally, it includes references for further reading and troubleshooting related to UIO interrupts on Zynq devices.

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11 views10 pages

How-to

This document provides a detailed guide for implementing the UIO module in a project using the ZCU102 Evaluation Board with specific software prerequisites. It outlines steps for creating interrupt input pins, configuring GPIO settings, modifying device tree source files, and testing the setup. Additionally, it includes references for further reading and troubleshooting related to UIO interrupts on Zynq devices.

Uploaded by

trandinhvinhwiz14
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Demo Design: UIO IRQ

Draft v3.0
Alex He ([email protected])
The design show how to implement the UIO module in project.
Git: https://gitenterprise.xilinx.com/AlexHe/UIO_Linux_Demo

Prerequisites
- Vivado 2017.2
- Petalinux 2017.2
- ZCU102 EVB final v1.0

STEP

Create 4 interrupt input pins of zcu102 EVB

Use the GPIO_DIP_SW[0-7]:SW13 of User I/O (Refer to UG1182-ZCU102 Evaluation Board)

Connect the 4 ports to pl_ps_irq0 through xlconcat.


In0 – Edge/Raising Edge  pl_irq_er (AN14, SW13.8, DIP0)
In1 – Edge/ Falling Edge  pl_irq_ef (AP14, SW13.7, DIP1)
In2 – Level/Active High  pl_irq_lh (AM14, SW13.6, DIP2)
In3 - Level/Active Low  pl_irq_ll (AN13, SW13.5, DIP3)

© Copyright 2018 Xilinx


Add constrains (refer to UG1182, ZCU102 BOARD Constraints File Listing)

Add a GPIO interrupt source

GPIO IP setting with enable interrupt

© Copyright 2018 Xilinx


Connect the GPIO to PL LEDs (led_8bits) on board.

Then the 5 pl_ps_irq[4:0] was created in sequence as Table 13-1 of UG1085.

So the IRQ number for the 5 input are here.


IRQ source IRQ number Board Info
pl_irq_er 121 SW13.8, DIP0
pl_irq_ef 122 SW13.7, DIP1
pl_irq_lh 123 SW13.6, DIP2
pl_irq_ll 124 SW13.5, DIP3
axi_gpio_1 125

Address Map

© Copyright 2018 Xilinx


Then use the IPI flow to create the bitstream and export the Hardware(HDF)
The design diagram is here.

Create the petalinux project with the HDF

$petalinux-create -t project --template zynqMP -n zcu102-pl2ps_irq


$cd ./ zcu102-pl2ps_irq
$petalinux-config --get-hw-description <path of HDF>
$petalinux-config -c kernel
Enable UIO_PDRV_GENIRQ driver
CONFIG_UIO=y
# CONFIG_UIO_CIF is not set
CONFIG_UIO_PDRV_GENIRQ=y
$petalinux-build -c device-tree
The pl.dtsi is created in ./components/plnx_workspace/device-tree-generation/ as below.

© Copyright 2018 Xilinx


The DTS should be modified for
1. Refine the axi_gpio_1 node as UIO
a) Change the interrupts value from 89 to 93
b) Change the compatible to “generic-uio” to use UIO_PDRV_GENIRQ driver.
2. Add UIO node for the each 4 DIP ports (to trigger pl_ps_irq0[3:0])
a) Set the interrupts value from 89 to 92
b) Set compatible to “generic-uio”
*The interrupt value of node in DTS has an offset 32 of the IRQ number (Table 13-1: System Interrupts, UG1085).
E.g.
The value 89 should add 32 to get the real hardware IRQ number which is 121, i.e. the first interrupt number of pl_ps_group0.
*DTS interrupts binding

Set the UIO nodes in ./project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi

© Copyright 2018 Xilinx


*The UIO_PDRV_GENIRQ driver never use fixed compatible table now. So there are two ways to make this driver to
match the UIO device node in DTS.
1. bootargs use “uio_pdrv_genirq.of_id=generic-uio”
2. insmod uio_pdrv_genirq.ko of_id=generic-uio when install the driver

Test

Boot to kernel with uio_pdrv_genirq.ko auto loaded. The /dev/uiox has been created.

Check the /proc/interrupts.

© Copyright 2018 Xilinx


Why no IRQ 122-edge falling and 124-level low?
*These two type interrupt is not support by hardware. See the kernel dmesg log bellow.

Switch each DIP0(SW13.8) and DIP2(SW13.6) one time to trigger the interrupts.

© Copyright 2018 Xilinx


Test the DIP UIO

Refer to https://01.org/linuxgraphics/gfx-docs/drm/driver-api/uio-howto.html

So do the enable IRQ by “echo 0x1 > /dev/uioX” (write system call which trigger the irqcontrol) after each time the interrupt
triggered by the DIP switch. The two DIP UIO is /dev/uio1 and /dev/uio2 in kernel.

Another test with user application.

pin-uio-test.c pin-uio-test

Run the application and trigger the interrupt by DIP switch.

Test the GPIO UIO which is /dev/uio0 in kernel

gpio-uio-test.c gpio-uio-test

This test application mmap out the registers from hardware to user space. Then enable all the IRQ bits in GIER and IP_IER
registers and dump out all the registers’ values. Please refer to pg144-axi-gpio.pdf for the IP.

© Copyright 2018 Xilinx


Test step and log.

Reference
https://01.org/linuxgraphics/gfx-docs/drm/driver-api/uio-howto.html

[Xilinx]

Simple PL-PS interrupt difficulty (Vivado 2017.2 + PetaLinux)

PL to PS interrupt in linux /proc/interrupts

UIO Interrupts on Zynq (refer to https://embeddedcentric.com/interrupts/ )

UIO interrupt with PS GPIO

Petalinux 2016.3 UIO

petalinux not creating uio

http://www.wiki.xilinx.com/GIC

© Copyright 2018 Xilinx


[uImage.FIT]

https://github.com/wowotechX/u-boot/tree/x_integration/doc/uImage.FIT

http://www.wiki.xilinx.com/U-Boot+Images

UG1085 - Zynq UltraScale+ MPSoC Technical Reference Manual

UG1182 - ZCU102 Board User Guide

PG144 - axi-gpio

Questions:

© Copyright 2018 Xilinx

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