Biasing of FETs and MOSFETs

FET biasing

Fixed bias Configuration

 Dc bias of a FET device needs setting of 𝑉𝐺𝑆 to give desired𝐼𝐷 .

 For a JFET, drain current is limited by the saturation current𝐼𝐷𝑆𝑆 .

 Since the JFET has such a high input impedance that no gate current flows and
the dc voltage of the gate set by a fixed battery voltage.

 Fixed dc bias is obtained using a battery𝑉𝐺𝐺 . This battery ensures that the gate
is always negative w.r.t. the source and no current flows through the resistor
𝑅𝐺 and gate terminal i.e. 𝐼𝐺 = 0 . The battery provides a voltage 𝑉𝐺𝑆 to bias
the n-channel JFET, but no resulting current is drawn from the battery𝑉𝐺𝐺 . The
dc voltage drop across 𝑅𝐺 is equal to 𝐼𝐺 𝑅𝐺 i.e. 0 volt.
 The gate-source voltage 𝑉𝐺𝑆 is then
𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = −𝑉𝐺𝐺

 The gate-source current 𝐼𝐷 is then fixed by the gate-source voltage as

determined by the equation
𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
𝑉𝑃

 This current then causes a voltage drop across the drain resistor 𝑅𝐷 and is
given by
𝑉𝑅𝐷 = 𝐼𝐷 𝑅𝐷

And the output voltage

𝑉0 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷

 Since 𝑉𝐺𝐺 is fixed value of dc supply and the magnitude of 𝑉𝐺𝑆 is also fixed,
hence the circuit is named as fixed-bias circuit.

 Since this bias circuit uses two batteries 𝑉𝐺𝐺 and 𝑉𝐷𝐷 , it is also known as two
battery bias circuit.

 A FET has high input impedance. To make advantage of it, 𝑅𝐺 should be as

large as possible so that input impedance of the circuit remains high. A
reasonable upper limit is 1MΩ. Normally 𝑅𝐺 should not exceed this value.
Graphical Analysis

A graphical analysis would require a plot of Shockley’s equation as shown in Fig. By choosing
𝐼
𝑉𝐺𝑆 = 𝑉𝑃 /2 will result in a drain current of 𝐷𝑆𝑆⁄4 when plotting the equation. For the
analysis, the three points defined by 𝐼𝐷𝑆𝑆 , 𝑉𝑃 and the intersection just described will be
sufficient for plotting the curve.

In Fig., the fixed level of VGS has been superimposed as a vertical line atVGS = −VGG . At any
point on the vertical line, the level of VGS is−VGG -the level of ID must simply be determined
on this vertical line. The point where the two curves intersect is the common solution to the
configuration-commonly referred to as the quiescent or operating point. The subscript Q will
be applied to drain current and gate-to-source voltage to identify their levels at the Q-point.
Note in Fig. that the quiescent level of ID is determined by drawing a horizontal line from the
Q-point to the vertical ID axis as shown in Fig.
Self bias Configuration

 This is the most common method of biasing a JFET.

 This circuit eliminates the requirement of two dc supplies i.e. only drain
supply is used and no gate supply is connected.
 In this circuit, a resistor𝑅𝑆 , known as bias resistor, is connected in the source
lag.
The dc component of drain current 𝐼𝐷 flowing through 𝑅𝑆 makes a voltage
drop across𝑅𝑆 . The voltage drop across 𝑅𝑆 reduces the gate-to-source reverse
voltage required for JFET operation. The resistor𝑅𝑆 , feedback resistor prevents
any variation in drain current.

 since no gate current flows through the reverse bias gate-source, the gate
current 𝐼𝐺 = 0 and therefore, 𝑉𝐺 = 𝐼𝐺 𝑅𝐺 = 0𝑉

 with the drain current 𝐼𝐷 the voltage at source

𝑉𝑆 = 𝐼𝐷 𝑅𝑆 = 0𝑉
And the gate-source voltage 𝑉𝐺𝑆 is
𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = −𝐼𝐷 𝑅𝑆

 So the voltage drop across the resistance𝑅𝑆 , provides the biasing voltage 𝑉𝐺𝑆
and no external source is required for biasing, and this is the reason that it is
called self biasing.
 The operating point (i.e. zero signal 𝐼𝐷 and 𝑉𝐷𝑆 ) can easily be determined by
the equations

𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
𝑉𝑃

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 (𝑅𝐷 + 𝑅𝑆 )

Graphical Analysis

The graphical approach requires that we first establish the device transfer characteristics as
shown in Fig. Since Eq. 𝑉𝐺𝑆 = −𝐼𝐷 𝑅𝑆 defines a straight line on the same graph, let us now
identify two points on the graph that are on the line and simply draw a straight line between
the two points. The most obvious condition to apply is 𝐼𝐷 = 0𝐴 since it results in 𝑉𝐺𝑆 =
−𝐼𝐷 𝑅𝑆 = 0𝑉 . For Eq., therefore, one point on the straight line is defined by𝐼𝐷 =
0𝐴𝑎𝑛𝑑 𝑉𝐺𝑆 = 0𝑉, as appearing on Fig.

The second point for Eq. requires that a level of 𝑉𝐺𝑆 𝑜𝑟 𝐼𝐷 be chosen and the corresponding
level of the other quantity be determined using Eq. The resulting levels of 𝑉𝐺𝑆 𝑎𝑛𝑑 𝐼𝐷 will
then define another point on the straight line and permit an actual drawing of the straight
line. Suppose, for example, that we choose a level of 𝐼𝐷 equal to one-half the saturation
level. That is,

𝐼𝐷𝑆𝑆
𝐼𝐷 =
2

𝐼𝐷𝑆𝑆
𝑉𝐺𝑆 = −𝐼𝐷 𝑅𝑆 = − 𝑅
2 𝑆

The result is a second point for the straight-line plot as shown in Fig. The straight line as
defined by Eq. is then drawn and the quiescent point obtained at the intersection of the
straight-line plot and the device characteristic curve. The quiescent values of 𝑉𝐺𝑆 𝑎𝑛𝑑 𝐼𝐷 can
then be determined and used to find the other quantities of interest.
Voltage-divider bias Configuration

 The resistor 𝑅1 and 𝑅2 form a potential divider across the drain supply𝑉𝐷𝐷 .

 The voltage 𝑉2 across 𝑅2 provides necessary bias. The additional gate resistor
𝑅1 form gate to supply voltage facilitates in larger adjustment of the dc bias
point and permits use of large valued𝑅𝑆 .
  The gate is reverse biased so that 𝐼𝐺 = 0 and the gate voltage

VDD
V2 = VG = R
R1 + R 2 2

And

𝑉𝐺𝑆 = 𝑉𝐺 − 𝐼𝐷 𝑅𝑆

 The circuit is so designed so that 𝐼𝐷 𝑅𝑆 is larger than VG so that 𝑉𝐺𝑆 is negative.

This provides correct bias voltage.

 The operating point can be determined as

𝑉2 − 𝑉𝐺𝑆
𝐼𝐷 =
𝑅𝑆

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 (𝑅𝐷 + 𝑅𝑆 )

 Maximum gain is achieved by making resistance 𝑅𝐷 as large as possible and

for a given level of 𝐼𝐷 it needs maximum voltage drop across resistor𝑅𝐷 .
However, greater bias stability is achieved by making 𝑅𝑆 as large as possible.

Graphical Analysis

𝑉𝐺𝑆 = 𝑉𝐺 − 𝐼𝐷 𝑅𝑆

Since any straight line requires two points to be defined, let us first use the fact that
anywhere on the horizontal axis of Fig. the current 𝐼𝐷 = 0 . If we therefore select 𝐼𝐷 to be 0
mA, we are in essence stating that we are somewhere on the horizontal axis. The exact
location can be determined simply by substituting 𝐼𝐷 = 0𝑚𝐴 into Eq. and finding the
resulting value of 𝑉𝐺𝑆 as follows:

𝑉𝐺𝑆 = 𝑉𝐺

The result specifies that whenever we plot Eq., if we choose𝐼𝐷 = 0𝑚𝐴, the value of for the
plot 𝑉𝐺𝑆 will be 𝑉𝐺 volts. The point just determined appears in Fig.
For the other point, let us now employ the fact that at any point on the vertical axis 𝑉𝐺𝑆 =
0𝑉and solve for the resulting value of𝐼𝐷 :

𝑉𝐺
𝐼𝐷 =
𝑅𝑆

The intersection of the straight line with the transfer curve in the region to the left of the
vertical axis will define the operating point and the corresponding levels of𝐼𝐷 𝑎𝑛𝑑𝑉𝐺𝑆 .

Biasing of MOSFETs

Feedback Biasing Arrangement

 A popular biasing arrangement for enhancement-type MOSFETs is provided

in Figure.

 The resistor 𝑅𝐺 brings a suitably large voltage to the gate to drive the MOSFET
“on.”
 Since 𝐼𝐺 = 0𝑚𝐴 and𝑉𝑅𝐺 = 0𝑉, the dc equivalent network appears as shown in
Fig.

 A direct connection now exists between drain and gate, resulting in

𝑉𝐷 = 𝑉𝐺

𝑉𝐷𝑆 = 𝑉𝐺𝑆

 For the output circuit,

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷

which becomes

𝑉𝐺𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷

 Since the Eq. is that of a straight line, the procedure employed to determine
the two points that will define the plot on the graph is as follows:
Substituting 𝐼𝐷 = 0𝑚𝐴 into Eq. gives

𝑉𝐺𝑆 = 𝑉𝐷𝐷 |𝐼𝐷 = 0𝑚𝐴

Substituting 𝑉𝐺𝑆 = 0𝑉 into Eq.

𝑉𝐷𝐷
𝐼𝐷 = | 𝑉 = 0𝑉
𝑅𝐷 𝐺𝑆
 The plots defined by the above Eqs. appear in Fig. with the resulting operating
point.