UNIVERSITY OF LAGOS d The presence of powerful processor to

DEPARTMENT OF COMPUTER SCIENCES manipulate data

POSTGRADUATE EXAMINATIONS e All of the above
FIRST SEMESTER 2013/2014 8 One statement is true about a computer hard disk
a It resides in the computer casing
MIT 805 - COMPUTER SYSTEMS & b It is made up of magnetic platter sealed in a
ORGANIZATION metal case
c It stores more than a diskette
MATRIC NUMBER __________________________ d It is a bit expensive than the blue ray
Time Allowed: 2 Hour e All of the above
Instructions: 9 All kinds of input, output and external storage
devices are called
a Moore’s law B Peripheral
1 Answer all questions in section A by shading the correct
c Stored-program d Coordinator
answers on the OMR sheet provided.
concept
e None of the above
2 Use the provided booklet to answer two questions in
10 The nerve centre where peripherals are connected
section B,
for operation is the ______
3 Submit your OMR sheet, the Question paper and the
a Controller B DMA
booklet after the examination.
c CPU D Memory
SECTION A TIME ALLOWED: 40
e All of the above
MINUTES
11 The speed of the microprocessor depends on____
Questions
A Size of hard disk
B Data path
1 With advancement in computer technology __ and C Size of main memory
___ features of computer system are rapidly D All of the above
increasing E None of the above
a Capabity and capacity 12 Computers may be classified by size. Which of the
b Memory and processing speed following arrangements is correct?
c Size miniaturilization and computer family A Mini, Digital, Mainframe
d All of the above B Mainframe, Minicomputer, Microcomputer
e None of the above D Digital, Laptop, Mini
2 Each decade in computer technology brings these E None of the above
except 13 A modern day computer is not expected to have____
a New b New c New a Multimedia features
applications devices services b Artificial Intelligence
d Eradicating e Coexistence of old and new c Pentium processor
old devices computer system d Parallel processing
3 ___is considered as the mind of the computer e Pentium II processor
system 14 In order to execute I-O related instruction, the
A Processor b Memory processor issues one of the following commands to
C Software d Hardware the I-O module
E None of the above a An address specifying the particular I-O module
4 ____ is the body of the computer system b The external device concerned
a processor b Memory c The I-O command or operation
c software d Hardware d All of the above
e All of the above e None of the above
5 _______is a vital component of any system 15 A number given to uniquely identify an I-O device
a output B Control is called
c feedback D Input a Address b Interrupt
e All of the above number number
6 For a music concert, ______serves as the processor d Status e Dual Core
A keyboard B Microphone number
C amplifier D Speaker 16 An I-O module that takes detailed processing burden
E Tape deck from the main processor is the ___
7 This computer capability is made available through a I-O channel
the stored program concept ________ b I-O processor
A the volatility of the main memory c DMA
B The volatility of the processor register d All of the above
c The use of the flash disk to hold data e None of the above
17 The device management technique that allows the e All of the above
processor to have direct control of the I-O 26 Instruction pipelining was introduced through
operations is the ___ a 8088 processor b 80286 processor
a Programmed I-O c 80386 processor d 80486 processor
b Direct Memory Device e Itanium processor
c Interrupt-drivenI-O 27 An instruction cycle involves one of the following
d Processor driven I-O activities______
e All of the above a Calculating the address of memory that has the
18 This class of software controls the computer system instruction
itself b Copying the instruction to the RAM
a McAffee B Operating System c Determining the op-code
c Firewall D Translator d Fetching the operands to be used
e All of the above e All of the above
19 One is true about communication devices a The first device gains higher throughput than the
a Combinations of input/ output devices are used second
b They convert discrete signals to continuous b The devices signals will overlap and become
signal gambled
c They only deal with analog signal transmission c They both will use the content to achieve desired
d They connect remote devices goal
e All of the above d The signal will be discarded
20 One statement is true e All of the above
a Data can be stored on a short term only 29 One of the following signals is a command signal __
b Data can be stored on a long term only a Memory B Bus grant c Reset
c Data can be stored on both short- term and long- write
term d Transfer E All of the above
d Data viewed on a VDU are long-term stored Ack
e All of the above 30 This device is not suitable for communicating with
21 _____orchestrates the performance of functional electronic equipment
parts of a computer system a Keyboard B Actuator C Disk-drive
a Arithmetic and b Control unit d Controller E USB keys
logic unit 31 An instruction cycle passes through these states except
c Semi-conductor d Keyboard a Determining the instruction address
memory b Reading the instruction from an address
e All of the above c Determining the type of desired operation
22 ___ provides some mechanisms for communication d Reading the value of operand if any
among the CPU, main memory and I/O devices e None of the above
a System bus b DMA 32 One of these operations occur when the processor
c System adapter d Mother board communicate with I-O devices
e All of the above d Address E All of the above
recognition
23 This is the world’s first general-purpose 33 One of the following statements is not correct about
microprocessor the width of the data bus __
a 80286 b IBM 370 a Determines the maximum addressable memory
c 8080 d 8088 cells
e 80486 b Determines the maximum transferrable bits at a
24 An I/O buffer register does what? time
a Exchanges data between the input device and c Determines the overall performance of the system
output device d Indicates the maximum number of visits to
b Specifies a particular I/O devices memory for instruction fetching
c Specifies the address of input devices and output e None of the above.
devices 34 A reason for multiple bus in modern systems is that
d Exchanges data between the I/O devices and the a The system bus may not function effectively
CPU b Peripheral devices may not function effectively
e All of the above c It acts as a bridge between the speed of the
25 One is an operation that can be performed by the processor and I-O devices
control unit d It counteract the mezzanine architecture
a Data transfer b Unconditional e All of the above
branching 35 In order to avoid losing of burst of data from memory
c Arithmetic d Address alteration to devices, there is a device storage called ____

2
 a Mass b Main c buffer d. Synchronous timing is easier to implement than
memory memory asynchronous
d cache e Register e. None of the above
36 One is not a function of an I-O module ___ 46 The delay experience by when a device is busy with a
A Report communication errors to the processor bottled-necked bus is called __
B Spool data into its memory a. Propagation delay
C Liaise between the processor and the I-O devices b. Queuing delay
D Performing arithmetic instruction c. Latency rate
E All of the above d. Service delay
e. None of the above
37 Commands from the processor to the I-O module are 47 Embedded processors are used in
issued through ___ a. Sensors b. Scanners
a DMA B Control c System bus c. Ignition system d. Personal digital
unit assistance
d I-O e PSW e. All of the above
devices 48 The first minicomputer vendor is attributed to
38 ______bus provides the path for moving data between a. IBM Computers
system modules b. DEC computers
A Address bus B Control bus c. INTEL computer
C System bus D Data bus d. All of the above
E All of the above e. None of the above
39 ______determines the maximum possible memory 49 ARM architecture uses ____ processor technology
locations of a computer system a. RISC
A Address bus B Control bus b. CISC
C System bus D c. Logic gate
E All of the above d. All of the above
40 The I/O READ and I/O WRITE are examples of e. None of the above
signals that can be sent through 50 The Operating system is an indispensable computer
a Address bus B Data bus resource in that ___
c Control bus D System bus a. It manages the application software
e All of the above b. It easily accommodates new technology
41 One is a human readable category of I/O devices c. It shields of usage complexities from the common
a USB keys B Sensors users
c VDU d Modern d. It recovers the running processes from deadlocks
e All of the above e. All of the above
42 External devices are connected to the CPU except 51 Across the spectrum of memory hierarchy, one of
through ______ the following relationships holds
a Serial ports b Parallel ports a. Faster access time, greater cost per bit
c Mother board d USB ports b. Greater capacity, smaller cost per bit
e Mouse c. Greater capacity , slow access time
43 A drawback of programmed I-O and Interrupt-driven d. The higher the volatility, the less the dependability
I-O is that __ e. All of the above
a. The data transfer rate is limited by the speed with 52 The processor passes the following information to the
which the processor can test and service a device DMA to read a block of data except ___
b. The processor is tied up in managing an I-O transfer a A read control signal
c. A number of instructions must be executed for each I- b The address of the I-O device that is involved
O transfer c The starting location in memory to be read from
d. All of the above d The number of words to be read
e. None of the above e None of the above
44 _____ lies in the heart of computing 53 A truth statement about the DMA I-O technique is that
a. Processor b. computer _____
c. Memory d. data a The processor is involved only at the beginning of
e. All of the above data transfer
45 One of the following statements is false __ b The processor is involved at the end of data
a. A synchronous timing is triggered by a clock transfer
b. An asynchronous timing is triggered by a clock c The processor is involved at the beginning and end
c. Event in asynchronous depends on the occurrence of a of data transfer
previous events d The processor is not involved during data transfer
at all
3
 e All of the above 63 The processor increments ___ register after execution
54 The DMA technology was interfaced to ___ family of of an instruction
Intel processor a PC b IR
a 8086 b 8088 c MAR d PSW
c 80186 d 8087 e MBR
e All the of the above 64 The low level instruction ADD B, A does what?
55 One of these statements is false _____ a Stores the sum of memory locations A and B in
a The use that a device is put influences the policies accumulator
in the operating system b Stores the sum of memory locations A and B in B
b The data transfer rate of peripherals is much c Stores the sum of memory locations A and B in A
slower to that of main memory d Add letter A and letter B into letter B
c The device controller bridges the speed mismatch e All of the above
between processor and devices 65 A bus that connect major computer components is
d The word-length of devices are the same with the callled
computer system’ s word-length a Address bus b Data bus
e None of the above c Control bus d System bus
56 ____ interprets the instructions in memory and cause e All of the above
them to be executed in IAS computer system 66 The IBM processor supports 500MHz clock speed
a ALU b Accumulat c Control Unit a Power PC G4 b Power PC G5
or c Power PC G3 d Power PC 740/750
d Memory e ROM e All of the above
57 ENIAC is a(an) ____ computer system 67 This translator takes from high level language to
a Digital b Analog machine language
c Mini d Micro a C# b C++
e Hybrid c Visual BASIC d Phyton
58 The stored-program concept was first implemented in e Java
___ 68 This describes the architecture of a computer system
a ENIAC b EDVAC except
c IAS d IBM a Instruction format b I/O Module
e All of the above c Instruction level d Instruction set
59 During multiplication arithmetic in IAS computer, the e Data representation
most significant bits are stored in ____ register 69 The booting programs reside in
a Multiplier quotient b Accumulator a ROM b RAM
c Program counter d Program Status Word c Hard disk d EPROM
e Instruction Pointer e All of the above
60 During the fetch operation, the Op-code of the 70 The operating system is responsible for
instruction is loaded in ____ register a Resource b Evolutionary support
a Instruction Register management
b Program Counter c Mediating between d Mediating between
c Accumulator users and hardware application programs
d Memory Address Register and hardware
e Memory buffer Register e All of the above
61 A difference between a formal and an informal
language is that SECTION B
a Number of possible operations that can be Time Allowed: 1 Hour 20 Minutes
expressed are few in formal language 1a. The basic function of a computer system is
b Number of possible operations that can be execution of instructions in a program. Discuss the
expressed are infinite in formal language key components involved in program execution
c Number of possible operations that can be b. What is the benefits of using a multi-bus
expressed are few in an informal language architecture compared to single-bus architecture?
d In formal, statements structures are infinite
c. Give five parameters that can be used to
e None of the above
62 A repeated procedure for extracting data or instruction assess computer memories.(5 marks)
from the memory is called ____ 2a. Is there any differences among sequential
a Fetch cycle b Execute c Decode cycle access, direct access and random memory
cycle access?
d Instruction e Processor cycle b. Is there any relationship among access time,
cycle
memory cost and memory capacity?

4
c. how can a memory be assessed?
3a. describe the techniques of managing I/O
devices
b. When a device interrupt occurs, how does
the processor determine which device issued
the interrupt?
c. What are the major functions of the I/O
module?