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Embedded Systems Architecture, Device Drivers - Part 1:

Interrupt Handling
Tammy Noergaard ­March 05, 2013

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Interrupt acknowledgment (IACK) is typically handled by the master processor when an external
device triggers an interrupt. Because IACK cycles are a function of the local bus, the IACK
function of the master CPU depends on interrupt policies of system buses, as well as the interrupt
policies of components within the system that trigger the interrupts. With respect to the external
device triggering an interrupt, the interrupt scheme depends on whether that device can provide
an interrupt vector (a place in memory that holds the address of an interrupt’s ISR (Interrupt
Service Routine), the software that the master CPU executes after the triggering of an interrupt).
For devices that cannot provide an interrupt vector, referred to as non­vectored interrupts, master
processors implement an auto­vectored interrupt scheme in which one ISR is shared by the non­
vectored interrupts; determining which specific interrupt to handle, interrupt acknowledgment, etc.,
are all handled by the ISR software.

Figure 8­7a. Motorola/Freescale MPC860 Interrupt Controllers.[4] © Freescale

Semiconductor, Inc. Used by permission.

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6/28/2017 Embedded Systems Architecture, Device Drivers - Part 1: Interrupt Handling | EDN
Click for larger image

Figure 8­7b. Mitsubishi M37267M8 Circuitry.[5]

An interrupt­vectored scheme is implemented to support peripherals that can provide an interrupt

vector over a bus and where acknowledgment is automatic. An IACK­related register on the
master CPU informs the device requesting the interrupt to stop requesting interrupt service, and
provides what the master processor needs to process the correct interrupt (such as the interrupt
number and vector number). Based upon the activation of an external interrupt pin, an interrupt
controller’s interrupt select register, a device’s interrupt select register, or some combination of the
above, the master processor can determine which ISR to execute. After the ISR completes, the
master processor resets the interrupt status by adjusting the bits in the processor’s status register
or an interrupt mask in the external interrupt controller. The interrupt request and acknowledgment
mechanisms are determined by the device requesting the interrupt (since it determines which
interrupt service to trigger), the master processor, and the system bus protocols.
Keep in mind that this is a general introduction to interrupt handling, covering some of the key
features found in a variety of schemes. The overall interrupt­handling scheme can vary widely
from architecture to architecture. For example, PowerPC architectures implement an auto­
vectored scheme, with no interrupt vector base register. The 68000 architecture supports both
auto­vectored and interrupt­vectored schemes, whereas MIPS32 architectures have no IACK
cycle and so the interrupt handler handles the triggered interrupts.
8.1.1 Interrupt Priorities
Because there are potentially multiple components on an embedded board that may need to
request interrupts, the scheme that manages all of the different types of interrupts is priority­
based. This means that all available interrupts within a processor have an associated interrupt
level, which is the priority of that interrupt within the system. Typically, interrupts starting at level
“1” are the highest priority within the system and incrementally from there (2, 3, 4, etc.) the
priorities of the associated interrupts decrease. Interrupts with higher levels have precedence over
any instruction stream being executed by the master processor, meaning that not only do
interrupts have precedence over the main program, but higher priority interrupts have priority over
interrupts with lower priorities as well. When an interrupt is triggered, lower priority interrupts are
typically masked, meaning they are not allowed to trigger when the system is handling a higher­
priority interrupt. The interrupt with the highest priority is usually called an NMI.

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