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 2.10.3 Accurate Modeling of DC Response
2.10.4 Frequency Response and Step Response
2.10.5 Loop Gain, Differential Gain, and Noise
2.11 Discrete-Time Amplifiers
2.11.1 DC Analysis with Charge Conservation
2.11.2 Unified Closed-Loop Model
2.11.3 Accurate Modeling of DC Response
2.11.4 Transient Response
2.11.5 Loop-Gain Extraction
2.12 Fully-Differential Discrete-Time Amplifiers
2.12.1 DC Analysis with Charge Conservation
2.12.2 Unified Closed-Loop Model
2.12.3 Accurate Modeling of DC Response
2.12.4 Transient Analysis and Loop-Gain Extraction
2.13 References
2.14 Exercises

3 Device Layer
3.1 Introduction
3.2 MOSFET Basics
3.2.1 Structure and Electrical Ports
3.2.2 Performance Metrics and Design Variables
3.3 NMOS Design Relations and Tools
3.3.1 Long-Channel Models
3.3.2 Threshold Voltage
3.3.3 Drain-Source Saturation Voltage
3.3.4 Sheet Current
3.3.5 Transconductance Efficiency
3.3.6 Output Resistance and Early Voltage
3.4 PMOS Design Relations and Tools
3.4.1 Strong-Inversion Model
3.4.2 Subthreshold Model
3.4.3 Threshold Voltage
3.4.4 Drain-Source Saturation Voltage, Sheet Current, and
Transconductance Efficiency
3.4.5 Output Resistance and Early Voltage
3.5 Thermal Effects
3.6 Biasing and Sizing a MOSFET with Design Tools
3.7 Small-Signal Modeling and Circuit Analysis
3.7.1 MOSFET DC Small-Signal Model

8
 3.7.2 DC Small-Signal Circuit Analysis
3.7.3 MOSFET Capacitances and High-Frequency Small-Signal
Model
3.8 MOSFET Noise Model
3.9 MOSFET as a Switch
3.9.1 Single-Device and Transmission-Gate Switch Properties
3.9.2 Charge Injection and Clock Feedthrough
3.10 Resistor Design
3.10.1 Resistor Structures and Resistance Modeling
3.10.2 Design Techniques for Accuracy and Precision
3.10.3 MOSFET as a Resistor
3.11 Capacitor Design
3.11.1 MIM Capacitor
3.11.2 MOSFET as a Capacitor
3.12 References
3.13 Exercises

4 Circuit Layer
4.1 Introduction
4.2 Current Sources, Sinks, and Mirrors
4.2.1 Fundamental Concepts and Performance Metrics
4.2.2 Accuracy and Precision in Current Mirroring
4.2.3 Basic Cascoding
4.2.4 Low-Voltage Cascoding
4.2.5 Regulated Cascoding
4.2.6 Self-Cascoding
4.3 Current and Voltage References
4.3.1 Voltage-Divider Current Reference
4.3.2 Beta-Multiplier Current Reference
4.3.3 Bandgap Voltage Reference
4.4 Basic Amplifier Stages
4.4.1 Common-Source Stage
4.4.2 Source Follower
4.4.3 Basic Differential Pair
4.4.4 Source-Degenerated Differential Pair
4.4.5 Super-GM Differential Pair
4.5 Basic OTA
4.5.1 DC Transfer Characteristic as a Voltage Amplifier
4.5.2 Range Limitations
4.5.3 DC Differential Gain and Offset

9
 4.5.4 Frequency Response and Step Response
4.5.5 Noise-Related Properties
4.6 Symmetrical OTA
4.6.1 Topology and DC Transfer Characteristic
4.6.2 Range Limitations
4.6.3 DC Differential Gain and Offset
4.6.4 Frequency Response and Step Response
4.6.5 Noise-Related Properties
4.6.6 Cascoded-Symmetrical OTA
4.7 Folded-Cascode OTA
4.7.1 Topology and DC Transfer Characteristic
4.7.2 DC Differential Gain and Range Limitations
4.7.3 Frequency Response, Step Response, and Noise-Related
Properties
4.7.4 Rail-to-Rail Folded-Cascode OTA
4.8 Miller OTA
4.8.1 Topology and DC Response
4.8.2 Frequency Response and Noise-Related Properties
4.8.3 Step Response
4.9 Opamp with a Push-Pull Source-Follower Output Stage
4.9.1 Topologies and Operation
4.9.2 DC Response
4.9.3 Frequency Response, Step Response, and Noise
4.10 Opamp with a Push-Pull Common-Source Output Stage
4.11 Fully-Differential OTAs and Opamps
4.11.1 Core Topologies and Properties
4.11.2 Common-Mode Feedback Circuits
4.11.3 Design Examples
4.12 References
4.13 Exercises

Index

10
 CHAPTER 1
Preliminaries

T his book is about linear analog integrated circuits. An analog circuit

is qualified as linear if it exhibits a linear relationship between its
input and output variables. Regulators, amplifiers, buffers, and filters are
typical examples of such circuits. They are used mostly for regulating
power supplies, conditioning sensor signals prior to analog-to-digital
conversion, or driving an actuator/transducer after digital-to-analog
conversion. The last two cases are exemplified in Fig. 1.1 with two simple
applications. Figure 1.1(a) shows a voltage amplifier matching up the
voltage-mode signal of a temperature-sensing diode to the input range of
an analog-to-digital converter (ADC). Figure 1.1(b) shows a
transimpedance amplifier converting and filtering the currentmode output
signal of a digital-to-analog converter (DAC) into a voltage-mode signal to
drive an actuator/transducer load. Both examples exhibit a feature common
to almost all linear integrated-circuit applications: Their architecture is in
the form of a closed-loop configuration consisting of (a) an operational
amplifier (opamp), and (b) an external network built usually with passive
components. In a closed-loop configuration, the opamp itself acts as an
inaccurate, imprecise, and nonlinear supplier of large voltage gain while
the negative feedback provided by the external network trades off the
excessive voltage gain for accuracy, precision, and linearity, which are the
three fundamental attributes of linear analog signal processing.

11
FIGURE 1.1 Two linear integrated-circuit application examples. (a) A
single-ended voltage amplifier for conditioning a thermal-sensor signal
prior to analog-to-digital conversion. (b) A fully-differential
transimpedance amplifier for driving an actuator.

Integrated-circuit design in general is a two-stage process. The first

stage, called electrical design, delivers a complete circuit schematic of the
closed-loop configuration annotated with the dimensions and other
physical parameters of (a) all external-network components and (b) all
opamp internal devices. The second stage, called physical design, converts
this schematic into an artwork defining the layout to be fabricated. This
book is primarily on electrical design; physical design is covered as much
as it pertains to electrical design.
Electrical design is a top-down process going through three layers of
abstraction as illustrated with a block diagram in Fig. 1.2. Electrical
performance of the application, as specified in terms of what we call
closed-loop metrics, is the input of the topmost application layer. In this
layer, design activity begins with the selection of a closed-loop
configuration that can handle the application, and moves to the translation
of the specified closed-loop metrics into (a) open-loop metrics, which
define the target performance of the opamp itself, and (b) external-network
device metrics, which define the target performance of external-network
components. The intermediate circuit layer of design is based on open-
loop metrics. Its outcome is twofold: (a) adopting an opamp circuit
topology that can satisfy these open-loop metrics, and (b) specifying the

12
target performance of opamp internal devices in terms of device metrics.
In the final device layer of design, the device metrics specified in
application and circuit layers are translated into bias conditions and
physical parameters for all opamp devices and external-network
components. Although the block diagram shown in Fig. 1.2 indicates a
one-way flow, it frequently becomes necessary to loop back and redesign
as overconstrained or underconstrained design spaces are encountered
along the way. However, this does not alter the definitions indicated in
Fig. 1.2 for the input metrics or outcomes of any of the three layers.

13
14
FIGURE 1.2 Layers of abstraction in electrical design.

The main body of this book is divided into three chapters, each dealing
with one of the three layers of design. The application layer is covered in
Chapter 2. The device layer comes next in Chapter 3. Finally, in Chapter 4,
we study the circuit layer and also work on complete linear integrated-
circuit design examples involving the contents of the preceding chapters.
The methodology practiced in this book for design and verification is
based on Spice simulations, which are run on version-27 of the open-
source platform Ngspice. The reader is referred to the companion website
of this book, www.mhprofessional.com/AICDS, for instructions regarding
its download and installation.
Circuit description in Ngspice is based on direct netlist entry whereas
commercial simulation platforms generate netlists from schematic entries.
Schematic entry is generally faster, easier, and foolproof, which are
valuable assets in professional use because they minimize the time and
attention needed for circuit description. However, the intricacies of circuit
description are better learned by paying attention to details, which is why
netlist entry is preferred in this book. Input files describing the netlists of
all simulation examples can be downloaded from this book’s website.
Each of the folders named chap2, chap3, and chap4 contains the files used
in one particular chapter. The first step of running a simulation with any of
these files is to open the Ngspice executable. Next, the folder containing
the input file is defined as the current directory if it is not already so. For a
file residing in, for example, c:\spice\chap3 of an MS Windows
installation, this is done by entering

at the prompt as shown at the top of Fig. 1.3. Next, the filename itself is
entered as exemplified in the middle part of Fig. 1.3 for an input file ex3-
16.sp. Finally, entering the command run as shown at the bottom of Fig.
1.3 initiates the simulation. As the reader will experience initially in
Example 2.9 of Subsection 2.4.2, it is possible to start a simulation without
entering a run command provided that the input file is properly scripted.
As to reading out or plotting the outcomes of a simulation, the reader will
find the necessary descriptions inside the examples presented throughout
the following three chapters.

15
FIGURE 1.3 Screenshots showing the steps of running an input file in an
MS Windows installation. Top: Changing the directory. Middle: Declaring

16
the filename. Bottom: Initiating the simulation.

Input files are prepared with a text editor, and saved with extension .sp.
Each begins with a title line and ends with a .end line. The lines in
between are expected to describe at least the network of components, their
parameters, and the type of analysis to be performed. For an example, the
reader is referred to file ex2-1.sp, which netlists the circuit schematic
shown in Fig. 2.5. Its line-by-line description is as follows:
Line 1 Filename is typed in the title line. Since Spice does not consider this
line as a declaration, any text can be included without affecting the outcome of
the simulation.

Line 2 This line quantifies certain parameters. Typographically, it spans over

two lines as indicated by the plus sign appearing at the beginning of the
extension. This is how a long line can be accommodated in an input file.
Line 3 Another file opmacrol.sp is called by this line. This additional file
actually describes the netlist of the opamp x1 declared in line 4 as a subcircuit.
If a circuit is involved in multiple simulations, or multiple instances of a circuit
are involved in a simulation, we prefer to describe such a circuit as a subcircuit
and simply include its instances whenever or wherever needed.

Line 4 This is an element line where an instance of the subcircuit opamp is

called. Note that a subcircuit instance is identified with a name beginning with
x. The three numbers appearing after the name are the node numbers of the top-
level circuit in which the subcircuit is embedded.
Lines 5 and 6 These lines begin with r, and therefore describe the instances of
resistors. Each contains two node identifiers and the value of the resistance.
Lines 7 and 8 Independent voltage sources are defined in these lines. They
begin with v, and continue with two node identifiers. The first between the two
is the reference node. The third number 0.54 appearing in line 7 is the voltage
imposed onto the reference node with respect to the ground node. Note that 0 is
the universal identifier of ground node. The voltage of the source vd is
undefined in line 8 because it is changed as a part of the analysis defined next in
line 9.

Line 9 Beginning with a dot, this line describes a command. Specifically, it

defines a dc simulation as indicated by .dc. The voltage of the independent
source vd is the variable of this simulation. It varies between 0.476 and 0.723 V
in 1-mV increments.
The end of the input file is declared in the very last line.

17
 Although the examples included in the following chapters will help the
reader master the basics of simulation with Ngspice, it will be much more
beneficial at this stage to read the specific sections of the user manual,
which is included in the downloaded Ngspice package.

18
 CHAPTER 2
Application Layer

2.1 Introduction
As stated in Chapter 1, the application layer of electrical design involves
(a) selection of an appropriate closed-loop configuration for the
application, and (b) translation of the specified closed-loop metrics into
open-loop metrics for the opamp and device metrics for the external
network. Available closed-loop amplifier configurations are well
documented in related literature. No attempt is made in this book to
present their inventory but most popular configurations are presented in
examples throughout this chapter. The main emphasis of the chapter is on
the analytical techniques and tools used in translating closed-loop metrics
into open-loop metrics and external-network device metrics. These
techniques and tools are generalized into four major architectural classes
depending on (a) whether amplification is performed in continuous time or
in discrete time, and (b) whether signal representation is single ended or
fully differential. The case of continuous-time/single-ended amplifier
configurations, being the most fundamental of the four, is covered in the
first nine sections of this chapter. Based on the foundation thus
established, coverage is then extended to continuous-time/fully-differential
configurations in Section 2.10, to discrete-time/single-ended
configurations in Section 2.11, and finally to discrete-time/fully-
differential configurations in Section 2.12.
Most of the concepts presented in this chapter are supported with Spice
simulations conducted with a parameterized single-ended or fully-
differential opamp macromodel defined as a subcircuit. The single-ended

19
version is netlisted in the input file opmacrol.sp. As shown in Fig. 2.1(a),
this macro interfaces with the closed-loop configuration through the
following three pins:

FIGURE 2.1 Symbols and pin configurations of the opamp macromodels

defined as subcircuits. (a) Single-ended opmacrol.sp. (b) Fully-
differential opmacro2.sp.

1. ninv: Noninverting input.

2. inv: Inverting input.
3. out: Output.

The user-defined parameters of the single-ended opamp macro are

described in the following list for future reference.

• vdd: Positive power-supply voltage. Introduced in Subsection

2.2.1.
• vss:Negative power-supply voltage (zero for a single-supply
opamp). Introduced in Subsection 2.2.1.
• voh: Higher limit VOH of output range. Introduced in Subsection
2.2.1.
• vol: Lower limit VOL of output range. Introduced in Subsection
2.2.1.
• a0: DC differential gain A0 at the midpoint of the output range.
Introduced in Subsection 2.4.1.
• fgbw: Gain-bandwidth product fGBW. Introduced in Subsection
2.5.1.
• vdir: Differential-input range VDIR. Introduced in Subsection
2.5.2.

20
 • fnd: Nondominant pole frequency fnd. Introduced in Section 2.7.
• vos at vout: Offset voltage Vos defined at an output bias voltage
VO. Introduced in Subsection 2.4.1. Unlike the preceding
parameters, these two are set by default to vos= 0 and vout=
(voh+vol)/2 but can be reset by adding the following lines to the
main input file that contains the opamp subcircuit opmacrol.sp:

where <subcircuit identifier> is the name of the opamp

instance, such as x1, and <value> is the reset value.
The input file netlisting the fully-differential opamp macro is
opmacro2.sp. As shown in Fig. 2.1(b), this macro interfaces with the
closed-loop configuration through the following five pins:

1. ninv: Noninverting input.

2. inv: Inverting input.
3. outp: Noninverting output. Described in Subsection 2.10.1.
4. outn: Inverting output. Described in Subsection 2.10.1.
5. ocm:
This is the pin where the output common-mode voltage
VOCM is externally applied as described in Subsection 2.10.1.

The user-defined parameters of the single-ended opamp macro described

previously apply also to this opamp with one exception. The exception is
the replacement of the single- ended open-loop dc gain parameter a0 with
the differential open-loop dc gain parameter adif0 which is defined in
Subsection 2.10.3.
Another adjustable opamp parameter is the offset voltage vos, whose
default value is zero. The user may alter it by adding the following line to
the main input file containing the opamp subcircuit opmacro2.sp:

21
where <subcircuit identifier> is the name of the opamp instance, such
as x1, and <value> is the reset value. The offset voltage of a fully-
differential opamp is described in Subsection 2.10.3.

2.2 First-Order DC Response

DC response is of prime importance in design because most applications
operate with dc bias and are supposed to handle signals whose frequency
spectra include dc. Furthermore, a closed-loop configuration treats a time-
varying signal not much differently than a pure dc as long as its bandwidth
is wider than the frequency spectrum of the signal. The voltage amplifier
shown in Fig. 1.1(a) is a good example. It is biased with a dc voltage as
well as a dc current, and is driven by a signal of thermal origin which
usually remains constant for most of the time and varies slowly otherwise.
In this section, we present an analysis of closed-loop dc response using
an ideal opamp model based on the so-called virtual-short approximation.
Despite its ultimate simplicity, the model is still sufficiently accurate for
specifying the resistive components of the external network and open-loop
dc range metrics of the opamp. In some applications, the designer has to
consider also the second-order features of closed-loop dc response. Those
are discussed in Section 2.4 on the basis of a more accurate opamp model.

2.2.1 First-Order Open-Loop DC Transfer Characteristic

and Range Limitations
Shown in Fig. 2.2(a) is the symbol convention we generally use for opamp
terminal voltages regardless of the type of response being analyzed. vO is
the total instantaneous output voltage. vIN and vIP represent the total
instantaneous voltages of the inverting and noninverting input terminals,
respectively. In steady state, the opamp does not draw any dc current from
these input terminals because they are capacitively terminated inside the
opamp. All of these voltages are defined with respect to system ground.
The difference between the two input voltages, as defined by

is called differential-input voltage. The average of the two defined by

22
is called common-mode voltage.
In this book, the relationship imposed by the opamp between vO and
vID is generally called open-loop transfer function if expressed
analytically, or open-loop transfer characteristic if displayed graphically.
The dc form of the open-loop transfer characteristic is shown in Fig. 2.2(b)
for an ideal single-supply opamp powered by a positive supply-voltage
VDD with respect to system ground. The ideal features of the characteristic
are associated with its segment located between the two output-voltage
levels vO = VOL and vO = VOH. In a real opamp, this segment is nonlinear
with a large but finite and varying slope as will be discussed in detail in
Section 2.4. In first-order dc modeling, we assume it to be perfectly
vertical and located at

FIGURE 2.2 (a) Symbol convention for opamp input and output
variables. (b) Open-loop dc transfer characteristic and output range in an
ideal single-supply opamp. (c) A rail-to-rail common-mode range. (d) A

23
common-mode range excluding ground. (e) A common-mode range
excluding the supply voltage VDD.

When functioning properly, the negative feedback established by the

external network of the closed-loop configuration keeps the operation
point of the opamp on this ideally vertical segment. The range between
VOL and VOH is an open-loop metric called output range. It must be made
wide enough by design to safely accommodate the so-called output swing,
which is a closed-loop metric defined as the range in which vO is expected
to vary. This design constraint can be stated as

and

where VO(min) and VO(max) are the limits of the output swing.
According to (2.1) and (2.2), the common-mode voltage of an ideal
opamp complying with (2.3) is given by

which enables us to interpret the common-mode voltage as the common

value of the identical vIP and vIN. Ideally, an opamp is expected to be
insensitive to vCM, that is, vO should remain unchanged even when vIP and
vIN commonly change in time. In reality, all opamps are somewhat
sensitive to vCM, but the sensitivity is, to a first-order approximation,
negligible as long as vCM remains within a particular range known as
common-mode range (CMR). This range is an open-loop metric. It must be
made sufficiently wide by design to accommodate the minimum and
maximum values VCM(min) and VCM(max) of the common-mode voltage.
Representing the lower and upper limits of CMR with VIL and VIH, this
design constraint can be expressed with

24
and

The range VCM(min) ≤ vCM ≤ VCM(max) is called common-mode swing in

this book. It is a closed-loop metric.
Depending on the topology of the opamp, VIL may be lower or higher
than ground. Likewise, VIH may be lower or higher than VDD. If CMR
includes both ground and VDD, as shown in Fig. 2.2(c), the opamp is said
to have a rail-to-rail input. Yet, some other topologies offer a CMR
excluding ground or VDD, as depicted in Figs. 2.2(d) and (e), respectively.
In the past, amplifiers used to be built mostly with split-supply opamps
which are powered symmetrically by a positive supply VDD and a negative
supply VSS. The main benefit of split-supply powering is that it enables an
amplifier to handle bipolar signals1 without necessitating any bias. Over
the years, however, the diversification of signal-processing applications
has introduced many other forms of signals which can’t be processed
without bias anyway. More importantly, the cost of incorporating two
separate power supplies is prohibitively high for the rapidly expanding
application area of battery-operated portable equipment. These trends have
diminished the popularity of split-supply opamps. Still, it is worth
knowing that the only effect the split-supply scheme has on the first-order
open-loop dc transfer characteristic is to shift it down as shown in Fig.
2.3(a). Since the output range now includes vO = 0, the opamp can put out
a signal centered around the ground. As shown in Figs. 2.3(b) to (d), the
CMR also shifts down to include the ground, which is why a split-supply
opamp can also handle a common-mode signal swinging around ground.

25
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