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DEPARTMENT OF AVIONICS ENGINEERING

SUBJECT : FPGA BASED EMBEDDED SYSTEM

DESIGN
SUBJECT CODE : 408448
LAB NO : 03

TITLE : Testbench to Verify the Functionality of

a Design (Full Adder and Subtractor)

SUBMITTED TO : Engr. Lal Said Khan

SEMESTER : 6th

SECTION : B

Marks Obtain
Group Member 1 Group Member 2
NAME MAHNOOR
REGISTRATION NUMBER 220701002
LAB REPORT 2
PERFORMANCE
TOTAL MARKS

DEADLINE FOR SUBMISSION:

DATE OF SUBMISSION:

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Objectives:

• The primary goal of this lab is to design and implement a comprehensive

testbench for the functional verification of a Full adder circuit.
• Students will gain practical experience in creating a systematic test environment,
applying input stimuli, and analyzing output responses to ensure the correct
operation of the Full adder design.
• Enhance students' understanding of digital circuit verification methodologies and
their proficiency in using testbenches as a crucial tool in the FPGA design and
simulation process.

Testbench

A testbench is a simulation environment used in digital design to verify and validate the
functionality of a hardware description language (HDL) design, such as Verilog or
VHDL, before it is implemented on hardware. It serves as a virtual environment where
the behavior of the designed circuit can be tested under various conditions and scenarios.
The testbench generates input signals or stimuli to apply to the design under test (DUT).
These stimuli simulate different scenarios and test cases to ensure the DUT behaves as
expected. The testbench controls the simulation process, specifying when to start and
stop the simulation, as well as managing the timing and sequence of events. The actual
hardware design (DUT) is instantiated within the testbench. The testbench provides the
necessary inputs to the DUT and monitors its outputs. This involves comparing
simulated output waveforms with the expected behavior. This help identify and analyze
issues within the design. estbenches allow designers to identify and fix issues in the
design before it is implemented in hardware, reducing the risk of errors in the final
product.

Introduction

Full Adder is the adder that adds three inputs and produces two outputs. The first two
inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM. The C-
OUT is also known as the majority 1’s detector, whose output goes high when more than
one input is high. A full adder logic is designed in such a manner that can take eight
inputs together to create a byte-wide adder and cascade the carry bit from one adder to
another. we use a full adder because when a carry-in bit is available, another 1-bit adder

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must be used since a 1-bit half-adder does not take a carry-in bit. A 1-bit full adder adds
three operands and generates 2-bit results.

Figure 1: Schematic diagram of a Full Adderr

Full Adder Truth Table:

Algorithm 1:
This Verilog full adder module performs the binary addition of three input bits (A, B,
and CARRY_IN) and produces a SUM and a CARRY_OUT. The SUM is computed
using two XOR operations: SUM = (A ^ B) ^ CARRY_IN, which ensures correct
bitwise addition. The CARRY_OUT is determined using the formula (A & B) | (B &
CARRY_IN) | (A & CARRY_IN), which correctly accounts for all cases where a carry
is generated—when at least two of the three input bits are 1. The module is purely
combinational, using continuous assignments (assign) to perform logic operations
without requiring clock signals. The timescale 10ns / 100ps directive specifies the
simulation time unit and precision for accurate timing analysis.

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Verilog Testbench: The Verilog testbench (full_adder_tb) in Algorithm 2 verifies the

functionality of the full adder module by applying all eight possible input combinations
(A, B, CARRY_IN) and checking the outputs (SUM and CARRY_OUT). It defines the
inputs as reg and the outputs as wire, then instantiates the full adder module as uut.
Using an initial block, the testbench iterates through all input cases with a 10ns delay
(#10) between each change, while $display prints the results in a structured format for
easy verification. The test concludes with $finish, ensuring proper termination of the
simulation.

Algorithm 2: Verilog testbench for Full Adder

`timescale 10ns / 100ps

module full_adder_tb;

// Declare inputs as reg and outputs as wire

reg A, B, CARRY_IN;
wire SUM, CARRY_OUT;

// Instantiate the full adder module

full_adder uut (
.A(A),
.B(B),
.CARRY_IN(CARRY_IN),
.SUM(SUM),

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.CARRY_OUT(CARRY_OUT)
);

// Test procedure
initial begin
$display("A B CIN | SUM COUT");
$display("-----------------");

// Apply all possible input combinations

A = 0; B = 0; CARRY_IN = 0; #10;
$display("%b %b %b | %b %b", A, B, CARRY_IN, SUM, CARRY_OUT);

A = 0; B = 0; CARRY_IN = 1; #10;
$display("%b %b %b | %b %b", A, B, CARRY_IN, SUM, CARRY_OUT);

A = 0; B = 1; CARRY_IN = 0; #10;
$display("%b %b %b | %b %b", A, B, CARRY_IN, SUM, CARRY_OUT);

A = 0; B = 1; CARRY_IN = 1; #10;
$display("%b %b %b | %b %b", A, B, CARRY_IN, SUM, CARRY_OUT);

A = 1; B = 0; CARRY_IN = 0; #10;
$display("%b %b %b | %b %b", A, B, CARRY_IN, SUM, CARRY_OUT);

A = 1; B = 0; CARRY_IN = 1; #10;
$display("%b %b %b | %b %b", A, B, CARRY_IN, SUM, CARRY_OUT);

A = 1; B = 1; CARRY_IN = 0; #10;
$display("%b %b %b | %b %b", A, B, CARRY_IN, SUM, CARRY_OUT);

A = 1; B = 1; CARRY_IN = 1; #10;
$display("%b %b %b | %b %b", A, B, CARRY_IN, SUM, CARRY_OUT);

$finish; // Terminate simulation

end
endmodule
How to Add test bench:
1. Click on Add sources.

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2. Add or create simulation sources and then click on Next and then click on create
File.

3. Write the File Name (exact same name as in the test bech in Algorithm 2
(full_adder_tb)) and then click on ok and then click on Finish .

4. Click on ok

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5. Click on yes

6. Double click on full_adder_tb(full_adder_tb.v)

7. Write the code of test bench as from Algorithm 2 and click on Save.

8. Click on Run simulation and then Run Behavioral Simulation.

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Result:

As here the A=0 B=0 CARRY_IN=0 so the sum=A+B+Cin , sum = 0+0+0 ,sum=0

Here the A=0 B=0 CARRY_IN=1 ,Sum = 0+0+1 ,Sum=1, Carry_out=0

Here the A=1 B=0 CARRY_IN=0 ,sum= 1+0+0 ,Sum=1 ,CARRY_OUT=0

Here the A= 0 B=1 CARRY_IN=0 ,sum= 0+1+0 ,Sum=1 ,CARRY_OUT=0

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Here the A= 0 B=1 CARRY_IN=1 ,sum= 0+1+1 ,Sum=0 ,CARRY_OUT=1

Here the A= 1 B=0 CARRY_IN=0 ,sum= 1+0+0 ,Sum=1 ,CARRY_OUT=0 Verifying truth
table

Here the A= 1 B=0 CARRY_IN=1 ,sum= 1+0+1 ,Sum=0,CARRY_OUT=1. Verifying truth

table

Here the A= 1 B=1 CARRY_IN=0 ,sum= 1+1+0 ,Sum=0 ,CARRY_OUT=1 Verifying truth
table

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Here the A= 1 B=1 CARRY_IN=1 ,sum= 1+1+1 ,Sum=1 ,CARRY_OUT=1 Verifying truth
table

Conclusion:
The full adder testbench verifies the circuit’s functionality by applying all possible input
combinations with timescale 10ns / 100ps, ensuring accurate timing. Inputs (A, B,
CARRY_IN) are defined as reg for controlled assignment, while outputs (SUM,
CARRY_OUT) are wire, driven by combinational logic. The adder follows the expected
equations: SUM = (A ⊕ B) ⊕ CARRY_IN and CARRY_OUT = (A & B) | (B &
CARRY_IN) | (A & CARRY_IN), confirming logical correctness. A #10 delay ensures
stable output before each test case is recorded. The $display command prints results for
direct truth table comparison, and $finish terminates execution. The timing diagram
confirms correct operation, verifying the full adder’s accuracy.

Task
Write the design code and test bench for full subtrator. discuss its time
diagrame in detail.
FULL SUBTRACTOR:
This is one kind of combinational logic circuit, used to perform the subtraction of two
binary digits like 0s and 1s. Subtraction of binary digits from 0 to 0 or 0 to 1 does not
alter the result, subtraction of 1 to 1 will result as 0 but the subtraction of 1 to 0 needs
borrow.
A full Subtractor is a digital circuit that performs the subtraction of three single-digit
binary numbers. This is a three-input and two-output digital circuit.
For three single-bit binary numbers A, B, and Bin, the full subtractor circuit generates
two single-bit binary outputs D (Difference), and B_out(Borrow Output).

Figure 1: block diagram of full subtractor

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Figure 2: truth table of full subtractor

Figure 3 : logic diagram of full subtractor

DIFFERENCE Calculation

• If we subtract B and BIN from A, the result can be 0 or 1.

• XOR (⊕) operation gives the correct DIFFERENCE:
DIFFERENCE=A⊕B⊕BIN
• This means:
o If A and B are the same, their XOR is 0, and the result depends on BIN.
o If A and B are different, their XOR is 1, and the result flips with BIN.

Borrow occurs when:

1. A is 0 but we need to subtract 1 (from B or BIN).
2. If B is 1, it already demands a borrow.
3. If BIN is 1, it adds another borrow requirement.
Mathematically,
BOUT = (~A & B) | ((~A | B) & BIN)
• (~A & B): Borrow is needed when A is 0 and B is 1.
• (~A | B) & BIN: If A is 0 or B is 1, and BIN is also 1, borrow is required.

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MODULE WINDOW:

TESTBENCH WINDOW:

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TIMING DIAGRAMS:

Analysis:
when A = 0, B = 0, and BORROW_IN = 0, no subtraction occurs since both A and B are
zero, and no borrow is present. As expected, the DIFFERENCE remains 0, and
BORROW_OUT is also 0, confirming that the circuit correctly handles this trivial case.

Analysis:
For A = 0, B = 0, and BORROW_IN = 1, the result is DIFFERENCE = 1 with
BORROW_OUT = 1, confirming correct borrow handling as verified by the timing

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diagram.

Analysis:
For A = 0, B = 1, and BORROW_IN = 0, the result is DIFFERENCE = 1 with
BORROW_OUT = 1. When BORROW_IN = 1, the result becomes DIFFERENCE = 0
with BORROW_OUT = 1, confirming the truth
table.

Analysis:
The timing diagram confirms this behavior by displaying DIFFERENCE = 0 and
BORROW_OUT = 1, which matches the truth table perfectly. This validates that the
circuit correctly processes this input case, handling borrow propagation as expected.

Analysis:
For A = 1, B = 0, and BORROW_IN = 0, the result is DIFFERENCE = 1 with no
borrow. When BORROW_IN = 1, the result becomes DIFFERENCE = 0 with
BORROW_OUT = 0, confirming correct borrow handling..

Analysis:
For A = 1, B = 0, and BORROW_IN = 1, the operation 1 - 0 - 1 results in 0. No borrow
is needed as A already accommodates the subtraction. The expected output,
DIFFERENCE = 0 and BORROW_OUT = 0, confirms correct circuit
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operation.

Analysis:
For A = 1, B = 1, and BORROW_IN = 0, the operation 1 - 1 - 0 results in 0. No borrow
is needed as A and B are equal. The expected output, DIFFERENCE = 0 and
BORROW_OUT = 0, confirms correct circuit
behavior.

Analysis:
For A = 1, B = 1, and BORROW_IN = 1, the operation 1 - 1 - 1 results in 1 with a
BORROW_OUT of 1. The circuit correctly handles borrowing, confirming its expected
functionality.

DISCUSSION:
The full subtractor testbench verifies the circuit’s correctness by applying all possible
input combinations under the timescale 10ns / 100ps, ensuring precise timing. Inputs (A,
B, BORROW_IN) are defined as reg for controlled assignment, while outputs
(DIFFERENCE, BORROW_OUT) are wire, driven by combinational logic. The
subtractor follows the expected equations: DIFFERENCE = (A ⊕ B) ⊕ BORROW_IN
and BORROW_OUT = (~A & B) | ((~A | B) & BORROW_IN), confirming logical
accuracy. A #10 delay ensures stable output before recording each test case. The $display
command prints results for direct comparison with the truth table, and $finish terminates
execution. The timing diagram confirms correct operation, verifying the full subtractor’s
functionality.

Conclusion:

• From this lab, we have learned to design and implement a comprehensive

testbench for verifying the functionality of a Full Adder circuit.
• The testbench allowed systematic input application and output analysis to ensure
the circuit operates correctly.
• This experience provided practical knowledge of digital circuit verification,
emphasizing the importance of testbenches in FPGA design and simulation.

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• The lab enhanced our understanding of verification methodologies, improving our

ability to debug and validate digital circuits effectively.

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