Scribd
Upload
2 views

Lab Assignment 1

The lab assignment focuses on introducing FPGA I/O and combinational logic using the Quartus II software and DE2 board. It includes tasks such as creating Verilog modules for I/O mapping, hexadecimal display, and a simple adder, along with simulation and testing on the hardware. Additionally, it poses questions about design methods and offers a challenge to enhance the adder with overflow detection.

Uploaded by

tdat1406
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
2 views

Lab Assignment 1

The lab assignment focuses on introducing FPGA I/O and combinational logic using the Quartus II software and DE2 board. It includes tasks such as creating Verilog modules for I/O mapping, hexadecimal display, and a simple adder, along with simulation and testing on the hardware. Additionally, it poses questions about design methods and offers a challenge to enhance the adder with overflow detection.

Uploaded by

tdat1406
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Lab Assignment 1:

Introduction to FPGA I/O and Combinational Logic

To familiarize with the Quartus II workflow, basic Verilog syntax for combinational logic,
FPGA pin assignments, and using the DE2 board's switches, LEDs, and 7-segment displays. The
lab introduces the fundamental process of creating a simple digital circuit in Verilog, simulating
it, assigning physical FPGA pins to the design's inputs and outputs, compiling the design, and
programming the FPGA chip on the DE2 board. We will implement circuits that directly map
switch inputs to LED outputs and display switch values on 7-segment displays. a simple binary
adder will also be implemented in this lab.

Tasks:

1. Project Setup: Create a new Quartus II project targeting the FPGA chip on the DE2
board.
2. Basic I/O Mapping:
o Write a Verilog module (io_map) that connects the lower 8 switches (SW[7:0])
directly to the red LEDs (LEDR[7:0]).
o Instantiate this module in a top-level file for the DE2 board.
3. Hexadecimal Display:
o Modify your top-level module (or create a new one, hex_display) to display the
hexadecimal value of switches SW[3:0] on HEX0 and SW[7:4] on HEX1. You
will need a sub-module (e.g., hex_decoder) that converts a 4-bit binary input to
the 7 signals required for a 7-segment display.
o Hint: You can find standard 7-segment decoder logic online or derive it. Ensure
common-anode configuration if applicable (DE2 uses common-anode, meaning a
'0' turns a segment ON).
4. Simple Adder:
o Create a new Verilog module (simple_adder) that takes two 4-bit inputs, A (from
SW[7:4]) and B (from SW[3:0]), and produces an 8-bit sum S. Display the sum S
on LEDR[7:0].
o Hint: Use the Verilog + operator for addition.
5. Simulation: Create Vector Waveform Files (.vwf) to simulate the hex_decoder and
simple_adder modules. Verify their logical correctness before proceeding to hardware.
6. Pin Assignments: Using the DE2_pin_assignments.csv file or the Pin Planner tool,
assign the correct FPGA pins to your top-level module's inputs (SW switches) and
outputs (LEDR LEDs, HEX0, HEX1 segments).
7. Compilation & Download: Compile your chosen design (e.g., the Hex Display or
Simple Adder). Ensure there are no timing violations (though unlikely for this simple
design). Download the compiled .sof file to the DE2 board.
8. Testing: Test the functionality on the DE2 board by toggling the switches and observing
the LEDs and 7-segment displays.

Questions:
1. What is the purpose of the Quartus II Pin Planner or using a pin assignment file? Why is
it necessary?
2. In your hex_decoder module, explain how you converted the 4-bit binary input to the 7-
segment control signals. Did you use logic equations, a case statement, or another
method?
3. When you compiled the simple_adder design, check the compilation report. How many
Logic Elements (LEs or ALUTs) did Quartus II use to implement the 4-bit adder?
4. What is the difference between a structural and a behavioral description in Verilog?
Which style did you primarily use for the adder and the hex decoder?
5. If you connected SW[15:0] directly to LEDR[15:0], would this be considered
combinational or sequential logic? Why?

Challenge (Bonus):

• Modify the simple_adder design to include an overflow output signal. Connect this signal
to LEDG[0]. Implement the logic to detect overflow for unsigned addition. Test its
functionality.

Deliverables Report includes:

• Verilog code for all modules (io_map.v, hex_display.v, hex_decoder.v, simple_adder.v,


top-level files).
• Screenshots of your simulation waveforms verifying the hex_decoder and simple_adder.
• Screenshots of the result on DE2 board
• A brief answer for the questions.

You might also like