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Lec 10

The document discusses the Input/Output subsystem in computer architecture, detailing the roles of input and output devices and the methods of data transfer between memory and peripherals. It explains the importance of interrupts in managing I/O operations and describes bus organization, types of buses, and how data is transferred within a system. Additionally, it covers the construction of common bus systems using multiplexers and three-state buffers for efficient data transfer.

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4 views

Lec 10

The document discusses the Input/Output subsystem in computer architecture, detailing the roles of input and output devices and the methods of data transfer between memory and peripherals. It explains the importance of interrupts in managing I/O operations and describes bus organization, types of buses, and how data is transferred within a system. Additionally, it covers the construction of common bus systems using multiplexers and three-state buffers for efficient data transfer.

Uploaded by

flhi6876
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Computer Architecture

I/O Systems
The Input/Output Subsystem
 Input and output (I/O) devices allow us to communicate with the
computer system.
 I/O is the transfer of data between primary memory and various I/O
peripherals.
 Input devices: keyboards, mice, scanners, voice, and touch screens (data
in)
 Output devices: monitors, printers, and speakers (data out)
 These devices are not connected directly to the CPU. Instead, there is an
interface that handles the data transfers. This interface converts the
system bus signals to and from a format that is acceptable to the given
device.
This exchange of data is performed in two ways:
 memory-mapped I/O: the registers in the interface
appear in the computer’s memory map and there is no real
difference between accessing memory and accessing an I/O
device. Clearly, this is advantageous from the perspective of
speed, but it uses up memory space in the system.
 Instruction-based I/O: the CPU has specialized
instructions that perform the input and output. Although this
does not use memory space, it requires specific I/O
instructions, which implies it can be used only by CPUs that
can execute these specific instructions.
 Interrupts play a very important part in I/O, because they
are an efficient way to notify the CPU that input or output is
available for us.
Interrupts
Important question:
 How these components interact with the processor???

 Interrupts are usually defined as an event that alters


the sequence of instructions executed by a processor.

An interrupt can be triggered for a variety of reasons,


including:

 I/O requests.
 Arithmetic errors (e.g., division by zero).
 Arithmetic overflow.
 Hardware malfunction (e.g., memory parity error).
Interrupts (continued)
 Page faults.
 Invalid instructions (usually resulting from pointer
issues).
 The actions performed for each of these types of
interrupts (called interrupt handling) are very
different. Because telling the CPU that an I/O
request has finished is much different from
terminating a program because of division by zero.
Interrupts (continued)

•Processor is executing the instruction located at address i when an interrupt occurs.


•Routine executed in response to an interrupt request is called the interrupt-service
routine.
•When an interrupt occurs, control must be transferred to the interrupt service routine.
•But before transferring control, the current contents of the PC (i+1), must be saved in a
known location.
•This will enable the return-from-interrupt instruction to resume execution at i+1.
•Return address, or the contents of the PC are usually stored on the processor stack.
Interrupt
 Interrupts have two types: Hardware interrupt
and Software interrupt. The hardware interrupt
occurs by the interrupt request signal from
peripheral circuits. On the other hand, the
software interrupt occurs by executing a
dedicated instruction.
 Types of Hardware Interrupt: Can be maskable
(disabled or ignored) or nonmaskable (a high
priority interrupt that cannot be disabled and
must be acknowledged).
 Interrupts are often divided into synchronous and
asynchronous interrupts.
 synchronous (occurs at the same place every time
a program is executed such as division by zero) or
asynchronous (occurs unexpectedly such as I/O
request).
Bus organization and transfer

 The CPU communicates with the other components


via a bus.
 A bus is a set of wires that acts as a shared but
common data path to connect multiple subsystems
within the system.
 It consists of multiple lines, allowing the parallel
movement of bits.
 Buses are low cost but very versatile, and they make
it easy to connect new devices to each other and to
the system.
 At any one time, only one device (be it a register, the
ALU, memory, or some other component) may use the
bus.
 However, this sharing often results in a
communication bottleneck.
 The speed of the bus is affected by its length as well
as by the number of devices sharing it.
(a) Point-to-Point Buses: connecting two specific components

(b) A Multipoints Bus: common pathway that connects a number


of devices
 Computing system bus consists: of data lines, address
lines, control lines, and power lines.
What does each line-set contain?
1- Data bus:
 The lines of a bus is dedicated to moving data.
 These data lines contain the actual information that must be
moved from one location to another.

2- Control lines
 These lines indicate which device has permission to use the
bus and for what purpose (reading or writing from memory or
from an I/O device, for example).
 They also transfer acknowledgments for bus requests,
interrupts.
3- Address lines
 They indicate the location (in memory, for example) that the
data should be either read from or written to.
The power lines:
 They provide the electrical power necessary.
 Typical bus transactions include:
A) sending an address (for a read or write),
B) Sending the operation in control lines,
C) transferring data from memory to a register (a
memory read),
D) transferring data to the memory from a register (a
memory write).

 In addition, buses are used for I/O reads and


writes from peripheral devices.
 Each type of transfer occurs within a bus cycle.
Types of buses according to connected components
 Processor-memory buses are short, high-speed buses
that are closely matched to the memory system on the
machine to maximize the bandwidth (transfer of data) and
are usually very design specific.
 I/O buses are typically longer than processor-memory
buses and allow for many types of devices with varying
bandwidths. These buses are compatible with much
different architecture.
 A backplane bus (system bus) is actually built into the
chassis of the machine and connects the processor, the I/O
devices, and the memory (so all devices share one bus)
Common Bus system configuration:

 A more efficient scheme for transferring


information between common bus registers in a
multiple-register configuration is a common bus
system.
 A bus structure consists of a set of common lines,
one for each bit of a register, through which binary
information is transferred one at a time.
 Control signals determine which register is selected
by the bus during each particular register transfer.

Constructing a common bus system


a. Using multiplexers
b. Using three state buffers
Using multiplexers.
 One way of constructing a common bus system is
with multiplexers.
 The multiplexers select the source register whose
binary information is then placed on the bus.
 In general, a bus system will multiplex k registers of n bits
each to produce an n-line common bus.
 The number of multiplexers needed to construct the bus is
equal to n.
 The size of each multiplexer must be k x 1 since it
multiplexes k data lines.
For example:
 A common bus for eight registers of 16 bits each requires
?multiplexers, one for each line in the bus.
So:
 Each multiplexer must have ? data input lines and ?
selection lines to multiplex one significant bit in the eight
registers.
 In general, a bus system will multiplex k registers of n bits
each to produce an n-line common bus.
 The number of multiplexers needed to construct the bus is
equal to n.
 The size of each multiplexer must be k x 1 since it
multiplexes k data lines.
For example:
 A common bus for eight registers of 16 bits each requires
16 multiplexers, one for each line in the bus.
So:
 Each multiplexer must have eight data input lines and three
selection lines to multiplex one significant bit in the eight
registers.
8 registers of 2 bits
 Common Bus using Mux

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Using three state buffers.
 A bus system can be constructed with three-state
gates instead of multiplexers.

A three-state gate:
 Is a digital circuit that exhibits three states. Two of
the states are signals equivalent to logic 1 and 0 as in
a conventional gate. The third state is a high-
impedance state.
 The high-impedance state behaves like an open circuit,
which means that the output is disconnected and does
not have logic significance.
 When the control input of the buffer is equal to 1,
the output is enabled and the gate behaves like any
conventional buffer, with the output equal to the
normal input.
 When the control input is 0, the output is disabled
and the gate goes to a high-impedance state (Hi-Z),
regardless of the value in the normal input.
4 registers of 2 bits
 Common bus using Tri-state buffer or (three state buffers)

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