Lecture 9

Memory Organization

1
 Write Policy
 An important aspect of cache
organization is concerned with
memory write requests.
 When the CPU finds a word in cache
during a read operation, the main
memory is not involved in the transfer.
 However, if the operation is a write,
there are two ways that the system
can proceed:
1. Write-through
2. Write-back
2
1. Write-through
 The simplest and most commonly used
procedure.
 Update main memory with every
memory write operation, with cache
memory being updated in parallel if it
contains the word at the specific
address.
 This method has the advantages that
main memory always contains the
same data as cache.

3
1. Write-through
 It ensures that the data residing
in main memory are valid at all
times so that an I/O device
would receive the most recent
updated data.
 However, it has the
disadvantage of high memory
traffic and may create a
bottleneck.
4
 2. Write-back
 Only the cache location is updated
during a write operation.
 The location is then marked by a flag
(called update bit or dirty bit) so that
later when the word is removed
(replaced) from the cache, it is copied
into main memory.
 The reason for the write back method is
that during the time a word resides in
the cache, it may be updated several
times;
 However, as long as the word remains
in the cache, it does not matter whether
the copy in main memory is out of date,
since requests from the word are filled5

from the cache.

2. Write-back
 It is only when the word is displaced
from the cache that an accurate copy
need be rewritten into main memory.
 The problem of this technique is that
portions of memory are invalid and
thus access from I/O modules to this
data can be through cache instead.
 This will require complex circuitry
and potential bottleneck.

6
Virtual Memory
 Most modern computer systems use a hard
disk (also called a hard drive) as the lowest
level in the memory hierarchy.
 Compared with the ideal large, fast, cheap
memory, a hard disk is large and cheap but
terribly slow. The disk provides a much larger
capacity than is possible with a cost-effective
main memory(DRAM).
 Virtual Memory is a storage scheme that
provides user an illusion of having a very big
main memory. This is done by treating a part of
secondary memory as the main memory.

Chapter 8 <7>
Memory Hierarchy

Access Bandwidth
Technology Price / GB
Time (ns) (GB/s)

SRAM $10,000 1 25+

Cache
Speed

DRAM $10 10 - 50 10
Main Memory

SSD $1 100,000 0.5

HDD $0.1 10,000,000 0.1
Virtual Memory
Capacity

• Physical Memory: DRAM (Main Memory)

• Virtual Memory: Hard drive
– Slow, Large, Cheap
Chapter 8 <8>
Hard Disk

Magnetic
Disks

Read/Write
Head

Takes milliseconds to seek correct location on disk

Chapter 8 <9>
Virtual Memory
 Virtual addresses
 Programs can access data anywhere in virtual
memory, so they must use virtual addresses that
specify the location in virtual memory.
 The physical memory holds a subset of most
recently accessed virtual memory.
 In this way, physical memory acts as a cache for
virtual memory.
 CPU translates virtual addresses into physical
addresses (DRAM addresses)
 The process of determining the physical address
from the virtual address is called address
translation.
 Data not in DRAM fetched from hard drive.
 Main memory (DRAM) acts as cache for hard disk
Chapter 8 <10>
Cache/Virtual Memory Analogues

Cache Virtual Memory

Block Page
Block Size Page Size
Block Offset Page Offset
Miss Page Fault
Tag Virtual Page Number

Physical memory acts as cache for virtual memory

Chapter 8 <11>
Virtual Memory Definitions
 Page size: amount of memory
transferred from hard disk to DRAM
at once.
 Address translation: determining
physical address from virtual
address
 Page table: lookup table used to
translate virtual addresses to
physical addresses

Chapter 8 <12>
Virtual & Physical Addresses

Chapter 8 <13>
Address Translation

 virtual memory and physical

memory are divided into pages.
 The most significant bits of the
virtual or physical address specify
the virtual or physical page
number.
 The least significant bits specify
the word within the page and are
called the page offset.

Chapter 8 <14>
Address Translation

Chapter 8 <15>
Virtual Memory Example
 System:
 Virtual memory size: 2 GB = 231
bytes
 Physical memory size: 128 MB =
227 bytes
 Page size: 4 KB = 212 bytes

Chapter 8 <16>
Virtual Memory Example
 System:
 Virtual memory size: 2 GB = 231 bytes
 Physical memory size: 128 MB = 227
bytes
 Page size: 4 KB = 212 bytes
 Organization:
 Virtual address: 31 bits
 Physical address: 27 bits
 Page offset: 12 bits
 # Virtual pages = 231/212 = 219 (VPN =
19 bits)
 # Physical pages = 227/212 = 215 (PPN =
Chapter 8 <17>
15 bits)
Virtual Memory Example
 19-bit virtual page
numbers
 15-bit physical page
numbers

Chapter 8 <18>
Virtual Memory Example

What is the physical

address of virtual
address 0x247C?

Chapter 8 <19>
Virtual Memory Example
What is the physical
address of virtual
address 0x247C?
 VPN = 0x2
 VPN 0x2 maps to PPN 0x7FFF
 12-bit page offset: 0x47C
 Physical address = 0x7FFF47C

Chapter 8 <20>
How to perform translation?
 Page table
 The processor uses a page table to
translate virtual addresses to
physical addresses.
 The page table contains an entry for
each virtual page.
 Entry fields:
 Valid bit: 1 if page in physical memory,
Otherwise, the virtual page is found on
disk.
 Physical page number: where the
page is located
Chapter 8 <21>
Page Table Example
Virtual Page
Page Number Offset
Virtual
0x00002 47C
Address
19 12

Physical
V Page Number
0
0
1 0x0000
VPN is index 1
0
0x7FFE

Page Table
into page table 0

0
0
1 0x0001
0
0
1 0x7FFF
0
0
15 12
Hit
Physical
0x7FFF 47C
Address
Chapter 8 <22>
Page Table Example 1

What is the physical V

Physical
Page Number
0
address of virtual 0
1 0x0000
address 0x5F20? 1
0
0x7FFE

Page Table
0

0
0
1 0x0001
0
0
1 0x7FFF
0
0

Chapter 8 <23>
Page Table Example 1
Virtual Page
Page Number Offset
Virtual
0x00005 F20
Address
19 12

What is the physical V

Physical
Page Number
0
address of virtual 0
1 0x0000
address 0x5F20? 1
0
0x7FFE

Page Table
VPN = 5 – 0

Entry 5 in page table – 0

0
VPN 5 => physical 1 0x0001
0
page 1 0
1 0x7FFF
Physical address: – 0
0
0x1F20 Hit
15 12

Physical
0x0001 F20
Address

Chapter 8 <24>
Page Table Example 2
Virtual Page
Page Number Offset
Virtual
0x00007 3E0
Address
19

What is the Physical

Page Number
physical V
0
0
address of 1 0x0000
1 0x7FFE
virtual address 0

Page Table
0
0x73E0?
0
0
1 0x0001
0
0
1 0x7FFF
0
0
15
Hit

Chapter 8 <25>
Page Table Example 2
Virtual Page
Page Number Offset
Virtual
0x00007 3E0
Address
19

What is the Physical

Page Number
physical address of V
0
0
virtual address 1 0x0000
1 0x7FFE
0x73E0? 0

Page Table
0
VPN = 7 –
Entry 7 is invalid – 0
0
Virtual page must – 1
0
0x0001

be paged into 0
1 0x7FFF
physical memory 0
0
from disk 15
Hit

Chapter 8 <26>
The Translation Lookaside Buffer
• The page table is usually so large that it is
located in physical memory. Hence, each load
or store involves two physical memory
accesses: a page table access, and a data
access.
• To speed up address translation, a translation
lookaside buffer (TLB) caches the most
commonly used page table entries.
• A TLB is organized as a fully associative cache
and typically holds16 to 512 entries.

Chapter 8 <27>
The Translation Lookaside Buffer
• Each TLB entry holds a virtual page number
and its corresponding physical page number.
The TLB is accessed using the virtual page
number.
• If the TLB hits, it returns the corresponding
physical page number.
• Otherwise, the processor must read the page
table in physical memory.

Chapter 8 <28>
Example 8.15 USING THE TLB TO PERFORM ADDRESS
TRANSLATION

Consider the virtual memory system of Figure 8.21. Use a two-entry

TLB, explain why a page table access is necessary to translate
virtual addresses 0x247C and 0x5FB0 to physical addresses.

Solution: Figure 8.25 shows the two-entry TLB with the request for
virtual address 0x247C. The TLB receives the virtual page number
of the incoming address, 0x2, and compares it to the virtual page
number of each entry. Entry 0 matches and is valid, so the request
hits. The translated physical address is the physical page number of
the matching entry, 0x7FFF, concatenated with the page offset of the
virtual address. As always, the page offset requires no translation.
The request for virtual address 0x5FB0 misses in the TLB. So, the
request is forwarded to the page table for translation.

Chapter 8 <29>
Chapter 8 <30>
Write and Replacement Policies

• Virtual memory systems use write-back and an

approximate least recently used (LRU) replacement
policy.
• A write-through policy, where each write to physical
memory initiates a write to the hard drive, would be
impractical. Store instructions would operate at the
speed of the hard drive instead of the speed of the
processor.
• Under the write-back policy, the physical page is
written back to disk only when it is evicted from
physical memory.
• To support these replacement policies, each page
table entry contains two additional status bits: a dirty
bit, D, and a use bit, U.
Chapter 8 <31>