Scribd
Upload
3 views

2.day RTL2GDS

The document outlines the VLSI design flow, which is a methodology for designing integrated circuits (ICs) based on application scope and design styles. It discusses different types of ICs, including ASICs and GPICs, and various design approaches such as full-custom, standard-cell-based, gate-array, and FPGA designs. Additionally, it covers economic considerations, performance metrics, and trade-offs involved in chip design.

Uploaded by

balanallam1005
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
3 views

2.day RTL2GDS

The document outlines the VLSI design flow, which is a methodology for designing integrated circuits (ICs) based on application scope and design styles. It discusses different types of ICs, including ASICs and GPICs, and various design approaches such as full-custom, standard-cell-based, gate-array, and FPGA designs. Additionally, it covers economic considerations, performance metrics, and trade-offs involved in chip design.

Uploaded by

balanallam1005
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 8

RTL2GDS-UNFOLDED NOTES

Adithya Mallisetti
1

DAY-2
#RTL2GDS-Unfolded
Q. What is VLSI Design Flow?
Methodology to design an IC such that it provides the
complete/desired functionality.

Q. What decides the VLSI design Flow?


• Scope of Application.
• Design Styles.

Based on Scope of Application:


• Application-Specific ICs
o Ex: Ic for Digital Camera,Video.
• General-purpose IC’s
o Ex: Microprocessors, Memory, FPGA.

Types of Integrated Circuits:


• ASICs: A chip designed to perform a specific task
or function is called Application-specific Integrated
Circuits.

RTL2GDS-UNFOLDED NOTES ADITHYA


2

• GPICs: A chip designed to perform a wide range


of applications are called General-Purpose
Integrated Circuits.

The volume of Production


• ASICs-Less
• GPICs-More

Based on Design Styles:


• Full-Custom Design:
o The layout of Transistors and interconnects is
design-specific.
▪ Merit: Design can be highly optimized.
• Standard-cell-based Design:
o Firstly It creates simple cells like AND, and
NAND designs, which are kept in a library and
further used.
o They have fixed sizes.
o Offers a high degree of automation.
• Gate-Array based Design:
o A gate array is an approach to the design and
manufacture of application-specific integrated
circuits (ASICs) using a prefabricated chip
with components that are later interconnected

RTL2GDS-UNFOLDED NOTES ADITHYA


3

into logic devices (e.g. NAND gates, flip-


flops, etc.)
o According to custom order by adding metal
interconnect layers in the factory.
o The designer defines interconnects between the
transistors.
• FPGA(Field Programmable Gate Array) Based
Design:
o IC hardware is fixed.
o The designer gets the desired functionality by
programming.
o Programming changes the interconnections
between the elements of the circuit.
o FPGA consists of an array of logic blocks, I/O
blocks, and routing channels.
o FPGA may also have embedded
microprocessors and analog components like
DSP blocks.
Ex: Xilinx(AMD), Altera(Intel).

Q. Which is a more complex Design..?


• Full custom design is the more complex design.
• It involves designing every transistor and layout
specifically for the application.

RTL2GDS-UNFOLDED NOTES ADITHYA


4

• Economics of Chip Design:


o Costs of design, fabrication, testing, packaging,
and distribution. The process involves significant
investment and careful consideration of market
demand, performance, and cost efficiency.
• Fixed Product Cost:
▪ Cost of Designing
▪ Software Tools
▪ Hardware
▪ Cost of Masks
• Variable Product Cost:
▪ Cost of Wafer.
▪ Cost of dies.

For Small volumes, FPGA is better, for large


volumes Standard-cell-based design is better.
Because
Cost Considerations
• FPGA:
o Initial Cost: FPGAs have relatively low non-
recurring engineering (NRE) costs because
they are pre-fabricated and can be programmed
after manufacturing.
o Per-Unit Cost: The per-unit cost of FPGAs is
typically higher than that of custom ASICs or
standard-cell designs. However, for small
RTL2GDS-UNFOLDED NOTES ADITHYA
5

volumes, this cost is often outweighed by the


lack of high upfront expenses.
• Standard-Cell-Based Design:
o Initial Cost: Standard-cell ASIC design
involves significant NRE costs, including
design, verification, and mask set creation for
fabrication. These costs are high, making the
initial investment substantial.
o Per-Unit Cost: Once the design and fabrication
process is set up, the per-unit cost of producing
standard-cell ASICs decreases significantly
with volume. This is due to economies of scale
and the lower material cost per chip compared
to FPGAs.
The goodness of an IC:
PPA- Power, Performance(Speed), Area.
• Power: Sum of static and dynamic power
consumed by an IC.(Minimum).
• Performance: The maximum clock frequency at
which the IC works. (It should be maximum)
• Area: It is as less as possible.(Minimum).

Other FiguresOfMerit's/Quality of Results:


Testability: In VLSI (Very Large Scale Integration)
design, testability refers to the ability to efficiently and
effectively test integrated circuits (ICs) to ensure they
RTL2GDS-UNFOLDED NOTES ADITHYA
6

meet their design specifications and are free from


manufacturing defects.
Reliability: Reliability refers to the ability of an
integrated circuit (IC) to perform its intended function
correctly and consistently over its expected operational
lifetime, even under various environmental conditions
and stress factors. (OR) Trustability
Schedule: Schedule refers to the detailed timeline or
plan that outlines the various stages and tasks involved
in the design, development, testing, and production of
an integrated circuit (IC).
These above all are FOMs and QORs.

Trade-off: Trade-off refers to a situation where gaining


one quality or benefit results in the loss of another. In
chip design and engineering (including FPGAs vs
ASICs), trade-offs are common because optimizing for
one factor (like cost, performance, or power efficiency)
often comes at the expense of others.
Improving one quantity adversely affects the other
parameters.
Some measures are required to be traded off.
The goal of a Design Flow is to find out the feasible
solution which best suits for the design.

RTL2GDS-UNFOLDED NOTES ADITHYA


7

========================================

RTL2GDS-UNFOLDED NOTES ADITHYA

You might also like