International Journal For Technological Research In Engineering

Volume 3, Issue 10, June-2016 ISSN (Online): 2347 - 4718

IMPLEMENTATION OF 4-BIT TWO STEP FLASH ADC USING

180nm TECHNOLOGY
Murugesh H M1, Dr Nagesh K N2
1
M.Tech VLSI Design and Embedded Systems, ECE Dept., 2Prof. and HOD ECE Dept.
NCET, Bengaluru, India.

Abstract: Analog-to-Digital converters (ADCs) are essential interface for portable battery mechanical system require
in approximately all communication and signal processing analog -to -digital converters and other interface essentials
application. In the current paper, it has been shown that a that dissolve the lowest possible power and operate on
4-bit Two Step Flash Analog-to-Digital (ADC) which has supply voltages friendly with the digital parts of the system.
Flash ADC, Resistor String DAC along with Sample and Also the rate and performance make it attractive to attain
Hold, all the sub-blocks are implemented using Cadence high level of incorporation on a single chip for varied signal
Virtuoso 180nm technology at an operating voltage of 2V. processing system. In the earlier time a few of the high speed
The simulated results shows a power dissipation of 0.75mw ADC’s have been calculated using bipolar technology, but
having the input frequency of 1 KHz and input voltage of the manufacture of these devices turn into very complex and
2V. The proposed design achieves low power consumption; large chip area and power. The idea for CMOS is that
Conversion time and delay are minimized. This occupation advanced level of combination and low power are possible
also includes the comparison among One Step Flash ADC then in the bipolar implementation [2].
and the projected Two Step Flash ADC.
Keywords: Sample and Hold; Flash ADC; Residue II. FLASH ADC ARCHITECTURE WITH TWO STEP
Amplifier; Comparatore. FLASH ADC APPROACH
On the other hand, we have different architectures of Flash
I. INTRODUCTION ADC’s as confirmed in the literature, but to complete our
A current wireless communication device asks for high data main goal that is high speed and low power. Two-Step Flash
rates with low power consumption and high speed. The ADC architecture is used. Initially, this architecture improve
important components in the wireless receivers is the analog the speed of our ADC, may be a small bit, but the optimized
to digital converter, it is a boundary between analog and components enhance the speed to a significant level. In many
digital design. For a System-On-Chip (SOC) application, applications it is essential to have a lesser conversion time
needed or require a less voltage, less power and more ADC. ADC’s considered for such application are the high
accurate analog -to -digital converters, high speed, less power speed ADC’s that use the equivalent techniques to reach the
are most requirements in many wireless applications. A Two shorter conversion period. One way of achieving this is to
Step Flash converter or Parallel Feed-Forward ADC is a type amplify the speed of the individual components, which will
of ADC. The converter of Two Step Flash ADC is separated increase the speed of the entire system. The prospective of
into two complete Flash ADC’s with Feed-Forward circuitry Two Step Flash architectures for realizing fast, high
to obtain a better and improved result. In this paper, Flash resolution analog -to -digital converters are established in a
ADC or Parallel ADC are used because of their speed of number of design in [4,5]&[6].With the alteration rates
converting an analog signal to digital signal is fastest their approaching half those of fully parallel (Flash ADC).
requirements are suitable for implementation. However Flash
converters use a lot of power, have comparatively low
resolution, and can be moderately costly. This confines them
to high frequency applications that cannot be address in any
other technique. Examples contain Data gaining, satellite
communications, radar processing, sampling oscilloscope and
high concentration disk drives. Two Step Flash ADC
approach is the favored design as it reduces area as well as
power. High resolution with low area is reachable however at
the expense of speed. The speed of the analog –to –digital
and digital –to -analog interface must balance with the speed Fig.1 Block diagram 4-bit Two-Step Flash ADC
of the digital circuits in organize to fully make use of the The fundamental structure of the Two Step Flash converter is
advantages of the advanced technologies. Recently low shown in Fig.1. The initial converter generates a rough
power, compact size and high resolution analog –to –digital estimation of the value of the input, and the second converter
interface circuits have been in large demand for convenient performs a very well conversion. The benefit of this
system such as camcorders, cellular phones and personal architecture is that the amount of comparators is very much
digital support etc. High integration analog -to -digital reduced from that of the flash converter from 2𝑁 − 1

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International Journal For Technological Research In Engineering
Volume 3, Issue 10, June-2016 ISSN (Online): 2347 - 4718

comparators to 2(2𝑁/2 − 1) comparators. For example, an 8 applied to it. Or else, the comparator in Fig.1.output is "0".
bit flash converter require 255 comparators, while the step As shown in Fig. 3, the Flash ADC is composed of three
require only 30.The transaction is that the exchange process most important components: resistors string, comparators
takes two steps as an alternative of one, with the speed and priority encoder. The analog input voltage is at the same
inadequate by bandwidth and settle time necessary by the time as compare to the reference voltage levels generated
residue amp and the summer. from resistors string and the speed of A/D conversion is
consequently maximize. The outputs of comparators
III. DESIGN OF SUB-BLOCKS OF TWO STEP FLASH appearance a thermometer code (TC) which is a mixture of a
ADC sequence of zeros and a sequence of ones, e.g.,
To get better the speed we optimize the different mechanism 0000…0011…1111. Since binary code is typically wanted
of the ADC on your own and by you. The design of the for digital signal processing, a thermometer code is then
different mechanism of ADC is selected so that when they altered to a binary code encoder. The rate of such a
are cascade together they improve the speed considerably. conventional encoder increases exponentially with the
resolution. Optimizations on area rate, circuit latencies and
Comparator power consumption are very much projected. In this paper
Comparator is a significant circuit in analog and mixed signal we have low power Comparator used in the implementation
design. The Two Step Flash ADC consists of Flash and all through a Comparator Circuit & implementation
Resistor String DAC structural design, in which comparator Specification.
is used as significant blocks to calculate the result. The two
stage operational amp is used as a comparator. The Fig. 2
shows the planned schematic of comparator circuit [2]. The
primary stage of the designed comparator consists of two
parts, one is biasing circuit to bias the present mirror and
another part is differential amp. The second stage is gain
stage to get better the gain of operational amp.

Fig. 3 Schematic of 4-bit Flash ADC with Thermometer code

to binary code converter.

Integration of Flash ADC and DAC Circuit

Fig. 2 Schematic of Comparator Circuit.

Flash ADC
Fig.3. shows a classic Flash analog –to -digital Converter
schematic diagram. On behalf of an "N" bit converter, the
circuit employs 2𝑁 − 1 comparators. Resistive dividers with
2𝑁 resistors provide the reference voltage. The reference
voltage for each one comparator is one least significant bit
(LSB) bigger than the reference voltage for the comparators
instantly lower it. All comparator produce a "1" while its
analog input voltage is higher than the reference voltage Fig.4 Schematic of Two-Step 4-bit Flash ADC

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International Journal For Technological Research In Engineering
Volume 3, Issue 10, June-2016 ISSN (Online): 2347 - 4718

The Fig. 4 shows the schematic sketch of a 4-bit Two-Step work as 9.01ms where as existing work as 41.014ms.
Flash ADC circuit. It consists of inner sub-blocks of Sample
and Hold circuit, subtract or with gain stage of residue V. CONCLUSION
amplifier, Resistor String DAC, Flash ADC. The work obtainable in this document is to design and
examine the performance individuality of the Two Step Flash
IV. RESULTS & DISCUSSIONS ADC mechanism. For this propose method are developed for
The major reason of our design is to get high speed with low individual mechanism of the analog –to –digital converter.
power. The output waveforms obtain for Flash ADC and Base on the method developed W/L ratio for all the
Two Step Flash ADC are shown in Fig.5, Fig. 6. Reference transistors are considered using the representation parameter
voltage is in use constant. The simulation has been run on of the 180nm CMOS technology. Individual mechanisms are
Cadence Virtuoso analog design phase and the implemented separately. The chosen technology as with the
implementation was done with 180nm technology. A supply scale of operating voltages to low values down to 2 V, it
voltage of 2V has been used and the comparisons of the ensures a high performance circuit. The considered
architectures are shown in Table I. mechanisms are best suitable for a whole Flash ADC. The
table I crates a comparison between delay, conversion time
and power dissipation with different ADC.

Acknowledgment
The author would like to acknowledge the assist of Dr.
Nagesh K N Prof. and HOD Dept of ECE for their support
with this development. The author is also thankful of
Department of Electronic & communication Engineering,
NCET. The mechanism was implemented using cadence tool
which is made obtainable by department.
Fig. 5 Simulation result of the 4-bit Flash ADC REFERENCES
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International Journal For Technological Research In Engineering
Volume 3, Issue 10, June-2016 ISSN (Online): 2347 - 4718

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