8237 DMA Controller

Dr. Gargi Alavani

Department of CS & IS

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8237 DMA Controller

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The 8237 DMA Controller Pin-out

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8237A-5 programmable DMA controller

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The 8237 DMA Controller Pin-out

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The 8237 DMA Controller Pin-out

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The 8237 DMA Controller Pin-out

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The 8237 DMA Controller Pin-out

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The 8237 DMA Controller Pin-out

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The 8237 DMA Controller Pin-out

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Internal Registers

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Internal Registers

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Command Register

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Mode Register

● The mode register programs the

mode of operation for a channel.
Note that each channel has its
own mode register, as selected
by bit positions 1 and 0.
● The remaining bits of the mode
register select the operation,
auto-initialization,
increment/decrement, and mode
for the channel

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Mode Register
● Demand mode transfers data until an
external EOP is input or until the DREQ
input becomes inactive.
● Single mode releases the HOLD after
each byte of data is transferred. If the
DREQ pin is held active, the 8237 again
requests a DMA transfer through the
DRQ line to the microprocessor’s HOLD
input.
● Block mode automatically transfers the
number of bytes indicated by the count
register for the channel. DREQ need not
be held active through the block mode
transfer.
● Cascade mode is used when more than
one 8237 is present in a system.
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Bus request register

● The bus request register

is used to request a DMA
transfer via software
● This is very useful in
memory-to-memory
transfers, where an
external signal is not
available to begin the
DMA transfer.

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Mask register set/reset

● The mask register set/reset

sets or clears the channel
mask
● If the mask is set, the channel
is disabled.
● Recall that the RESET signal
sets all channel masks to
disable them.

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The mask register

● clears or sets all of the masks

with one command instead of
individual channels, as with
the MRSR.

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 The Status Register

● The status register shows the status of

each DMA channel
● The TC bits indicate whether the
channel has reached its terminal count
(transferred all its bytes). Whenever the
terminal count is reached, the DMA
transfer is terminated for most modes of
operation.
● The request bits indicate whether the
DREQ input for a given channel is
active.

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Software Commands

Clear first-last flip-flop:

● This command resets the First/Last flip-flop in 8237 to zero.
● F/L = 0, the low-order byte is selected; if F/L = 1, the high-order byte is
selected

Master Clear:
● This command is used as software RESET.

Clear Mask Register:

● This command is used to clear the mask bits of the DMA channels in order to
enable all four DMA channels.

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Software Command Examples
➢ Enable or disable the DMA controller (Write Command Register)
➢ Set the transfer mode (block, demand, etc.) for a DMA channel
(Write Mode Register)
➢ Mask or unmask specific DMA channels (Write Single Mask Register
Bit)
➢ Clear internal flip-flops or temporary states (Master Clear, Clear Byte
Pointer Flip-Flop)
➢ Initiate a DMA request via software (Write Request Register)
➢ Read status of DMA channels (Read Status Register)
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Software Commands

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Programming the Address and Count Registers

● Four steps are required to program the 8237:

(1) The F/L flip-flop is cleared using a clear F/L command;
(2) The channel is disabled;
(3) The LSB and then MSB of the address are programmed
(4) The LSB and MSB of the count are programmed.

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Programming the Address and Count Registers

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The 8237 Connected to the 80X86 Microprocessor
Part A
Normal 8088
Operation (AEN = 0)
Active Latches:
Latch A provides
A19–A16.
Latch C provides A7–
A0.
Multiplexer E
provides control
signals.

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The 8237 Connected to the 80X86 Microprocessor
Part A

DMA Operation (AEN = 1)

Active Latches:
Latch B provides A19–A16.
Latch D provides A15–A8.
8237 directly provides A7–A0,
completing the 20-bit DMA
address.
Control signals (like MEMR,
MEMW, IOR, IOW) come from
the DMA controller instead of
the CPU.
ADSTB (Address Strobe from
8237) clocks the DMA address
bits into latch D.

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The 8237 Connected to the 80X86 Microprocessor
Part B
Temporarily stores upper
address bits A15–A8 from
the DMA controller.

Decodes I/O addresses to generate

chip-select signals for
programming:
• DMA controller
• DMA page registers (which
output A19–A16)

Routes control signals

(MEMR MEMW IOR IOW
, , , ) from either:

•The 8088 CPU (normal

operation, AEN = 0), or
•The 8237 DMA (DMA
operation, AEN = 1)

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The 8237 Connected to the 80X86 Microprocessor

● During normal 8086 operation, the DMA controller and integrated circuits B
and D are disabled.

● During a DMA action, integrated circuits A, C and E are disabled so that 8239
can take control of the system through the buses

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Programming DMA

• The leftmost digit of the 5-digit address is sent to Latch B.The F/L flip-
flop is cleared.
• Channels are programmed: Channel 0 is set as the source.
Channel 1 is set as the destination (for memory-to-memory transfer).
• The count register is programmed with a value one less than the
number of bytes to be transferred.
• The mode register of each channel is programmed.
• The command register is programmed to select a block move 29
operation.
Programming DMA

• The leftmost digit of the 5-digit address is

sent to Latch B.The F/L flip-flop is cleared.
• Channels are programmed: Channel 0 is
set as the source. Channel 1 is set as the
destination (for memory-to-memory
transfer).
• The count register is programmed with a
value one less than the number of bytes
to be transferred.
• The mode register of each channel is
programmed.
• The command register is programmed to
select a block move operation.

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Programming DMA

• The count register is programmed with a

value one less than the number of bytes
to be transferred.
• The mode register of each channel is
programmed.
• The command register is programmed to
select a block move operation.
• Channel 0 is enabled.
• A software DMA request is
initiated.Before exiting the procedure,
the status register is tested for a terminal
count.

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Programming DMA

Before exiting the procedure:

• The status register is checked for
terminal count (TC).
• The TC flag indicates the
completion of the DMA transfer.
• TC also disables the channel,
preventing further transfers.

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THANK YOU

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