PROBLEMS

Computer Simulation Problems

Problems identified by this icon are intended to (a) For VG1 = VG2 = 0 V, find |VOV | and VSG for each of Q1
demonstrate the value of using SPICE simulation to verify and Q2 . Also find VS , VD1 , VD2 , and VO .
hand analysis and design, and to investigate important issues (b) If the current source requires a minimum voltage of
such as allowable signal swing and amplifier nonlinear 0.2 V, find the input common-mode range.
distortion. Instructions to assist in setting up simulations for
all the indicated problems can be found in the corresponding D 8.3 Design the circuit in Fig. P8.3 to obtain a dc voltage
files on the website. Note that if a particular parameter value of +0.1 V at each of the drains of Q1 and Q2 when vG1 =
is not specified in the problem statement, you are to make a vG2 = 0 V. Operate all transistors at VOV = 0.15 V and
reasonable assumption. assume that for the process technology in which the circuit
2
is fabricated, Vtn = 0.4 V and μn Cox = 400 µA/V . Neglect
Section 8.1: The MOS Differential Pair
channel-length modulation. Determine the values of R, RD ,
8.1 For an NMOS differential pair with a common-mode and the W/L ratios of Q1 , Q2 , Q3 , and Q4 . What is the input
voltageVCM applied,asshowninFig. 8.2,letVDD = VSS = 1.0 V, common-mode voltage range for your design?
 2
kn = 0.4 mA/V , (W/L)1,2 = 10, Vtn = 0.4 V, I = 0.16 mA,
RD = 5 k, and neglect channel-length modulation.
VDD 0.9 V
(a) Find VOV and VGS for each transistor.
(b) For VCM = 0, find VS , ID1 , ID2 , VD1 , VD2 , and VO .
(c) Repeat (b) for VCM = +0.4 V. RD RD
(d) Repeat (b) for VCM = −0.1 V.
(e) What is the highest value of VCM for which Q1 and Q2
vG1 vG2
remain in saturation? Q1 Q2
0.9 V
(f) If current source I requires a minimum voltage of 0.2 V
0.1 mA
to operate properly, what is the lowest value allowed for
R
VS and hence for VCM ? 0.2 mA
(g) What is the input common-mode range?
Q4 Q3
8.2 For the PMOS differential amplifier shown in
 2
Fig. P8.2, let Vtp = −0.4 V and kp W/L = 5 mA/V . Neglect
channel-length modulation.
VSS 0.9 V
0.9 V
Figure P8.3

0.2 mA
D 8.4 Design the MOS differential amplifier of Fig. 8.5
V to operate at VOV = 0.25 V and to provide a transconduc-
tance gm of 1 mA/V. Specify the W/L ratios and the bias
current. The technology available provides Vt = 0.5 V and
2
V Q Q V
μn Cox = 400 µA/V .

D 8.5 Design an NMOS differential amplifier to operate

V  VO  V
with a differential input voltage that can be as high as 0.1 V
while keeping the nonlinear term under the square root in
4k 4k
Eq. (8.23) to a maximum of 0.04. A transconductance gm of 2
mA/V is needed, and the amplifier must provide a differential
output signal of 1 V when the input is at its maximum value.
0.9 V
Find the required values of VOV , I, RD , and W/L. Assume that
2
Figure P8.2 the technology available has μn Cox = 200 µA/V and λ = 0.

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 631

CHAPTER 8
D 8.6 Design a MOS differential amplifier to operate from transistor is operating. For dc bias calculations you may
±0.6-V supplies and dissipate no more than 0.3 mW in neglect channel-length modulation.
its equilibrium state. Select the value of VOV so that the
value of vid that steers the current from one side of the 1.5 V
pair to the other is 0.2 V. The differential voltage gain
 2
Ad is to be 8 V/V. Assume kn = 500 µA/V and neglect
the Early effect. Specify the required values of I, RD ,

PROBLEMS
and W/L. Q6 Q3

8.7 Find the differential half-circuit for the differential I

amplifier shown in Fig. P8.7 and use it to derive an expres- IREF
sion for the differential gain Ad ≡ vod /vid in terms of gm , RD ,
and Rs . Neglect the Early effect. What is the gain with Rs = 0?
R vid2 Q1 Q2 vid2
What is the value of Rs (in terms of 1/gm ) that reduces the gain
to half this value?
vod
VDD
Q4
Q7 Q5
RD RD

vod
vid vid
Q1 Q2
2 2 1.5 V

Figure P8.8
Rs

I I D *8.9 For the cascode differential amplifier of Fig. 8.13(a),

– –
2 2
show that if all transistors have  the same channel length
and are operated at the same VOV  and assuming that VAn

=
    
VSS VAp  = VA , the differential gain Ad is given by

Figure P8.7   2

Ad = 2 VA  VOV 

Now design the  amplifier

 to obtain
   a differential gain of
D *8.8 Figure P8.8 shows a circuit for a differential ampli- 500 V/V. Use VOV  = 0.2 V. If VA  = 5 V/µm, specify the
fier with an active load. Here Q1 and Q2 form the differential required channel length L. If gm is to be as high as possible
pair, while the current source transistors Q4 and Q5 form the but the power dissipation in the amplifier (in equilibrium) is
active loads for Q1 and Q2 , respectively. The dc bias circuit to be limited to 0.5 mW, what bias current I would you use?
that establishes an appropriate dc voltage at the drains of Q1 Let VDD = VSS = 0.9 V.
and Q2 is not shown. It is required to design the circuit to
8.10 For the differential amplifier specified in Problem 8.1
meet the following specifications:
let vG2 = 0 and vG1 = vid . Find the value of vid that
(a) Differential gain Ad = 50 V/V. corresponds to each of the following situations:
(b) IREF = I = 200 µA. (a) iD1 = iD2 = 0.08 mA; (b) iD1 = 0.12 mA and iD2 = 0.04 mA;
(c) The dc voltage at the gates of Q6 and Q3 is +0.8 V. (c) iD1 = 0.16 mA and iD2 = 0 (Q2 just cuts off);
(d) The dc voltage at the gates of Q7 , Q4 , and Q5 is −0.8 V. (d) iD1 = 0.04 mA and iD2 = 0.12 mA; (e) iD1 = 0 mA (Q1 just
cuts off) and iD2 = 0.16 mA. For each case, find vS , vD1 , vD2 ,
The technology available is specified
  μ
as follows:  n Cox = and vO .
2.5 μp Cox = 250 µA/V ; Vtn = Vtp  = 0.5 V, VAn = VAp  = 10 V.
2

Specify the required value of R and the W/L ratios for 8.11 For the differential amplifier specified in Prob-
all transistors. Also specify ID and VGS  at which each lem 8.2, let vG2 = 0 and vG1 = vid . Find the range of vid needed
 632 Chapter 8 Differential and Multistage Amplifiers
PROBLEMS

to steer the bias current from one side of the pair to the other. D 8.18 Design a MOS differential amplifier to operate from
At each end of this range, give the value of the voltage at the ±1-V power supplies and dissipate no more than 1 mW in
common-source terminal, the drain voltages, and vO . the equilibrium state. The differential voltage gain Ad is to
be 10 V/V and the output common-mode dc voltage is to be
8.12 Consider the differential amplifier specified in Prob-
0.2 V. (Note: This is the dc voltage at the drains.) Assume
lem 8.1 with G2 grounded and vG1 = vid . Let vid be adjusted 2
μn Cox = 400 µA/V and neglect the Early effect. Specify I,
to the value that causes iD1 = 0.09 mA and iD2 = 0.07 mA.
RD , and W/L.
CHAPTER 8

Find the corresponding values of vGS2 , vS , vGS1 , and hence vid .

What is the difference output voltage vO ? What is the voltage
8.19 An NMOS differential amplifier with equal drain
gain vO /vid ? What value of vid results in iD1 = 0.07 mA and
resistors, RD = 47 k, has a differential gain Ad of
iD2 = 0.09 mA?
20 V/V.
8.13 The table providing the answers to Exercise 8.3 shows
that as the maximum input signal to be applied to the (a) What is the value of gm for each of the two transistors?
differential pair is increased, linearity is maintained at the (b) If each of the two transistors is operating at an overdrive
  voltage VOV = 0.2 V, what must the value of I be?
same level by operating at a higher VOV . If vid max is to be
220 mV, use the data in the table to determine the required (c) For vid = 0, what is the dc voltage across each RD ?
VOV and the corresponding values of W/L and gm . (d) If vid is 20-mV peak-to-peak sine wave applied in a
balanced manner but superimposed on VCM = 0.5 V,
8.14 Use Eq. (8.23) to show that if the term involving vid
2
what is the peak of the sine-wave signal at each
is to be kept to a maximum value of k then the maximum drain?
possible fractional change in the transistor current is given (e) What is the lowest value that VDD must have to ensure
by saturation-mode operation for Q1 and Q2 at all times?
Imax  Assume Vt = 0.5 V.
= 2 k(1 − k)
I/2
and the corresponding maximum value of vid is given by 8.20 A MOS differential amplifier is designed to have a
differential gain Ad equal to the voltage gain obtained from
√
vidmax = 2 kVOV a common-source amplifier. Both amplifiers utilize the same
values of RD and supply voltages, and all the transistors have
Evaluate both expressions for k = 0.01, 0.1, and 0.2. the same W/L ratios. What must the bias current I of the
differential pair be relative to the bias current ID of the CS
8.15 A MOS differential amplifier biased with a current amplifier? What is the ratio of the power dissipation of the
source I = 200 µA is found to switch currents completely two circuits?
to one side of the pair when a difference signal vid = 0.3 V is
applied. At what overdrive voltage will each of Q1 and Q2 be
8.21 A differential amplifier is designed to have a dif-
operating when vid = 0? If vid for full current switching is to
ferential voltage gain equal to the voltage gain of a
be 0.5 V, what must the bias current I be changed to?
common-source amplifier. Both amplifiers use the same val-
*8.16 For the MOS differential pair in Fig. 8.5, specify the ues of RD and supply voltages and are designed to dissipate
value of vid ≡ vG1 − vG2 , in terms of VOV , that equal amounts of power in their equilibrium or quiescent
state. As well, all the transistors use the same channel length.
(a) causes iD1 to increase by 10% above its equilibrium value
What must the width W of the differential-pair transistors be
of I/2.
relative to the width of the CS transistor?
(b) makes iD1 /iD2 = 1.0; 2.0; 1.1; 1.01; 20.

8.17 An NMOS differential amplifier is operated at a D 8.22 Figure P8.22 shows a MOS differential amplifer
bias current I of 0.2 mA and has a W/L ratio of 32, with the drain resistors RD implemented using
2
μn Cox = 200 µA/V , VA = 10 V, and RD = 10 k. Find VOV , diode-connected PMOS transistors, Q3 and Q4 . Let Q1 and
gm , ro , and Ad . Q2 be matched, and Q3 and Q4 be matched.

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 633

VDD

CHAPTER 8
at the sources of Q1 and Q2 ? Express these in terms of
the overdrive voltage VOV at which each of Q1 and Q2
operates, and Vt .
(b) For the situation in (a), what current flows in Q3 ? What
Q3 Q4 overdrive voltage VOV3 is Q3 operating at, in terms of VC ,
VOV , and Vt ?
(c) Now consider the case vG1 = +vid /2 and vG2 = −vid /2,
 vod 

PROBLEMS
where vid is a small signal. Convince yourself that Q3
vid vid
Q1 Q2 now conducts current and operates in the triode region
2 2
with a small vDS . What resistance rDS does it have,
expressed in terms of the overdrive voltage VOV3 at which
it is operating? This is the resistance Rs . Now if all three
transistors have the same W/L, express Rs in terms of VOV ,
I
VOV3 , and gm1,2 .
(d) Find VOV3 and hence VC that result in (i) Rs = 1/gm1,2 ; (ii)
Rs = 0.5/gm1,2 .
Figure P8.22 *8.24 The circuit of Fig. P8.24 shows an effective way of
implementing the resistance Rs needed for the circuit in
(a) Find the differential half-circuit and use it to derive Fig. P8.7. Here Rs is realized as the series equivalent of two
an expression for Ad in terms of gm1,2 , gm3,4 , ro1,2 , MOSFETs Q3 and Q4 that are operated in the triode region,
and ro3,4 . thus, Rs = rDS3 + rDS4 . Assume that Q1 and Q2 are matched
(b) Neglecting the effect of the output resistances ro , find Ad and operate in saturation at an overdrive voltage VOV that
in terms of μn , μp , (W/L)1,2 and (W/L)3,4 . corresponds to a drain bias current of I/2. Also, assume that
(c) If μn = 4μp and all four transistors have the same channel Q3 and Q4 are matched.
length, find (W1,2 /W3,4 ) that results in Ad = 10 V/V.
*8.23 The resistance Rs in the circuit of Fig. P8.7 can be VDD
implemented by using a MOSFET operated in the triode
region, as shown in Fig. P8.23. Here Q3 implements Rs , with RD RD
the value of Rs determined by the voltage VC at the gate of Q3 .
vod
VDD
Q1 Q2 vG2
RD RD vG1

vod
Q3 Q4
Q1 Q2 vG2
vG1 I I
– –
Q3 2 2

–VSS
I I
– VC –
2 2 Figure P8.24

– V SS
(a) With vG1 = vG2 = 0 V, what dc voltages appear at the
Figure P8.23 sources of Q1 and Q2 ? What current flows through Q3
and Q4 ? At what overdrive voltages are Q3 and Q4 oper-
(a) With vG1 = vG2 = 0 V, and assuming that Q1 and Q2 ating? Find an expression for rDS for each of Q3 and Q4
are operating in saturation, what dc voltages appear and hence for Rs in terms of (W/L)1,2 , (W/L)3,4 , and gm1,2 .
 634 Chapter 8 Differential and Multistage Amplifiers

(b) Now with vG1 = vid /2 and vG2 = − vid /2, where vid is leave the active mode at vCE ≤ 0.3 V. The collector resistors
PROBLEMS

a small signal, find an expression of the voltage gain RC = 82 k, and the power supplies are ±1.2 V. The bias
Ad ≡ vod /vid in terms of gm1,2 , RD , (W/L)1,2 , and (W/L)3,4 . current I = 20 µA and is supplied with a simple current
source.
*8.25 A design error has resulted in a gross mismatch in the
circuit of Fig. P8.25. Specifically, Q2 has twice the W/L ratio (a) For vB1 = vB2 = VCM = 0 V, find VE , VC1 , and VC2 .
of Q1 . If vid is a small sine-wave signal, find: (b) Find the input common-mode range.
CHAPTER 8

(c) If vB2 = 0, find the value of vB1 that increases the current
(a) ID1 and ID2 .
in Q1 by 10%.
(b) VOV for each of Q1 and Q2 .
(c) The differential gain Ad in terms of RD , I, and VOV .
D 8.28 Design the circuit of Fig. 8.14 to provide a differen-
tial output voltage vO of 1 V when the differential input signal
VDD is 10 mV. A current source of 1 mA and a positive supply
of +5 V are available. What is the largest possible input
common-mode voltage for the circuit to operate as required?
RD RD Assume α  1.

8.29 A BJT differential amplifier uses a 400-µA bias

vod current. What is the value of gm of each device? If β is 160,
what is the differential input resistance?
Q1 Q2
D 8.30 Design the basic BJT differential amplifier circuit
vid 2 WL 2W L
of Fig. 8.18 to provide a differential input resistance of at
least 20 k and a differential voltage gain of 100 V/V. The
transistor β is specified to be at least 100. Specify I and RC .
vid 2 8.31 For a differential amplifier to which a total difference
signal of 10 mV is applied, what is the equivalent signal to its
corresponding CE half-circuit? If the emitter current source I
is 200 µA, what is re of the half-circuit? For a load resistance
I
of 10 k in each collector, what is the half-circuit gain? What
magnitude of signal output voltage would you expect at each
collector? Between the two collectors?
VSS
D 8.32 Design a BJT differential amplifier to amplify a
Figure P8.25 differential input signal of 0.2 V and provide a differ-
ential output signal of 2 V. To ensure adequate linearity,
it is required to limit the signal amplitude across each
base–emitter junction to a maximum of 5 mV. Another
Section 8.2: The BJT Differential Pair design requirement is that the differential input resistance be
8.26 For the differential amplifier of Fig. 8.15(a) let at least 400 k. The BJTs available are specified to have β
I = 0.4 mA, VCC = VEE = 2.5 V, VCM = −1 V, RC = 5 k, and ≥ 100. Give the circuit configuration and specify the values
β = 100. Assume that the BJTs have vBE = 0.7 V at of all its components.
iC = 1 mA. Find the voltage at the emitters and at the outputs.
8.33 For each of the emitter-degenerated differential ampli-
8.27 An npn differential pair employs transistors for which fiers shown in Fig. P8.33, find the differential half-circuit and
vBE = 690 mV at iC = 1 mA, and β = 50. The transistors derive expressions for the differential gain Ad and differential

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 635

CHAPTER 8
input resistance Rid . For each circuit, what dc voltage appears 8.35 A particular differential amplifier operates from an
across the bias current source(s) in the quiescent state (i.e., emitter current source I = 0.4 mA. Each of the collector
with vid = 0)? Hence, which of the two circuits will allow a resistances RC = 20 k and a load resistance RL = 40 k
larger negative VCM ? is connected between the two collectors. If the amplifier is
fed in the manner shown in Fig. P8.52 with Rsig = 100 k,
VCC
find the overall voltage gain. Let β = 100.

8.36 Find the voltage gain and input resistance of the

PROBLEMS
RC RC
amplifier in Fig. P8.36 assuming that β = 100.

vod
5V

vid vid
VCM VCM 25 k
2 2
vo

vi
Re Re 500

I Rin 0.1 mA 0.1 mA

VEE
(a) Figure P8.36

VCC
8.37 An npn differential amplifier with I = 0.4 mA, VCC =
RC RC VEE = 2.5 V, and RC = 5 k utilizes BJTs with β = 100 and
vBE = 0.7 V at iC = 1 mA. If vB2 = 0, find VE , VC1 , and VC2
vod obtained with vB1 = +0.5 V, and with vB1 = −0.5 V. Assume
that the current source requires a minimum of 0.3 V for
proper operation.

vid vid 8.38 An npn differential amplifier with I = 0.4 mA, VCC =
VCM VCM
2 2 Re 2 VEE = 2.5 V, and RC = 5 k utilizes BJTs with β = 100 and
vBE = 0.7 V at iC = 1 mA. Assuming that the bias current is
obtained by a simple current source and that all transistors
require a minimum vCE of 0.3 V for operation in the active
I I mode, find the input common-mode range.
– –
2 2
8.39 Repeat Exercise 8.7 for an input of –0.3 V.

VEE 8.40 Consider the BJT differential amplifier when fed with
a common-mode voltage VCM as shown in Fig. 8.15(a). As is
(b) often the case, the supply voltage VCC may not be pure dc
Figure P8.33 but might include a ripple component vr of small amplitude
and a frequency of 120 Hz (see Section 3.6). Thus the supply
8.34 Consider a bipolar differential amplifier that, in addi- voltage becomes VCC + vr . Find the ripple component of the
tion to the collector resistances RC , has a load resistance collector voltages, vC1 and vC2 , as well as of the difference
RL connected between the two collectors. What does the output voltage vod ≡ vC2 − vC1 . Comment on the differential
differential gain Ad become? amplifier response to this undesirable power-supply ripple.
 636 Chapter 8 Differential and Multistage Amplifiers
PROBLEMS

D 8.41 Consider the differential amplifier of Fig. 8.14 and (b) With no emitter resistances Re , use the large-signal
let the BJT β be very large: model to find iC1 and iC2 when vid = 20 mV.
(c) Now find the value of Re that will result in the same
(a) What is the largest input common-mode signal that can
iC1 and iC2 as in (b) but with vid = 200 mV. Use the
be applied while the BJTs remain comfortably in the
large-signal model.
active region with vCB = 0?
(d) Calculate the effective transconductance Gm as the ratio
(b) If the available power supply VCC is 2.0 V, what value of
of the difference current, (iC1 − iC2 ), to vid in the cases
CHAPTER 8

IRC should you choose in order to allow a common-mode

without and with the Re ’s. By what factor is Gm reduced?
input signal of ±1.0 V?
How does this factor relate to the increase in vid ?
(c) For the value of IRC found in (b), select values for I and
Comment.
RC . Use the largest possible value for I subject to the
constraint that the base current of each transistor (when I 8.46 A BJT differential amplifier is biased from a 0.5-mA
divides equally) should not exceed 2 µA. Let β = 100. constant-current source and includes a 400- resistor in
each emitter. The collectors are connected to VCC via 10-k
8.42 To gain insight into the possibility of nonlinear
resistors. A differential input signal of 0.2 V is applied
distortion resulting from large differential input signals
between the two bases.
applied to the differential amplifier of Fig. 8.14, evaluate the
 
normalized change in the current iE1 ,  iE1 /I = iE1 − (I/2) /I, (a) Find the signal current in the emitters (ie ) and the signal
for differential input signals vid of 2, 5, 8, 10, 20, 30, and voltage vbe for each BJT.
 
40 mV. Use a table to show the ratio iE1 /I /vid , which (b) What is the total emitter current in each BJT?
represents the proportional transconductance gain of the (c) What is the signal voltage at each collector? Assume
differential pair, versus vid . Comment on the linearity of the α = 1.
differential pair as an amplifier. (d) What is the voltage gain realized when the output is
taken between the two collectors?
*8.43 For the circuit in Fig. 8.14, assuming α = 1 and
IRC = 5 V, use Eqs. (8.48) and (8.49) to find iC1 and iC2 , and D 8.47 Design a bipolar differential amplifier such as that
hence determine vod = vC2 − vC1 for input differential signals in Fig. 8.18 to operate from ±2.5 V power supplies and to
vid ≡ vB1 − vB2 of 2 mV, 5 mV, 10 mV, 15 mV, 20 mV, provide differential gain of 60 V/V. The power dissipation in
25 mV, 30 mV, 35 mV, and 40 mV. Plot vod versus vid , and the quiescent state should not exceed 1 mW.
hence comment on the amplifier linearity. As another way of
  (a) Specify the values of I and RC . What dc voltage appears
visualizing linearity, determine the gain vo /vid versus vid . at the collectors?
Comment on the resulting graph. (b) If β = 100, what is the input differential resistance?
(c) For vid = 10 mV, what is the signal voltage at each of the
8.44 In a differential amplifier using a 1.5-mA emitter bias
collectors?
current source, the two BJTs are not matched. Rather, one has
(d) For the situation in (c), what is the maximum allowable
twice the emitter junction area of the other. For a differential
value of the input common-mode voltage, VCM ? Recall
input signal of zero volts, what do the collector currents
that to maintain an npn BJT in saturation, vB should not
become? What difference input is needed to equalize the
exceed vC by more than 0.4 V.
collector currents? Assume α = 1.
D *8.48 In this problem we explore the trade-off between
*8.45 This problem explores the linearization of the transfer
input common-mode range and differential gain in the design
characteristics of the differential pair achieved by including
of the bipolar differential BJT amplifier. Consider the bipolar
emitter-degeneration resistances Re in the emitters (see
differential amplifier in Fig. 8.14 with the input voltages
Fig. 8.17). Consider the case I = 200 µA with the transistors
 
exhibiting vBE = 690 mV at iC = 1 mA and assume α  1. vB1 = VCM + vid /2
 
(a) With no emitter resistances Re , what value of VBE results vB2 = VCM − vid /2
when vid = 0?

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 637

Rsig 2

CHAPTER 8
(a) Bearing in mind that for a BJT to remain in the active
mode, vBC should not exceed 0.4 V, show that when
vid has a peak v̂id , the maximum input common-mode
vsig
voltage VCMmax is given by –
2
 
v̂id v̂
VCMmax = VCC + 0.4 − − Ad VT + id vid
2 2

PROBLEMS
VCM

(b) For the case VCC = 2.5 V and v̂id = 10 mV, use the vsig
–
relationship above to determine VCMmax for the case Ad = 2
50 V/V. Also find the peak output signal v̂od and the
required value of IRC . Now if the power dissipation in
the circuit is to be limited to 1 mW in the quiescent Rsig 2
state (i.e., with vid = 0), find I and RC . (Remember to
include the power drawn from the negative power supply Figure P8.52
−VEE = −2.5 V.)
(c) If VCMmax is to be +1 V, and all other conditions remain
the same, what maximum gain Ad is achievable? 8.53 Find the voltage gain and the input resistance of the
amplifier shown in Fig. P8.53 assuming β = 100.
8.49 For the differential amplifier of Fig. 8.14, let VCC =
+5 V and IRC = 4 V. Find the differential gain Ad . Sketch and
clearly label the waveforms for the total collector voltages 3V
vC1 and vC2 and for (vO ) for the case:
20 k
vB1 = 1 + 0.005 sin(ωt)
vo
vB2 = 1 − 0.005 sin(ωt)
8.50 Consider a bipolar differential amplifier in which vi Q1 Q2
the collector resistors RC are replaced with simple current
sources implemented using pnp transistors. Sketch the circuit
and give its differential half-circuit. If VA = 20 V for all 250 250
Rin
transistors, find the differential voltage gain achieved. 0.2 mA
8.51 A bipolar differential amplifier having resistance Re
inserted in series with each emitter [as in Fig. P8.33(a)] is
biased with a constant current I. When both input terminals Figure P8.53
are grounded, the dc voltage measured across each Re is
found to be 3 VT and that measured across each RC is found
to be 80VT . What differential voltage gain Ad do you expect
8.54 Derive an expression for the small-signal voltage gain
the amplifier to have?
vo /vi of the circuit shown in Fig. P8.54 in two different ways:
8.52 A bipolar differential amplifier with emitter-
(a) as a differential amplifier
degeneration resistances Re and Re is fed with the
(b) as a cascade of a common-collector stage Q1 and a
arrangement shown in Fig. P8.52. Derive an expression for
common-base stage Q2
the overall differential voltage gain Gv ≡ vod /vsig . If Rsig is of
such a value that vid = 0.5vsig , find the gain Gv in terms of Assume that the BJTs are matched and have a current gain
RC , re , Re , and α. Now if β is doubled, by what factor does Gv α, and neglect the Early effect. Verify that both approaches
increase? lead to the same result.
 638 Chapter 8 Differential and Multistage Amplifiers
PROBLEMS
CHAPTER 8

Figure P8.54 Figure P8.57

8.58 Consider the basic differential circuit in which the

transistors have β = 100 and VA = 100 V, with I = 0.2 mA,
Section 8.3: Common-Mode Rejection REE = 500 k, and RC = 25 k. The collector resistances are
8.55 An NMOS differential pair is biased by a current matched to within 1%. Find:
source I = 0.2 mA having an output resistance RSS = 100 k. (a) the differential gain
The amplifier has drain resistances RD = 12 k, using (b) the differential input resistance
 2
transistors with kn W/L = 5 mA/V , and ro that is large. (c) the common-mode gain
If the output is taken differentially and there is a 1% (d) the common-mode rejection ratio
mismatch between the drain resistances, find Ad , Acm , (e) the common-mode input resistance
and CMRR.
8.59 For the differential amplifier shown in Fig. P8.59,
D 8.56 It is required to design a MOS differential amplifier identify and sketch the differential half-circuit and the
to have a CMRR of 80 dB. The only source of mismatch common-mode half-circuit. Find the differential gain, the dif-
in the circuit is a 2% difference between the W/L ratios ferential input resistance, the common-mode gain assuming
of the two transistors. Let I = 100 µA and assume that all the resistances RC have 1% tolerance, and the common-mode
transistors are operated at VOV = 0.2 V. For the 0.18-µm input resistance. For these transistors, β = 100 and

CMOS fabrication process available, VA = 5 V/µm. What is VA = 100 V.
the value of L required for the current-source transistor? 10 V

8.57 The differential amplifier circuit of Fig. P8.57 utilizes

RC RC
a resistor connected to the negative power supply to establish 10 k vod 10 k
the bias current I.
RL
(a) For vB1 = vid /2 and vB2 = −vid /2, where vid is a small
20 k
signal with zero average,  find the magnitude of the Q1 Q2
differential gain, vo /vid . RE
(b) For vB1 = vB2 = vicm , where vicm has a zeroaverage,
 find 300
the magnitude of the common-mode gain, vo /vicm . 200 200
(c) Calculate the CMRR. k k
0.5 mA 0.5 mA
(d) If vB1 = 0.1 sin 2π × 60t + 0.005 sin 2π × 1000t, volts,
and vB2 = 0.1 sin 2π × 60t − 0.005 sin 2π × 1000t, volts,
find vo . Figure P8.59

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 639

CHAPTER 8
8.60 For the differential amplifier shown in Fig. P8.2, let Q1 Note that this equation indicates that RD can be deliberately
 2
and Q2 have kp (W/L) = 4 mA/V , and assume that the bias  varied to compensate for the initial variability in gm and RD ,
current  
 has an output resistance of 30 k. Find VOV ,
 source that is, to minimize Acm .
gm , Ad , Acm , and the CMRR (in dB) obtained with the In a MOS differential amplifier for which RD = 5 k and
output taken differentially. The drain resistances are known RSS = 25 k, the common-mode gain is measured and found
to have a mismatch of 2%. to be 0.002 V/V. Find the percentage change required in one
of the two drain resistors so as to reduce Acm to zero (or close
D *8.61 The differential amplifier in Fig. P8.61 uti-

PROBLEMS
to zero).
lizes a resistor RSS to establish a 0.02-mA dc bias current.
Note that this amplifier uses a single 2-V supply and thus the D 8.63 A MOS differential amplifier utilizing a simple
dc common-mode voltage VCM cannot be zero. Transistors Q1 current source to provide the bias current I has a CMRR of
 2
and Q2 have kn W/L = 1 mA/V , Vt = 0.4 V, and λ = 0. 60 dB. If the CMRR must be raised to 100 dB by adding
a cascode transistor to the current source, what must the
(a) Find the required value of VCM .
intrinsic gain A0 of the cascode transistor be? If the cascode
(b) Find the value of RD that results in a differential gain Ad
transistor is operated at VOV = 0.2 V, what must its VA be? If
of 15 V/V. 
for the specific technology utilized VA = 5 V/µm, specify the
(c) Determine the dc voltage at the drains.
channel length L of the cascode transistor.
(d) Determine the single-ended-output common-mode gain
VD1 /VCM . (Hint: You need to take 1/gm into account.) 8.64 In a bipolar differential-amplifier circuit, the bias cur-
(e) Use the common-mode gain found in (d) to find the rent generator consists of a simple common-emitter transistor
change in VCM that results in Q1 and Q2 entering the triode operating at 200 µA. For this transistor, and those used in the
region. differential pair, VA = 20 V and β = 50. What common-mode
input resistance would result? Assume RC ro .

VDD 2V 8.65 A bipolar differential amplifier with I = 0.2 mA

utilizes transistors for which VA = 20 V and β = 100. The
collector resistances RC = 10 k and are matched to within
RD RD 10%. Find:

(a) the differential gain

vod (b) the common-mode gain and the CMRR if the bias current
I is generated using a simple current mirror
Q1 Q2 (c) the common-mode gain and the CMRR if the bias current
I is generated using a Wilson mirror. (Refer to Eq. 8.98
vid for Ro of the Wilson mirror.)

D 8.66 Design a differential amplifier to provide the largest

possible signal to a pair of 10-k load resistances. The input
differential signal is a sinusoid of 5-mV peak amplitude,
VCM 0.02 mA RSS 20 k
which is applied to one input terminal while the other input
terminal is grounded. The power supply VCC available is 5 V.
To determine the required bias current I, derive an expression
Figure P8.61 for the total voltage at each of the collectors in terms of VCC
and I in the presence of the input signal. Then impose the
condition that both transistors remain well out of saturation
8.62 It can be shown that if the drain resistors of a with a minimum vCB of roughly 0 V. Thus determine the
MOS differential amplifier have a mismatch RD and if required value of I. For this design, what differential gain
simultaneously the transconductances of Q1 and Q2 have a is achieved? What is the amplitude of the signal voltage
mismatch gm , the common-mode gain is given by obtained between the two collectors? Assume α 1.
  
RD gm RD D *8.67 Design a BJT differential amplifier that provides
Acm  + two single-ended outputs (at the collectors). The amplifier is
2RSS gm RD
 640 Chapter 8 Differential and Multistage Amplifiers

of Vt of ±5 mV, and of W/L and RD (independently) of

PROBLEMS

to have a differential gain (to each of the two outputs) of at

least 100 V/V, a differential input resistance ≥ 10 k, and a ±1%. What is the worst-case input offset voltage you would
common-mode gain (to each of the two outputs) no greater expect to find? What is the major contribution to this total
than 0.1 V/V. Use a 2-mA current source for biasing. Give offset? If you used a variation of one of the drain resistors
the complete circuit with component values and suitable to reduce the output offset to zero and thereby compensate
power supplies that allow for ±2 V swing at each collector for the uncertainties (including that of the other RD ), what
and an input common-mode voltage as high as +3 V. Specify percentage change from nominal would you require?
CHAPTER 8

the minimum value that the output resistance of the bias

8.72 A bipolar differential amplifier uses two well-matched
current source must have. If the current source is realized
transistors, but collector load resistors that are mismatched
by a simple mirror, what must the minimum value of VA be?
by 10%. What input offset voltage is required to reduce the
The BJTs available have β ≥ 100. What is the value of the
differential output voltage to zero?
input common-mode resistance when the bias source has the
lowest acceptable output resistance? 8.73 A bipolar differential amplifier uses two transistors
whose scale currents IS differ by 10%. If the two collector
8.68 When the output of a BJT differential amplifier is taken
resistors are well matched, find the resulting input offset
differentially, its CMRR is found to be 46 dB higher than
voltage.
when the output is taken single-endedly. If the only source of
common-mode gain when the output is taken differentially 8.74 Modify Eq. (8.101) for a differential amplifier having a
is the mismatch in collector resistances, what must this resistance RE connected in the emitter of each transistor. Let
mismatch be (in percent)? the bias current source be I.

*8.69 In a particular BJT differential amplifier, a production 8.75 One approach to “offset correction” involves the
error results in one of the transistors having an emitter–base adjustment of the values of RC1 and RC2 so as to reduce the
junction area that is twice that of the other. With the inputs differential output voltage to zero when both input terminals
grounded, how will the emitter bias current split between the are grounded. This offset-nulling process can be accom-
two transistors? If the output resistance of the current source plished by utilizing a potentiometer in the collector circuit,
is 400 k and the resistance in each collector (RC ) is 15 k, as shown in Fig. P8.75. We wish to find the potentiometer
find the common-mode gain obtained when the output is setting, represented by the fraction x of its value connected in
taken differentially. Assume α  1. (Hint: The CM signal series with RC1 , that is required for nulling the output offset
current vicm /REE will split between Q1 and Q2 in the same voltage that results from:
ratio as the bias current I does.) VCC

(x) (1 x)
Section 8.4: DC Offset
1k
D 8.70 An NMOS differential amplifier for which the RC1 RC2
MOSFETs have a transconductance parameter kn and whose 5k 5k
drain resistances RD have a mismatch RD is biased with a
current I.
Q1 Q2
(a) Find expressions for Ad and VOS in terms of kn , RD ,
RD /RD , and I. Use these expressions to relate VOS and
Ad .
2
(b) If kn = 4 mA/V , RD = 10 k, and RD /RD = 0.02, find
1 mA
the maximum gain realized if VOS is to be limited to 1
mV, 2 mV, 3 mV, 4 mV, and 5 mV. For each case, give
the value of the required bias current I. Note the trade-off
Figure P8.75
between gain and offset voltage.

D 8.71 An NMOS amplifier, whose designed operating (a) RC1 being 4% higher than nominal and RC2 4% lower than
point is at VOV = 0.3 V, is suspected to have a variability nominal

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 641

CHAPTER 8
(b) Q1 having an area 5% larger than nominal, while Q2 has find the input voltage that would restore current balance to
area 5% smaller than nominal. the differential pair. Repeat using large-signal analysis and
compare results.
8.76 A differential amplifier for which the total emitter bias
current is 400 µA uses transistors for which β is specified D 8.84 A large fraction of mass-produced differential-
to lie between 80 and 200. What is the largest possible input amplifier modules using 20-k collector resistors is found
bias current? The smallest possible input bias current? The to have an input offset voltage ranging from +2 mV to
largest possible input offset current? –2 mV. By what amount must one collector resistor be

PROBLEMS
adjusted to reduce the input offset to zero? If an adjustment
D 8.77 An NMOS differential pair is to be used in an
mechanism is devised that raises one collector resistance
amplifier whose drain resistors are 10 k ± 1%. For the pair,
 2 while correspondingly lowering the other, what resistance
kn W/L = 4 mA/V . Decide whether to use a bias current I of
change is needed? If a potentiometer connected as shown
160 µA or 360 µA. Contrast the differential gain and input
in Fig. P8.75 is used, what value of potentiometer resistance
offset voltage for the two possibilities.
(specified to 1 significant digit) is needed? Assume that the
8.78 An NMOS differential pair operating at a bias current offset is entirely due to the finite tolerance of RC .
 2
I of 100 µA uses transistors for which kn = 200 µA/V and
W/L = 10. Find the three components of input offset voltage Section 8.5: The Differential Amplifier with
under the conditions that RD /RD = 4%, (W/L)/(W/L) = a Current-Mirror Load
4%, and Vt = 5 mV. In the worst case, what might the
total offset be? For the usual case of the three effects being 8.85 A current-mirror-loaded NMOS differential amplifier

independent, what is the offset likely to be? is fabricated in a technology for which |VA | = 5 V/µm.
All the transistors have L = 0.5 µm. If the differential-pair
8.79 A differential amplifier uses two transistors whose β transistors are operated at VOV = 0.25 V, what open-circuit
values are β 1 and β 2 . If everything else is matched, show that
    differential gain is realized?
the input offset voltage is approximately VT 1/β1 − 1/β2 .
Evaluate VOS for β 1 = 50 and β 2 = 100. (Hint: The bias 8.86 The differential amplifier of Fig. 8.31(a) is biased with
current I will still split equally between the two emitters.) I = 200 µA. All transistors have L = 0.5 µm, and Q1 and
Q2 have W/L = 20. The circuit is fabricated in a process for
8.80 Two possible differential amplifier designs are consid- 2 
which μn Cox = 400 µA/V and |VA | = 6 V/µm. Find gm1,2 ,
ered, one using BJTs and the other MOSFETs. In both cases, ro2 , ro4 , and Ad .
the collector (drain) resistors are maintained within ±2% of
nominal value. The MOSFETs are operated at VOV = 200 D 8.87 In a current-mirror-loaded differential amplifier of
mV. What input offset voltage results in each case? What the form shown in Fig. 8.31(a), all  transistors
 are charac-
terized by k W/L = 4 mA/V , and VA  = 5 V. Find the bias
 2
does the MOS VOS become if the devices are increased in
width by a factor of 4 while the bias current is kept constant? current I for which the gain vo /vid = 20 V/V.

*8.81 A differential amplifier uses two transistors having VA 8.88 A current-mirror-loaded NMOS differential amplifier
values of 100 V and 200 V. If everything else is matched, operates with a bias current I of 200 µA. The NMOS tran-
find the resulting input offset voltage. Assume that the two   are operated at VOV = 0.2 V and the PMOS devices at
sistors
transistors are intended to be biased at a VCE of about 10 V. VOV  = 0.3 V. The Early voltages are 20 V for the NMOS and
12 V for the PMOS transistors. Find Gm , Ro , and Ad . For what
**8.82 A differential amplifier is fed in a balanced or
value of load resistance is the gain reduced by a factor of 2?
push–pull manner, and the source resistance in series with
each base is Rs . Show that a mismatch Rs between the 8.89 The differential amplifier in Fig. 8.35(a) is operated
values of the two source resistances gives rise to an input with I = 500 µA, with devices for which VA = 10 V and
offset voltage of approximately (I/2β)Rs / [1 + (gm Rs )/β]. β = 100. What differential input resistance, output resistance,
short-circuit transconductance, and open-circuit voltage gain
*8.83 In a particular BJT differential amplifier, a production
would you expect? What will the voltage gain be if the input
error results in one of the transistors having an emitter–base
resistance of the subsequent stage is equal to Rid of this stage?
junction area twice that of the other. With both inputs
grounded, find the current in each of the two transistors and 8.90 Figure P8.90 shows a differential cascode amplifier
hence the dc offset voltage at the output, assuming that the with an active load formed by a Wilson current mirror.
collector resistances are equal. Use small-signal analysis to Utilizing the expressions derived in Chapter 7 for the output
 642 Chapter 8 Differential and Multistage Amplifiers
PROBLEMS

resistance of a bipolar cascode and the output resistance (d) If I is delivered by a simple NMOS current source
of the Wilson mirror, and assuming all transistors to be operated at the same VOV and having the same channel
identical, show that the differential voltage gain Ad is given length as the other four transistors, determine the CMRR
approximately by obtained.
1
Ad = βgm ro 8.92 The MOS differential amplifier of Fig. 8.31(a) is
3
biased with a simple current mirror delivering I = 200 µA.
Evaluate Ad for the case of β = 100 and VA = 20 V.
CHAPTER 8

All transistors are operated at VOV = 0.2 V and have VA = 6 V.

Find Gmd , Ro , Ad , RSS , Rim , Am , Gmcm , Acm , and CMRR.
VCC 5
8.93 The differential amplifier of Fig. 8.31(a) is measured
and found to have a short-circuit transconductance of 2
mA/V. A differential input signal is applied and the output
voltage is measured with a load resistance RL connected. It
Q5 Q6 is found that when RL is reduced from ∞ to 20 k, the
magnitude of the output signal is reduced by half. What do
you estimate Ro and Ad (with RL disconnected) to be?
Q7 D 8.94 Consider a current-mirror-loaded differential ampli-
fier such as that shown in Fig. 8.31(a) with the bias current
vo source implemented with the modified Wilson mirror  of
Fig. P8.94 with I = 200 µA. The transistors have Vt  = 0.5V
 2
Q3 Q4 and k W/L = 5 mA/V . What is the lowest value of the
  (V DD +
total power supply  VSS ) that allows each transistor to
VBIAS operate with VDS  ≥ VGS ?

Q1 Q2

vd
I
I

RSS
I

Q8 Q7
VEE 5V

Figure P8.90

Q5 Q6
D 8.91 Design the current-mirror-loaded differential
MOS amplifier of Fig. 8.31(a) to obtain a differential gain
of 60 V/V. The technology available provides μn Cox =
2   
4μp Cox = 500 µA/V , Vt  = 0.4 V, and VA  = 15 V/µm and
operates from ±0.8-V supplies. Use a bias current I = 200
Figure P8.94
µA and operate all devices at VOV  = 0.15 V. Assume all
transistors have the same channel length.

(a) Find the W/L ratios of the four transistors. *8.95 (a) Sketch the circuit of a current-mirror-loaded MOS
(b) Specify the channel length required of all transistors. differential amplifier in which the input transistors are
(c) If VICM = 0, what is the allowable range of vO ? cascoded and a cascode current mirror is used for the load.

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 643

CHAPTER 8
vg3 vid 4
ro Q3 Q4 ro

i13 i12 i2 i1
1
vo (g r ) v
2 m o id

PROBLEMS
i11 i3

i9 i6 i4

(vid 2) Q1 ro ro Q2 (vid 2)

i8 i10 i7 i5

vs vid 4

Figure P8.96

(b) Show that if all transistors are operated at an overdrive given by
voltage VOV and have equal Early voltages VA , the gain is   (W/L)A
VOS1 = VOV /2
given by (W/L)A
 2 where VOV is the overdrive voltage at which Q1 and Q2 are
Ad = 2 VA /VOV operating.
(b) Repeat for a mismatch (W/L)M in the W/L ratios of the
Evaluate the gain for VOV = 0.20 V and VA = 10 V.
mirror transistor Q3 and Q4 to show that the corresponding
8.96 Figure P8.96 shows the current-mirror-loaded MOS VOS is given by
differential amplifier prepared for small-signal analysis. We   (W/L)M
have pulled ro out of each transistor; thus, the current in VOS2 = VOV /2
(W/L)M
the drain of each transistor will be gm vgs . We have also
simplified matters by indicating approximate values for where VOV is the overdrive voltage at which Q1 and Q2 are
some of the node voltages. For instance, the output voltage operating.
 
vo = 12 gm ro vid , which we have derived in the text. The (c)
 For a circuit in which all transistors are operated at
voltage at the common sources has been found to be roughly VOV  = 0.2 V and all W/L ratios are accurate to within ±1%
+vid /4, which is very far from the virtual ground we might of nominal, find the worst-case total offset voltage VOS .
expect. Also, the voltage at the drain of Q1 is approximately
D 8.98 Consider the bias design of the Wilson-loaded
−vid /4, confirming our contention that the voltage there is
cascode differential amplifier shown in Fig. P8.90.
vastly different from the output voltage, hence the lack of
balance in the circuit and the unavailability of a differential (a) What is the largest signal voltage possible at the output
half-circuit. Find the currents labeled i1 to i13 in terms of without Q7 saturating? Assume that the CB junction
(gm vid ). Determine their values in the sequence of their conducts when the voltage across it exceeds 0.4 V.
numbering and assume gm r o  1. Assume that all transistors (b) What should the dc bias voltage established at the output
are operating at the same VOV . Write the current values on (by an arrangement not shown) be in order to allow for
the circuit diagram and reflect on the results. positive output signal swing of 1.5 V?
(c) What should the value of VBIAS be in order to allow for a
8.97 This problem investigates the effect of transis-
negative output signal swing of 1.5 V?
tor mismatches on the input offset voltage of the
(d) What is the upper limit on the input common-mode
current-mirror-loaded MOS differential amplifier of
voltage VICM ?
Fig. 8.31(a). For this purpose, ground both input terminals
and short-circuit the output node to ground. 8.99 In addition to the random offset voltages that result
(a) If the amplifying transistors Q1 and Q2 exhibit a W/L from the mismatches inevitably present in the differen-
mismatch of (W/L)A , find the resulting short-circuit output tial amplifier, the current-mirror-loaded bipolar differential
current and hence show that the corresponding VOS is amplifier suffers from a systematic offset voltage. This is due
 644 Chapter 8 Differential and Multistage Amplifiers
PROBLEMS

to the error in the current transfer ratio of the current-mirror 8.101 Consider the current-mirror-loaded MOS differential
load caused by the finite β of the pnp transistors that make amplifier of Fig. 8.31(a) in two cases:
up the mirror. The situation is illustrated in Fig. P8.99. Show
(a) Current source I is implemented with a simple current
that the resulting input offset voltage is given by
mirror.
VOS = −2VT /βP (b) Current source I is implemented with the modified
Wilson current mirror shown in Fig. P8.101.

CHAPTER 8

and evaluate VOS for βP = 50. Also, if the simple current Recalling that for the simple mirror RSS = ro Q and for
S
mirror is replaced by the pnp version of the Wilson mirror the Wilson mirror RSS  gm7 ro7 ro5 , and assuming that all
transistors have the same VA  and k W/L, show that for
of Fig. 8.37(a), find the expected systematic input offset 

voltage. Give both an expression and a value. (a)

 2
VCC VA
CMRR = 2
VOV
Q3 Q4 and for (b)
aI 2  3
2 √ VA
1 b CMRR = 2 2
P
VOV
aI 2 aI 2 i
where VOV is the overdrive voltage that corresponds to a
 2
  current of I/2. For k W/L = 4 mA/ V , I = 160 µA, and
Q1 Q2 drain
I 2 I 2
VA  = 5 V, find CMRR for both cases.

I
I
Figure P8.99 RSS

8.100 For the BiCMOS differential amplifier in Fig. P8.100 Q8 Q7

2  

let VDD = VSS = 3 V, I = 0.2 mA, kp W/L  
 = 6.4 mA/V ; VA
for p-channel MOSFETs is 10 V, VA  for npn transistors is
30 V. Find Gmd , Ro , and Ad .
Q5 Q6
V

Q Q
Figure P8.101
v

8.102 A current-mirror-loaded MOS differential amplifier

Q Q
is found to have a differential voltage gain Ad of 30 V/V.
Its bias current source has an output resistance RSS = 100 k.
The current mirror utilized has a current gain Am of 0.98 A/A,
an input resistance Rim of 1.63 k, and an output resistance
V
Rom of 75 k. If the output resistances of the amplifier Rod is
Figure P8.100 50 k, find Gmcm , Acm , and CMRR.

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 645

VDD 0.9 V

CHAPTER 8
Q3 Q4
IREF 200 A
Q6

PROBLEMS
A
Q1 Q2 B vo

Q5
Q8 Q7

VSS 0.9 V

Figure P8.104

D 8.103 A current-mirror-loaded MOS differential ampli- 8.105 Consider the amplifier of Fig. 8.37, whose parameters
fier has a differential voltage gain Ad of 40 V/V. The output are specified in Example 8.6. If a manufacturing error results
resistance of the current-mirror load is equal to the output in the W/L ratio of Q7 being 24/0.4, find the current that Q7
resistance of the amplifier at 40 k. If the current-mirror gain will now conduct. Thus find the systematic offset voltage that
is 0.98 A/A and its input resistance Rim is 500 , find the will appear at the output. (Use the results of Example 8.6.)
required value of the output resistance RSS of the bias current Assuming that the open-loop gain will remain approximately
source to obtain a CMRR of 80 dB. unchanged from the value found in Example 8.6, find the
corresponding value of input offset voltage, VOS .
Section 8.6: Multistage Amplifiers
D 8.104 The two-stage CMOS op amp in Fig. P8.104 is *8.106 Figure P8.106 shows a bipolar op-amp circuit that
  resembles the CMOS op amp of Fig. 8.37. Here, the
fabricated in a 0.18-µm technology having kn = 4kp =
2
400 µA/V , Vtn = −Vtp = 0.4 V. input differential pair Q1 –Q2 is loaded in a current mir-
ror formed by Q3 and Q4 . The second stage is formed
(a) With A and B grounded, perform a dc design that will by the current-source-loaded common-emitter transistor
result in each of Q1 , Q2 , Q3 , and Q4 conducting a drain Q5 . Unlike the CMOS circuit, here there is an output
current of 100 µA and each of Q6 and Q7 a current of stage formed by the emitter follower Q6 . The func-
200 µA. Design so that all transistors operate at 0.2-V tion of capacitor CC will be explained  later,
 in Chap-
overdrive voltages. Specify the W/L ratio required for ter 11. All transistors have β = 100, VBE  = 0.7 V, and
each MOSFET. Present your results in tabular form. ro = ∞.
What is the dc voltage at the output (ideally)?
(b) Find the input common-mode range. (a) For inputs grounded and output held at 0 V (by negative
(c) Find the allowable range of the output voltage. feedback, not shown) find the emitter currents of all
(d) With vA = vid /2 and vB = −vid /2, find the voltage gain transistors.
vo /vid . Assume an Early voltage of 6 V. (b) Calculate the gain of the amplifier with RL = 1 k.
 646 Chapter 8 Differential and Multistage Amplifiers

5V
PROBLEMS

0.4 mA

0.5 mA

Q6
CHAPTER 8

Q1 Q2 CC
vo

Q5
1 mA RL

Q3 Q4

5V

Figure P8.106

8.107 A BJT differential amplifier, biased to have re = 50  (a) Find the dc bias current in each of the three transistors.
 
and utilizing two 50- emitter resistors and 5-k loads, Also find the dc voltage at the output. Assume VBE  =
drives a second differential stage biased to have re = 25 . 0.7 V, β = 100, and neglect the Early effect.
All BJTs have β = 100. What is the voltage gain of the first (b) Find the input resistance and the output resistance.
stage? Also find the input resistance of the first stage, and (c) Use the current-gain method to evaluate the voltage gain
the current gain from the input of the first stage to the vo /vi .
collectors of the second stage.

D 8.108 (a) If, in the multistage amplifier of Fig. 8.38, the 5V

resistor R5 is replaced by a constant-current source  1
mA, such that the bias situation is essentially unaffected, 3.3 k
what does the overall voltage gain of the amplifier become? 8.2 k
68 k
Assume that the output resistance of the current source is
very high. Use the results of Example 8.8. Q2
(b) With the modification suggested in (a), what is the effect vi Q1 Q3
of the change on output resistance? What is the overall
vo
gain of the amplifier when loaded by 100  to ground? 33 k 5.6 k
The original amplifier (before modification) has an output 4.7 k 2.4 k
resistance of 152  and a voltage gain of 8513 V/V. What is
its gain when loaded by 100 ? Comment. Use β = 100. 5V
*8.109 Figure P8.109 shows a three-stage amplifier in Figure P8.109
which the stages are directly coupled. The amplifier, how-
ever, utilizes bypass capacitors, and, as such, its frequency
response falls off at low frequencies. For our purposes here, 8.110 Consider the circuit in Fig. 8.37 with the
we shall assume that the capacitors are large enough to act as  µm) shown in Table P8.110.
device geometries  (in
perfect short circuits at all signal frequencies of interest. Let IREF = 50 µA, Vt  = 0.4 V for all devices, μn Cox =

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem
 Problems 647

Table P8.110

CHAPTER 8
Transistor Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8

W/L 25/0.5 25/0.5 6.25/0.5 6.25/0.5 50/0.5 W/0.5 50/0.5 12.5/0.5

 
360 µA/V , μp Cox = 90 µA/V , VA  = 6 V for all devices,
2 2
8.114 In the multistage amplifier of Fig. 8.38, emitter

PROBLEMS
VDD = VSS = 0.9 V. Determine the width of Q6 , W, that will resistors are to be introduced: 100  in the emitter lead
ensure that the op amp will not have a systematic
   offset  of each of the first-stage transistors and 25  for each of
voltage. Then, for all devices evaluate ID , VOV , VGS , gm , the second-stage transistors. What is the effect on input
and ro . Provide your results in a table similar to Table 8.1. resistance, the voltage gain of the first stage, and the overall
Also find A1 , A2 , the open-loop voltage gain, the input voltage gain? Use the bias values found in Example 8.7.
common-mode range, and the output voltage range. Neglect
D 8.115 Consider the circuit of Fig. 8.38 and its output
the effect of VA on the bias currents.
resistance. Which resistor has the most effect on the output
D *8.111 In a particular design of the CMOS op amp of resistance? What should this resistor be changed to if the
Fig. 8.37 the designer wishes to investigate the effects of output resistance is to be reduced by a factor of 2? What
increasing the W/L ratio of both Q1 and Q2 by a factor will the amplifier gain become after this change? What
of 4. Assuming that all other parameters are kept unchanged, other change can you make to restore the amplifier gain to
refer to Example 8.6 to help you answer the following approximately its prior value?
questions:
  **8.116 The MOS differential amplifier shown in
(a) What change results in VOV  and in gm of Q1 Fig. P8.116 utilizes three current mirrors for signal
and Q2 ? transmission: Q4−Q6 has a transmission factor of 2 [i.e.,
(b) What change results in the voltage gain of the input (W/L)6 /(W/L)4 = 2], Q3−Q5 has a transmission factor of 1,
stage? In the overall voltage gain? and Q7−Q8 has a transmission factor of 2. All transistors
  are
(c) What is the effect on the input offset voltages? (You sized to operate at the same overdrive voltage, VOV . All

might wish to refer to Section 8.4). transistors have the same Early voltage VA .
8.112 Consider the input stage of the CMOS op amp in (a) Provide in tabular form the values of ID , gm , and ro of
Fig. 8.37 with both inputs grounded. Assume that the two each of the eight transistors in terms of I, VOV , and VA .
sides of the input stage are perfectly matched except that the
threshold voltages of Q3 and Q4 have a mismatch Vt . Show VDD
that a current gm3 Vt appears at the output of the first stage.
What is the corresponding input offset voltage? Q5 Q3 Q4 Q6
D 8.113 The two-stage op amp in Figure P8.104 is fab-
 
ricated in a 65-nm technology having kn = 5.4 × kp =
2
540 µA/V and Vtn = −Vtp = 0.35 V. The amplifier is Q1 Q2
operated with VDD = +1.2 V and VSS = 0 V. vo
(a) Perform a dc design that will cause each of Q1 , Q2 , Q3 ,
and Q4 to conduct a drain current of 200 µA and each
I
of Q6 and Q7 to conduct a current of 400 µA. Design so
that all transistors operate at 0.15-V overdrive voltages.
Specify the W/L ratio required for each MOSFET. Q7 Q8
Present all results in a table.
(b) Find the input common-mode range. VDD
(c) Find the allowable range of the output voltage.
(d) With vA = vid /2 and vB = −vid /2, find the voltage gain Figure P8.116
vo /vid . Assume an Early voltage of 2.4 V.
 648 Chapter 8 Differential and Multistage Amplifiers
PROBLEMS

(b) Show that the differential voltage gain Ad is given by transfer ratio is given by
   
Ad = 2gm1 ro6 ro8 = VA /VOV 1
Ai  Ai (ideal) 1 −
gm ro
(c) Show that the CM gain is given by
  ro6 ro8 1 where gm and ro are the parameters of the input transistor
Acm   of the mirror.)
RSS gm7 ro7
CHAPTER 8

(d) If the current source I is implemented using a simple

where RSS is the output resistance of the bias current mirror and the MOS transistor is operated at the same
source I. (Hint: Since the input differential circuit is bal- VOV , show that the CMRR is given by
anced, each of Q1 and Q2 will conduct a common-mode
 2
signal current of approximately (vicm /2RSS ). These cur- CMRR = 4 VA /VOV
rents are fed into the current mirror loads. Use the
current-mirror equivalent circuit derived in Section (e) Find the input CM  range and the output linear range in
7.2.5. Specificially, for each current mirror, the current terms of VDD , Vt , and VOV .

problems with green numbers are considered essential; * = difficult problem; ** = more difficult; *** = very challenging
= simulation; D = design problem