572 VLSI Hasan Alsalman Homeworks 4
572 VLSI Hasan Alsalman Homeworks 4
1. [25 points] The purpose of this homework is to get you familiar with PSPICE
tool. Spice is an acronym for Simulation Program with Integrated Circuit
Emphasis. PSPICE is circuit simulator application for simulation and
verification of analog and mixed-signal circuits. We will use PSpice to
simulate 3-input AOI gate F=[(A*B) + C]‘ from homework 3.
Preparation:
- Read through OCS the OrCAD Pspice manual. This will help you finish
your homework in time.
Expected Results:
- Simulate the AOI circuit for the logic functionality so it satisfies gate
properties with 0.5-µm CMOS technology, Load Capacitance CL=160 fF
and a power supply voltage VDD=3 V.
- From the transient analysis measure the propagation delay values from the
midpoint one of the inputs waveforms (the midpoint of the voltage at the
Vinput) to the midpoint of output (Vout).
- A fair amount of precision is required on this assignment to get the correct
values, so use cursors when you are determining propagation delays.
Now apply the input pulse to a different input. Repeat for three inputs, and
for the rising and falling portions of the waveform.
Hand in your propagation-delay values. The delays will be different for
each of the two inputs, and for rising versus falling.
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The propagation delay as below I measured delay, by using the midpoint 1.5 V
as total we have 3 V of the voltage of an input pulse and by comparing it to the
midpoint of the output voltage.
Also, I measured delays for each input (A, B, and C), for both rising and falling edges
of the waveform as the below screenshot and attached files
By comparing the propagation delays for each input and edge to determine the
fastest and slowest paths. Differences in delay can result from the circuit layout and
the inherent capacitance differences at each input (A ,B and c) with F can be
summarized for Analyzing the result in the table below.
Input A
Input B
Input C
Output F
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To calculate the propagation delay
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- Which is the fastest? The slowest? Why?
B is the fastest due to the combination of the transistor characteristics and the circuit
design. If we compare it to the rising propagation delay (where B was slower), the
NMOS transistors performing better for pulling the signal down to 0 the difference
between rising and falling delays suggests that different parts of the circuit (PMOS
vs. NMOS) have different performance characteristics.
B is the fastest for the falling edge with a propagation delay of 0.0007 µs.
C has a propagation delay of 4.57 ns, which have the smallest delay between A and
B meaning C is also very fast.
C is likely the fastest because it uses a PMOS transistor in the lower part of the
CMOS logic. PMOS transistors typically have better conductivity when pulling the
signal to ground, which could explain a faster response and a smaller propagation
delay compared to the other inputs (A and B). PMOS transistors can charge
capacitances more efficiently than NMOS in certain configurations, contributing to a
faster transition time.
SPICE Code :
* 1 = GND (-29.5,25.5)
VGND 1 0 DC 0
* 2 = VDD (-34,70)
VDD 2 0 DC 3
* 3 = F (30.499,46.5)
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* 4 = B (0,84)
* 5 = A (-8,83.5)
* 6 = C (7.999,84)
Cpar1 3 0 7.336125f
Cpar2 7 0 7.9149375f
Cload 3 0 160fF
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+PSCBE1 = 5.88417E8 PSCBE2 = 1.020647E-4 PVAG = 0.3914131
+DELTA = 0.01 MOBMOD = 1 PRT = 0
+UTE = -1.5 KT1 = -0.11 KT1L = 0
+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
+UC1 = -5.6E-11 AT = 3.3E4 WL = 0
+WLN = 1 WW = 0 WWN = 1
+WWL = 0 LL = 0 LLN = 1
+LW = 0 LWN = 1 LWL = 0
+CAPMOD = 2 XPART = 0.4 CGDO = 1.9E-10
+CGSO = 1.9E-10 CGBO = 1E-11 CJ = 4.266435E-4
+PB = 0.99 MJ = 0.4481178 CJSW = 3.152209E-10
+PBSW = 0.5007282 MJSW = 0.1339493 )
* Total Nodes: 8
* Total Elements: 8
* Extract Elapsed Time: 0 seconds
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.END
Waveforms
Showing 3 input A , B and C in green and the F in blue
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2. [5 points] What is meant by a Voltage Transfer Characteristic (VTC)?
An asymmetric VTC curve can occur when there is a mismatch between the pull-up
and pull-down networks in a circuit. For example, if NMOS transistors switch faster
or have a different threshold voltage than PMOS transistors, this mismatch causes the
VTC curve to shift, resulting in asymmetry. (Chen et al., 2021)1.
4. [5 points] Does the VTC tell you anything about the timing of gate?
The VTC can provide implicit information about when switching occurs by indicating
transition voltages at which the gate turns on or off, thereby showing its switching
capability. However, to obtain direct timing information, such as propagation delay or
timing skew, a transient analysis is necessary.
5. [10 points] Briefly explain how noise margins are calculated and why?
To calculate noise margins, we define two key thresholds: NMH (Noise Margin High)
and NML (Noise Margin Low).
The low threshold, NMH is the case between VOH and VIH.
NML is a result of VIL which is defined as input low threshold minus VOL which is
the output low.
These noise margins represent the maximum allowable noise that a circuit can tolerate
at high and low logic levels, ensuring that the circuit maintains reliable performance
despite potential interference from surrounding circuits.
Noise margins help define the range of acceptable signal deviation, supporting
reliable operation under noisy conditions by indicating the maximum noise voltage a
circuit can withstand without misinterpreting logic levels.
Reference:
1- Chen, L., et al. "Effects of Transistor Parameter Variations on VTC Curve
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Symmetry in CMOS Circuits." IEEE Transactions on Circuits and Systems, vol. 68,
no. 4, 2021, pp. 1123-1130.