Kuwait University

Computer Engineering Department

CpE 572 - VLSI Design Principle
Homework # 4
Due Date: November 13, 2024, Wednesday
Hasan H. Alsalman
224125180

1. [25 points] The purpose of this homework is to get you familiar with PSPICE
tool. Spice is an acronym for Simulation Program with Integrated Circuit
Emphasis. PSPICE is circuit simulator application for simulation and
verification of analog and mixed-signal circuits. We will use PSpice to
simulate 3-input AOI gate F=[(A*B) + C]‘ from homework 3.

Done as the attached files

Preparation:
- Read through OCS the OrCAD Pspice manual. This will help you finish
your homework in time.

Expected Results:
- Simulate the AOI circuit for the logic functionality so it satisfies gate
properties with 0.5-µm CMOS technology, Load Capacitance CL=160 fF
and a power supply voltage VDD=3 V.

Done as the attached file .cir

- From the transient analysis measure the propagation delay values from the
midpoint one of the inputs waveforms (the midpoint of the voltage at the
Vinput) to the midpoint of output (Vout).
- A fair amount of precision is required on this assignment to get the correct
values, so use cursors when you are determining propagation delays.
Now apply the input pulse to a different input. Repeat for three inputs, and
for the rising and falling portions of the waveform.
Hand in your propagation-delay values. The delays will be different for
each of the two inputs, and for rising versus falling.

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 The propagation delay as below I measured delay, by using the midpoint 1.5 V
as total we have 3 V of the voltage of an input pulse and by comparing it to the
midpoint of the output voltage.

Also, I measured delays for each input (A, B, and C), for both rising and falling edges
of the waveform as the below screenshot and attached files
By comparing the propagation delays for each input and edge to determine the
fastest and slowest paths. Differences in delay can result from the circuit layout and
the inherent capacitance differences at each input (A ,B and c) with F can be
summarized for Analyzing the result in the table below.

Input A

Input B

Input C

Output F

 Tables as per the above simulation results :

The input Rasing The input Falling

A 500.993 n A 1.0034 u
B 500.128 n B 1.0003 u
C 501.726 n C 1.0002 u

The output Rasing The Falling

F 506.296 n output
F 1.0010 u

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  To calculate the propagation delay

Tpdr for A: rising propagation delay

A : 506.296 - 500.993 = 5.303 ns

Tpdr for B: rising propagation

B: 506.296 - 500.128 = 6.168 ns

Tpdr for C : rising propagation

C: 506.296 – 501.726 = 4.57ns

Tpd: average rising propagation delay

Tpd average rising: 5.303 + 6.168 + 4.57 / 3 =
=16.041 ns / 3
=5.347 ns

Tpdr for A: falling propagation delay

A : 1.0034 - 1.0010 = 0.0024 us

Tpdr for B: falling propagation

B: 1.0003 – 1.0010 = 0.0007 us

Tpdr for C : falling propagation

C: 1.0002 – 1.0010 = 0.0008 us

Tpd: average falling propagation delay

Tpd average : 1.0034 + 1.0003 + 1.0002 / 3 =
=3.0039 us / 3
= 1.0013 us

When we add the inputs A , B and C in the simulation curve represented in

yellow and in the other hand the pink color represent the output F we can see clearly
the propagation delay between the time of the input and reflected in the output.

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- Which is the fastest? The slowest? Why?

 Falling propagation delay:

B is the fastest due to the combination of the transistor characteristics and the circuit
design. If we compare it to the rising propagation delay (where B was slower), the
NMOS transistors performing better for pulling the signal down to 0 the difference
between rising and falling delays suggests that different parts of the circuit (PMOS
vs. NMOS) have different performance characteristics.

B is the fastest for the falling edge with a propagation delay of 0.0007 µs.

 Rising propagation delay:

C has a propagation delay of 4.57 ns, which have the smallest delay between A and
B meaning C is also very fast.

B is the slowest, with the largest rising propagation delay of 6.168 ns

C is likely the fastest because it uses a PMOS transistor in the lower part of the
CMOS logic. PMOS transistors typically have better conductivity when pulling the
signal to ground, which could explain a faster response and a smaller propagation
delay compared to the other inputs (A and B). PMOS transistors can charge
capacitances more efficiently than NMOS in certain configurations, contributing to a
faster transition time.

- Please turn in your SPICE code along with the waveforms.

 SPICE Code :

* Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ;

* TDB File: C:\Users\H\OneDrive\Desktop\VLSI\ledit\l-edit student version 72last\
L-Edit Student v7.12\Layout1 homework 3 Hasan Alsalman ok submited HW , Cell:
Cell0
* Extract Definition File: C:\Users\H\OneDrive\Desktop\VLSI\ledit\l-edit student
version 72last\mosis\mhp_ns5.ext
* Extract Date and Time: 11/10/2024 - 22:29

* NODE NAME ALIASES

* 1 = GND (-29.5,25.5)
VGND 1 0 DC 0
* 2 = VDD (-34,70)
VDD 2 0 DC 3

* 3 = F (30.499,46.5)

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* 4 = B (0,84)
* 5 = A (-8,83.5)
* 6 = C (7.999,84)

VB 4 0 pulse ( 1 3 1p 1p 1p 0.5u 1u)

VA 5 0 pulse ( 1 3 1p 1p 1p 0.5u 1u)
VC 6 0 pulse ( 1 3 1p 1p 1p 0.5u 1u)
.TRAN .02u 2u
.PROBE

Cpar1 3 0 7.336125f
Cpar2 7 0 7.9149375f
Cload 3 0 160fF

M3 1 4 8 1 NMOS L=0.5u W=1.5u AD=2.8125p PD=6.75u AS=2.4375p PS=6.25u

* M3 DRAIN GATE SOURCE BULK (-3 29.5 -1 35.5)
M4 8 5 3 1 NMOS L=0.5u W=1.5u AD=2.4375p PD=6.25u AS=5.625p PS=13.5u
* M4 DRAIN GATE SOURCE BULK (-11.5 29.5 -9.5 35.5)
M5 3 6 1 1 NMOS L=0.5u W=1.5u AD=5.625p PD=13.5u AS=2.8125p PS=6.75u
* M5 DRAIN GATE SOURCE BULK (6.5 29.5 8.5 35.5)
M6 7 4 2 2 PMOS L=0.5u W=2.25u AD=8.15625p PD=16.25u AS=3.65625p
PS=7.75u
* M6 DRAIN GATE SOURCE BULK (-3 54.5 -1 63.5)
M7 2 5 7 2 PMOS L=0.5u W=2.25u AD=3.65625p PD=7.75u AS=8.15625p
PS=16.25u
* M7 DRAIN GATE SOURCE BULK (-11.5 54.5 -9.5 63.5)
M8 3 6 7 2 PMOS L=0.5u W=2.25u AD=3.9375p PD=8u AS=8.15625p PS=16.25u
* M8 DRAIN GATE SOURCE BULK (6.5 54.5 8.5 63.5)

.MODEL NMOS NMOS ( LEVEL = 7

+VERSION = 3.1 TNOM = 27 TOX = 1.39E-8
+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = 0.77269
+K1 = 0.7297494 K2 = -0.0506893 K3 = 31.4631363
+K3B = -11.2621866 W0 = 1E-8 NLX = 1E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.806584 DVT1 = 0.4071509 DVT2 = -0.2695432
+U0 = 530.4792998 UA = 2.711027E-13 UB = 3.086214E-18
+UC = 6.526596E-11 VSAT = 9.92744E4 A0 = 0.5982151
+AGS = 0.1815599 B0 = 1.260889E-6 B1 = 1.247614E-6
+KETA = -9.95193E-3 A1 = 0 A2 = 1
+RDSW = 2.265793E3 PRWG = -0.0421807 PRWB = 0.0840864
+WR = 1 WINT = 2.28694E-7 LINT = 3.4243E-8
+XL = 0 XW = 0 DWG = -2.179541E-8
+DWB = -1.061163E-8 VOFF = -0.1276 NFACTOR = 1.601
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.02354 ETAB = -1.35983E-3
+DSUB = 0.2295 PCLM = 1.4773229 PDIBLC1 = -0.3225681
+PDIBLC2 = 3.242849E-3 PDIBLCB = 3.28937E-3 DROUT = 0.3630621

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+PSCBE1 = 5.88417E8 PSCBE2 = 1.020647E-4 PVAG = 0.3914131
+DELTA = 0.01 MOBMOD = 1 PRT = 0
+UTE = -1.5 KT1 = -0.11 KT1L = 0
+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
+UC1 = -5.6E-11 AT = 3.3E4 WL = 0
+WLN = 1 WW = 0 WWN = 1
+WWL = 0 LL = 0 LLN = 1
+LW = 0 LWN = 1 LWL = 0
+CAPMOD = 2 XPART = 0.4 CGDO = 1.9E-10
+CGSO = 1.9E-10 CGBO = 1E-11 CJ = 4.266435E-4
+PB = 0.99 MJ = 0.4481178 CJSW = 3.152209E-10
+PBSW = 0.5007282 MJSW = 0.1339493 )

.MODEL PMOS PMOS ( LEVEL = 7

+VERSION = 3.1 TNOM = 27 TOX = 1.39E-8
+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = -0.972531
+K1 = 0.5616782 K2 = 2.773863E-4 K3 = 12.7986171
+K3B = -0.4723902 W0 = 1E-8 NLX = 1E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.811011 DVT1 = 0.188458 DVT2 = -0.1862226
+U0 = 364.2897131 UA = 6.556695E-9 UB = 2.005454E-19
+UC = -5.21416E-12 VSAT = 1.805928E5 A0 = 0.6916524
+AGS = 0.217888 B0 = 2.404098E-6 B1 = 5E-6
+KETA = -3.409663E-3 A1 = 0 A2 = 1
+RDSW = 2.846814E3 PRWG = -0.0499675 PRWB = -0.1304146
+WR = 1 WINT = 2.508674E-7 LINT = 1.459153E-8
+XL = 0 XW = 0 DWG = -2.24102E-8
+DWB = 2.268096E-8 VOFF = -0.1446 NFACTOR = 0.9027
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 4.973E-3 ETAB = -3.342697E-3
+DSUB = 0.1147 PCLM = 3.1538098 PDIBLC1 = 0.6370303
+PDIBLC2 = 1.376041E-3 PDIBLCB = 0.2184 DROUT = 0.6256738
+PSCBE1 = 1.235615E10 PSCBE2 = 1.210011E-9 PVAG = 7.1862598
+DELTA = 0.01 MOBMOD = 1 PRT = 0
+UTE = -1.5 KT1 = -0.11 KT1L = 0
+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
+UC1 = -5.6E-11 AT = 3.3E4 WL = 0
+WLN = 1 WW = 0 WWN = 1
+WWL = 0 LL = 0 LLN = 1
+LW = 0 LWN = 1 LWL = 0
+CAPMOD = 2 XPART = 0.4 CGDO = 2.42E-10
+CGSO = 2.42E-10 CGBO = 1E-11 CJ = 7.303593E-4
+PB = 0.9569 MJ = 0.5047944 CJSW = 2.120694E-10
+PBSW = 0.8208359 MJSW = 0.1000002 )

* Total Nodes: 8
* Total Elements: 8
* Extract Elapsed Time: 0 seconds

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.END
 Waveforms
Showing 3 input A , B and C in green and the F in blue

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 2. [5 points] What is meant by a Voltage Transfer Characteristic (VTC)?

A Voltage Transfer Characteristic (VTC) is a curve visually represent the

relationship between the input and output voltages of a digital circuit, such as an
inverter. It demonstrates how the output voltage varies in response to changes in input
voltage, with particular emphasis on regions where the circuit transitions between
high and low logic levels.
The VTC curve is crucial for analyzing a circuit’s response to input variations,
showing stable output regions and transition phases where switching occurs

3. [5 points] Why might a voltage transfer characteristic (VTC) be asymmetric?

An asymmetric VTC curve can occur when there is a mismatch between the pull-up
and pull-down networks in a circuit. For example, if NMOS transistors switch faster
or have a different threshold voltage than PMOS transistors, this mismatch causes the
VTC curve to shift, resulting in asymmetry. (Chen et al., 2021)1.

4. [5 points] Does the VTC tell you anything about the timing of gate?

The VTC can provide implicit information about when switching occurs by indicating
transition voltages at which the gate turns on or off, thereby showing its switching
capability. However, to obtain direct timing information, such as propagation delay or
timing skew, a transient analysis is necessary.

5. [10 points] Briefly explain how noise margins are calculated and why?

To calculate noise margins, we define two key thresholds: NMH (Noise Margin High)
and NML (Noise Margin Low).

The low threshold, NMH is the case between VOH and VIH.

NML is a result of VIL which is defined as input low threshold minus VOL which is
the output low.

These noise margins represent the maximum allowable noise that a circuit can tolerate
at high and low logic levels, ensuring that the circuit maintains reliable performance
despite potential interference from surrounding circuits.

Noise margins help define the range of acceptable signal deviation, supporting
reliable operation under noisy conditions by indicating the maximum noise voltage a
circuit can withstand without misinterpreting logic levels.

Reference:
1- Chen, L., et al. "Effects of Transistor Parameter Variations on VTC Curve

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Symmetry in CMOS Circuits." IEEE Transactions on Circuits and Systems, vol. 68,
no. 4, 2021, pp. 1123-1130.