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 WINNER OF THE
Frederick Emmons Terman Award in Electrical & Computer Engineering

FOURTH EDITION

CMOS
Circuit Design, Layout, and Simulation

R. JACOB BAKER

IEEE Series on Microelectronic Systems

Brief Contents
Chapter 1 Introduction to CMOS Design 1
Chapter 2 The Well 31
Chapter 3 The Metal Layers 59
Chapter 4 The Active and Poly Layers 83
Chapter 5 Resistors, Capacitors, MOSFETs 107
Chapter 6 MOSFET Operation 135
Chapter 7 CMOS Fabrication by Jeff Jessing 165
Chapter 8 Electrical Noise: An Overview 221
Chapter 9 Models for Analog Design 277
Chapter 10 Models for Digital Design 327
Chapter 11 The Inverter 347
Chapter 12 Static Logic Gates 369
Chapter 13 Clocked Circuits 389
Chapter 14 Dynamic Logic Gates 411
Chapter 15 CMOS Layout Examples 425
Chapter 16 Memory Circuits 445
Chapter 17 Sensing Using Modulation 493
Chapter 18 Special Purpose CMOS Circuits 533
Chapter 19 Digital Phase-Locked Loops 561
Chapter 20 Current Mirrors 621
Chapter 21 Amplifiers 671
Chapter 22 Differential Amplifiers 735
Chapter 23 Voltage References 773
Chapter 24 Operational Amplifiers I 803
Chapter 25 Dynamic Analog Circuits 857
Chapter 26 Operational Amplifiers II 889
Chapter 27 Nonlinear Analog Circuits 933
Chapter 28 Data Converter Fundamentals by Harry Li 955
Chapter 29 Data Converter Architectures by Harry Li 987
Chapter 30 Implementing Data Converters 1043
Chapter 31 Feedback Amplifiers with Harry Li 1115
Chapter 32 Hysteretic Power Converters 1175

WJJ
Contents

Preface YYYJJJ

Chapter 1 Introduction to CMOS Design 1

1.1 The CMOS IC Design Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Fabrication 2
Layout and Cross-Sectional Views 5
1.2 CMOS Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
The CMOS Acronym 6
CMOS Inverter 6
The First CMOS Circuits 7
Analog Design in CMOS 7
1.3 An Introduction to SPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Generating a Netlist File 8
Operating Point 8
Transfer Function Analysis 10
The Voltage-Controlled Voltage Source 10
An Ideal Op-Amp 11
The Subcircuit 12
DC Analysis 13
Plotting IV Curves 13
Dual Loop DC Analysis 14
Transient Analysis 14
The SIN Source 15
An RC Circuit Example 16
Another RC Circuit Example 17
AC Analysis 18
Decades and Octaves 19
Decibels 19
Pulse Statement 20
Finite Pulse Rise time 20

JY
Y Contents

Step Response 21
Delay and Rise time in RC Circuits 21
Piece-Wise Linear (PWL) Source 22
Simulating Switches 22
Initial Conditions on a Capacitor 23
Initial Conditions in an Inductor 23
Q of an LC Tank 24
Frequency Response of an Ideal Integrator 24
Unity-Gain Frequency 26
Time-Domain Behavior of the Integrator 26
Convergence 26
Some Common Mistakes and Helpful Techniques 27
Chapter 2 The Well 31
The Substrate (The Unprocessed Wafer) 31
A Parasitic Diode 31
Using the N-well as a Resistor 32
2.1 Patterning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.1.1 Patterning the N-well 35
2.2 Laying Out the N-well . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.1 Design Rules for the N-well 36
2.3 Resistance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Layout of Corners 38
2.3.1 The N-well Resistor 38
2.4 The N-well/Substrate Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.4.1 A Brief Introduction to PN Junction Physics 39
Carrier Concentrations 40
Fermi Energy Level 41
2.4.2 Depletion Layer Capacitance 42
2.4.3 Storage or Diffusion Capacitance 45
2.4.4 SPICE Modeling 46
2.5 The RC Delay through the N-well . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
RC Circuit Review 48
Distributed RC Delay 50
Distributed RC Rise Time 51
2.6 Twin Well Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Design Rules for the Well 52
SEM Views of Wells 54
Chapter 3 The Metal Layers 59
3.1 The Bonding Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Contents YJ

3.1.1 Laying Out the Pad I 60

Capacitance of Metal-to-Substrate 60
Passivation 62
An Important Note 62
3.2 Design and Layout Using the Metal Layers . . . . . . . . . . . . . . . . . . . . . . 63
3.2.1 Metal1 and Via1 63
An Example Layout 63
3.2.2 Parasitics Associated with the Metal Layers 63
Intrinsic Propagation Delay 65
3.2.3 Current-Carrying Limitations 67
3.2.4 Design Rules for the Metal Layers 68
Layout of Two Shapes or a Single Shape 68
A Layout Trick for the Metal Layers 68
3.2.5 Contact Resistance 69
3.3 Crosstalk and Ground Bounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.3.1 Crosstalk 71
3.3.2 Ground Bounce 72
DC Problems 72
AC Problems 72
A Final Comment 74
3.4 Layout Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.4.1 Laying Out the Pad II 74
3.4.2 Laying Out Metal Test Structures 76
SEM View of Metal 79
Chapter 4 The Active and Poly Layers 83
4.1 Layout Using the Active and Poly Layers . . . . . . . . . . . . . . . . . . . . . . . . 83
The Active Layer 83
The P- and N-Select Layers 84
The Poly Layer 86
Self-Aligned Gate 86
The FinFET 88
The Poly Wire 89
Silicide Block 90
4.1.1 Process Flow 90
Damascene Process Steps 91
4.2 Connecting Wires to Poly and Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Connecting the P-Substrate to Ground 94
Layout of an N-Well Resistor 94
Layout of an NMOS Device 95
xJJ Contents

Layout of a PMOS Device 96

A Comment Concerning MOSFET Symbols 97
Standard Cell Frame 97
Design Rules 98
4.3 Electrostatic Discharge (ESD) Protection . . . . . . . . . . . . . . . . . . . . . . . 99
Layout of the Diodes 101
Chapter 5 Resistors, Capacitors, MOSFETs 107
5.1 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Temperature Coefficient (Temp Co) 107
Polarity of the Temp Co 108
Voltage Coefficient 109
Using Unit Elements 110
Guard Rings 111
Interdigitated Layout 112
Common-Centroid Layout 112
Dummy Elements 114
5.2 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Layout of the Poly-Poly Capacitor 115
Parasitics 117
Temperature Coefficient (Temp Co) 117
Voltage Coefficient 117
5.3 MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Lateral Diffusion 118
Oxide Encroachment 119
Source/Drain Depletion Capacitance 119
Source/Drain Parasitic Resistance 119
Layout of Long-Length MOSFETs 121
Layout of Large-Width MOSFETs 122
A Qualitative Description of MOSFET Capacitances 123
5.4 Layout Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Metal Capacitors 126
Polysilicon Resistors 128
Chapter 6 MOSFET Operation 135
6.1 MOSFET Capacitance Overview/Review . . . . . . . . . . . . . . . . . . . . . . . 136
Case I: Accumulation 136
Case II: Depletion 137
Case III: Strong Inversion 137
Summary 139
6.2 The Threshold Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Contents xJJi

Contact Potentials 141

Threshold Voltage Adjust 143
6.3 IV Characteristics of MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
6.3.1 MOSFET Operation in the Triode Region 144
6.3.2 The Saturation Region 146
Cgs Calculation in the Saturation Region 148
6.4 SPICE Modeling of the MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Model Parameters Related to V THN 149
Long-Channel MOSFET Models 149
Model Parameters Related to the Drain Current 150
SPICE Modeling of the Source and Drain Implants 150
Summary 151
6.4.1 Some SPICE Simulation Examples 151
Threshold Voltage and Body Effect 151
6.4.2 The Subthreshold Current 152
6.5 Short-Channel MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Hot Carriers 154
Lightly Doped Drain (LDD) 155
6.5.1 MOSFET Scaling 155
6.5.2 Short-Channel Effects 156
Negative Bias Temperature Instability (NBTI) 156
Oxide Breakdown 157
Drain-Induced Barrier Lowering 157
Gate-Induced Drain Leakage 157
Gate Tunnel Current 157
6.5.3 SPICE Models for Our Short-Channel CMOS 157
Process
BSIM4 Model Listing (NMOS) 157
BSIM4 Model Listing (PMOS) 159
Simulation Results 160
Chapter 7 CMOS Fabrication by Jeff Jessing 165
7.1 CMOS Unit Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
7.1.1 Wafer Manufacture 165
Metallurgical Grade Silicon (MGS) 166
Electronic Grade Silicon (EGS) 166
Czochralski (CZ) Growth and Wafer Formation 166
7.1.2 Thermal Oxidation 167
7.1.3 Doping Processes 168
Ion Implantation 169
xiW Contents

Solid State Diffusion 170

7.1.4 Photolithography 170
Resolution 172
Depth of Focus 173
Aligning Masks 173
7.1.5 Thin Film Removal 173
Thin Film Etching 174
Wet Etching 174
Dry Etching 175
Chemical Mechanical Polishing 176
7.1.6 Thin Film Deposition 177
Physical Vapor Deposition (PVD) 178
Chemical Vapor Depositon (CVD) 179
7.2 CMOS Process Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
FEOL 181
BEOL 181
CMOS Process Description 181
7.2.1 Frontend-of-the-Line Integration 182
Starting Material 182
Shallow Trench Isolation Module 184
Twin Tub Module 188
Gate Module 192
Source/Drain Module 194
7.2.2 Backend-of-the-Line Integration 196
Self-Aligned Silicide (Salicide) Module 197
Pre-Metal Dielectric 199
Contact Module 200
Metallization 1 202
Intra-Metal Dielectric 1 Deposition 204
Via 1 Module 205
Metallization 2 205
Additional Metal/Dieletric Layers 206
Final Passivation 209
7.3 Backend Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Wafer Probe 210
Die Separation 212
Packaging 212
Final Test and Burn-In 212
7.4 Advanced CMOS Process Integration 212
Contents xW

7.4.1 FinFETs 213

7.4.2 Dual Damascene Low-k/Cu Interconnects 216
7.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Chapter 8 Electrical Noise: An Overview 221
8.1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.1.1 Power and Energy 221
Comments 223
8.1.2 Power Spectral Density 223
Spectrum Analyzers 223
8.2 Circuit Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
8.2.1 Calculating and Modeling Circuit Noise 227
Input-Referred Noise I 227
Noise Equivalent Bandwidth 228
Input-Referred Noise in Cascaded Amplifiers 230
Calculating Vonoise,RMS from a Spectrum: A Summary 231
8.2.2 Thermal Noise 231
8.2.3 Signal-to-Noise Ratio 237
Input-Referred Noise II 238
Noise Figure 240
An Important Limitation of the Noise Figure 240
Optimum Source Resistance 243
Simulating Noiseless Resistors 243
Noise Temperature 245
Averaging White Noise 246
8.2.4 Shot Noise 247
8.2.5 Flicker Noise 251
8.2.6 Other Noise Sources 258
Random Telegraph Signal Noise 258
Excess Noise (Flicker Noise) 259
Avalanche Noise 259
8.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
8.3.1 Correlation 260
Correlation of Input-Referred Noise Sources 261
Complex Input Impedance 262
8.3.2 Noise and Feedback 264
Op-Amp Noise Modeling 265
8.3.3 Some Final Notes Concerning Notation 267
Chapter 9 Models for Analog Design 277
9.1 Long-Channel MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
xWi Contents

9.1.1 The Square-Law Equations 279

PMOS Square-Law Equations 280
Qualitative Discussion 280
Threshold Voltage and Body Effect 283
Qualitative Discussion 284
The Triode Region 285
The Cutoff and Subthreshold Regions 286
9.1.2 Small Signal Models 286
Transconductance 287
AC Analysis 292
Transient Analysis 293
Body Effect Transconductance, gmb 294
Output Resistance 295
MOSFET Transition Frequency, fT 297
General Device Sizes for Analog Design 298
Subthreshold gm and V THN 299
9.1.3 Temperature Effects 300
Threshold Variation and Temperature 300
Mobility Variation with Temperature 301
Drain Current Change with Temperature 302
9.2 Short-Channel MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
9.2.1 General Design (A Starting Point) 303
Output Resistance 304
Forward Transconductance 304
Transition Frequency 305
9.2.2 Specific Design (A Discussion) 306
9.3 MOSFET Noise Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Drain Current Noise Model 308
Chapter 10 Models for Digital Design 327
Miller Capacitance 327
10.1 The Digital MOSFET Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Effective Switching Resistance 328
Short-Channel MOSFET Effective Switching 330
Resistance
10.1.1 Capacitive Effects 331
10.1.2 Process Characteristic Time Constant 331
10.1.3 Delay and Transition Times 333
10.1.4 General Digital Design 326
10.2 The MOSFET Pass Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Contents xWJJ

The PMOS Pass Gate 337

10.2.1 Delay through a Pass Gate 338
The Transmission Gate (The TG) 340
10.2.2 Delay through Series-Connected PGs 340
10.3 A Final Comment Concerning Measurements . . . . . . . . . . . . . . . . . 341
Chapter 11 The Inverter 347
11.1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Noise Margins 349
Inverter Switching Point 350
Ideal Inverter VTC and Noise Margins 350
11.2 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
The Ring Oscillator 354
Dynamic Power Dissipation 355
11.3 Layout of the Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Latch-Up 356
11.4 Sizing for Large Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Buffer Topology 359
Distributed Drivers 362
Driving Long Lines 363
11.5 Other Inverter Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
NMOS-Only Output Drivers 365
Inverters with Tri-State Outputs 366
Additional Examples 366
Chapter 12 Static Logic Gates 369
12.1 DC Characteristics of the NAND and NOR Gates . . . . . . . . . . . . . 369
12.1.1 DC Characteristics of the NAND Gate 369
12.1.2 DC Characteristics of the NOR Gate 372
A Practical Note Concerning V SP and Pass Gates 373
12.2 Layout of the NAND and NOR Gates . . . . . . . . . . . . . . . . . . . . . . . . . 373
12.3 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Parallel Connection of MOSFETs 374
Series Connection of MOSFETs 374
12.3.1 NAND Gate 375
Quick Estimate of Delays 377
12.3.2 Number of Inputs 378
12.4 Complex CMOS Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Cascode Voltage Switch Logic 383
Differential Split-Level Logic 383
Tri-State Outputs 383
xvJJi Contents

Additional Examples 384

Chapter 13 Clocked Circuits 389
13.1 The CMOS TG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Series Connection of TGs 390
13.2 Applications of the Transmission Gate . . . . . . . . . . . . . . . . . . . . . . . . 391
Path Selector 391
Static Circuits 394
13.3 Latches and Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Basic Latches 395
An Arbiter 396
Flip-Flops and Flow-through Latches 397
An Edge-Triggered D-FF 399
Flip-Flop Timing 400
13.4 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Chapter 14 Dynamic Logic Gates 411
14.1 Fundamentals of Dynamic Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
14.1.1 Charge Leakage 411
14.1.2 Simulating Dynamic Circuits 414
14.1.3 Nonoverlapping Clock Generation 415
14.1.4 CMOS TG in Dynamic Circuits 416
14.2 Clocked CMOS Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Clocked CMOS Latch 417
An Important Note 417
PE Logic 418
Domino Logic 419
NP Logic (Zipper Logic) 420
Pipelining 421
Chapter 15 CMOS Layout Examples 425
15.1 Chip Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Regularity 426
Standard Cell Examples 426
Power and Ground Considerations 428
An Adder Example 431
A 4-to-1 MUX/DEMUX 433
15.2 Layout Steps by Dean Moriarty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Planning and Stick Diagrams 434
Device Placement 437
Polish 437
Standard Cells Versus Full-Custom Layout 437
Contents xJY

Chapter 16 Memory Circuits 445

16.1 Array Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
16.1.1 Sensing Basics 446
NMOS Sense Amplifier (NSA) 447
The Open Array Architecture 447
PMOS Sense Amplifier (PSA) 450
Refresh Operation 452
16.1.2 The Folded Array 452
Layout of the DRAM Memory Bit (Mbit) 453
16.1.3 Chip Organization 458
16.2 Peripheral Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
16.2.1 Sense Amplifier Design 458
Kickback Noise and Clock Feedthrough 459
Memory 461
Current Draw 461
Contention Current (Switching Current) 461
Removing Sense Amplifier Memory 462
Creating an Imbalance and Reducing Kickback Noise 462
Increasing the Input Range 465
Simulation Examples 466
16.2.2 Row/Column Decoders 467
Global and Local Decoders 468
Reducing Decoder Layout Area 470
16.2.3 Row Drivers 470
16.3 Memory Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
16.3.1 The SRAM Cell 473
16.3.2 Read-Only Memory (ROM) 473
16.3.3 Floating Gate Memory 473
The Threshold Voltage 474
Erasable Programmable Read-Only Memory 477
Two Important Notes 478
Flash Memory 479
Chapter 17 Sensing Using Modulation 493
17.1 Qualitative Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
17.1.1 Examples of DSM 494
The Counter 495
Cup Size 496
Another Example 496
17.1.2 Using DSM for Sensing in Flash Memory 496
xY Contents

The Basic Idea 497

The Feedback Signal 501
Incomplete Settling 505
17.2 Sensing Resistive Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
The Bit Line Voltage 507
Adding an Offset to the Comparator 507
Schematic and Design Values 508
A Couple of Comments 511
17.3 Sensing in CMOS Imagers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Resetting the Pixel 513
The Intensity Level 514
Sampling the Reference and Intensity Signals 514
Noise Issues 514
Subtracting V R from V S 516
Sensing Circuit Mismatches 526
Chapter 18 Special Purpose CMOS Circuits 533
18.1 The Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
18.1.1 Design of the Schmitt Trigger 534
Switching Characteristics 536
18.1.2 Applications of the Schmitt Trigger 536
18.2 Multivibrator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
18.2.1 The Monostable Multivibrator 539
18.2.2 The Astable Multivibrator 540
18.3 Input Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
18.3.1 Basic Circuits 541
Skew in Logic Gates 542
18.3.2 Differential Circuits 543
Transient Response 544
18.3.3 DC Reference 547
18.3.4 Reducing Buffer Input Resistance 550
18.4 Charge Pumps (Voltage Generators) . . . . . . . . . . . . . . . . . . . . . . . . . 551
Negative Voltages 552
Using MOSFETs for the Capacitors 553
18.4.1 Increasing the Output Voltage 553
18.4.2 Generating Higher Voltages: The Dickson Charge 553
Pump
Clock Driver with a Pumped Output Voltage 554
NMOS Clock Driver 555
18.4.3 Example 556
Contents xYJ

Chapter 19 Digital Phase-Locked Loops 561

19.1 The Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
19.1.1 The XOR Phase Detector 563
19.1.2 The Phase Frequency Detector 567
19.2 The Voltage-Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
19.2.1 The Current-Starved VCO 570
Linearizing the VCO’s Gain 573
19.2.2 Source-Coupled VCOs 574
19.3 The Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
19.3.1 XOR DPLL 577
Active-PI Loop Filter 581
19.3.2 PFD DPLL 583
Tri-State Output 583
Implementing the PFD in CMOS 584
PFD with a Charge Pump Output 587
Practical Implementation of the Charge Pump 588
Discussion 589
19.4 System Concerns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
19.4.1 Clock Recovery from NRZ Data 593
The Hogge Phase Detector 596
Jitter 598
19.5 Delay-Locked Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
Delay Elements 602
Practical VCO and VCDL Design 602
19.6 Some Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
19.6.1 A 2 GHz DLL 603
19.6.2 A 1 Gbit/s Clock-Recovery Circuit 609
Chapter 20 Current Mirrors 621
20.1 The Basic Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
20.1.1 Long-Channel Design 622
20.1.2 Matching Currents in the Mirror 624
Threshold Voltage Mismatch 624
Transconductance Parameter Mismatch 624
Drain-to-Source Voltage and Lambda 625
Layout Techniques to Improve Matching 625
Layout of the Mirror with Different Widths 627
20.1.3 Biasing the Current Mirror 628
Using a MOSFET-Only Reference Circuit 629
Supply Independent Biasing 631
xxJJ Contents

20.1.4 Short-Channel Design 634

An Important Note 637
20.1.5 Temperature Behavior 638
Resistor-MOSFET Reference Circuit 638
MOSFET-Only Reference Circuit 639
Temperature Behavior of the Beta-Multiplier 641
Voltage Reference Using the Beta-Multiplier 641
20.1.6 Biasing in the Subthreshold Region 642
20.2 Cascoding the Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
20.2.1 The Simple Cascode 643
DC Operation 643
Cascode Output Resistance 644
20.2.2 Low-Voltage (Wide-Swing) Cascode 645
An Important Practical Note 647
Layout Concerns 648
20.2.3 Wide-Swing, Short-Channel Design 648
20.2.4 Regulated Drain Current Mirror 651
20.3 Biasing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
20.3.1 Long-Channel Biasing Circuits 653
Basic Cascode Biasing 653
The Folded-Cascode Structure 653
20.3.2 Short-Channel Biasing Circuits 656
Floating Current Sources 656
20.3.3 A Final Comment 657
Chapter 21 Amplifiers 671
21.1 Gate-Drain Connected Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
21.1.1 Common-Source (CS) Amplifiers 671
Miller’s Theorem 674
Frequency Response 675
The Right-Hand Plane Zero 675
A Common-Source Current Amplifier 679
Common-Source Amplifier with Source Degeneration 681
Noise Performance of the CS Amplifier with 683
Gate-Drain Load
21.1.2 The Source Follower (Common-Drain Amplifier) 683
21.1.3 Common Gate Amplifier 684
21.2 Current Source Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
21.2.1 Common-Source Amplifier 685
Class A Operation 685
Contents xxJJi

Small-Signal Gain 686

Open Circuit Gain 686
High-Impedance and Low-Impedance Nodes 687
Frequency Response 687
Pole Splitting 689
Pole Splitting Summary 692
Canceling the RHP Zero 697
Noise Performance of the CS Amplifier with Current 698
Source Load
21.2.2 The Cascode Amplifier 698
Frequency Response 699
Class A Operation 700
Noise Performance of the Cascode Amplifier 700
Operation as a Transimpedance Amplifier 701
21.2.3 The Common-Gate Amplifier 702
21.2.4 The Source Follower (Common-Drain Amplifier) 702
Body Effect and Gain 703
Level Shifting 704
Input Capacitance 705
Noise Performance of the SF Amplifier 706
Frequency Behavior 706
SF as an Output Buffer 708
A Class AB Output Buffer Using SFs 709
21.3 The Push-Pull Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
21.3.1 DC Operation and Biasing 711
Power Conversion Efficiency 711
21.3.2 Small-Signal Analysis 714
21.3.3 Distortion 716
Modeling Distortion with SPICE 717
Chapter 22 Differential Amplifiers 735
22.1 The Source-Coupled Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
22.1.1 DC Operation 735
Maximum and Minimum Differential Input Voltage 736
Maximum and Minimum Common-Mode Input 737
Voltage
Current Mirror Load 739
Biasing from the Current Mirror Load 740
Minimum Power Supply Voltage 741
22.1.2 AC Operation 741
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Title: Victor Serenus: A Story of the Pauline Era

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BOSTON

VICTOR SERENUS
A STORY OF THE PAULINE ERA

BY
HENRY WOOD
AUTHOR OF “IDEAL SUGGESTION” “GOD’S IMAGE IN MAN” “EDWARD BURTON”
“THE POLITICAL ECONOMY OF NATURAL LAW” “STUDIES IN THE THOUGHT
WORLD” ETC.
 It is only the finite that has wrought and suffered; the
infinite lies stretched in smiling repose.—Emerson.

BOSTON U.S.A.
LEE AND SHEPARD PUBLISHERS
1904

Copyright, 1898, by Henry Wood

All Rights Reserved

 Victor Serenus

TYPOGRAPHY BY C. J. PETERS & SON, BOSTON, U.S.A.

PRESSWORK BY BERWICK & SMITH.

To Margaret

[pg v]

PREFACE
It seems unnecessary to suggest that this book is entirely
independent of the conventional lines of the modern realistic novel.
To any who hold that idealism in fiction is not artistic, that a didactic
element is inadmissible, and that philosophizing has no place, the
work will hardly commend itself. To others, who believe that fiction
may be a useful vehicle for the conveyance of helpful ideals, and
even abstract truth, it is offered with the hope that it may furnish
some measure both of entertainment and profit.

On many historical and chronological points that are involved,

authorities differ; but so far as the author has been able to sift
them, the prevailing and apparently most probable hypotheses have
been followed. As may be inferred, it has been necessary to glean in
many fields for the facts, opinions, and conclusions that make up the
historic portion of the raw material from which this story has been
fabricated.1

[pg vi]
A majority of the characters being creations, and a large part of the
action also unhistoric, it must be left to the judgment of the reader
how well they fit into their historic frame-work. So far as St. Paul is
introduced in the narrative, nearly everything delineated belongs to
those portions of his life which are but very briefly or incidentally
touched upon, either in the Scriptural writings or other history. But
utilizing many undoubted realities, the aim has been to fill in the
wide blanks with that which is in accord and in the line of the
possible or probable.

The author has intended to respect the hallowed associations which

cluster about the name of the great Apostle. But Paul was a man
with like passions as other men, and to be faithful, any outline of the
forces that played through his great soul should be drawn naturally,
and without that misleading glamor often imposed by far-away time
and distance. Only by such a treatment can his life be brought near,
and its practical lessons enforced. If to any the interpretation seem
unduly broad, they may be assured that the author has no
iconoclastic intent, but on the contrary, an aim which is wholly
constructive, whereby everything wholesome and uplifting in human
life may be encouraged and strengthened.

Boston, 1898.

[pg vii]

CONTENTS

PART FIRST
Chapter Page
I. A Religious Procession in Tarsus 1
II. An Evening Excursion on the Cydnus 8
III. In the Toils 17
IV. The Net is Rent 23
V. Two University Students 32
VI. To the Tower of Antonia 40
VII. A Tarsian Festival to Apollo 47
VIII. The Mysteries of the Adytum 56
IX. Soliloquy of Gamaliel’s Daughter 68
X. Magic and Mystery: Strange Visions 79
XI. Important Messages 92
XII. Serenus makes an Avowal 102
 XIII. The Walls have Ears 111
XIV. Love versus Duty 121
XV. The Rescue of Rebecca 133
XVI. After the Storm 146
XVII. A Roman Parade 161
XVIII. Amabel’s Remarkable Experience 177
XIX. Surrounded by Prison Walls 195
XX. Sowing and Reaping 211
XXI. The Great Harvest 228
PART SECOND
THE LIGHT SPREADS TO THE WESTWARD
XXII. Sunshine and Shadow 245
XXIII. A Battered Eagle 260
XXIV. On the Verge of the Unseen 280
XXV. A Psychical Journey 299
XXVI. A Powerful Pulse Stirred 312
XXVII. A Message from Stephanos 330
XXVIII. Leander visits a Mystic Shrine 348
XXIX. Changes of Soul-color 368
XXX. A Paradise Discovered 381
XXXI. In Deep Waters 399
XXXII. Scourging and Flight 412
XXXIII. A Priestess of the Tarsian Temple 422
XXXIV. Once More Upon the Cydnus 430
PART THIRD
AFTER THE FLIGHT OF TWENTY YEARS
XXXV. The Bay of Puteoli 441
XXXVI. Nocturnal Interview with a Seer 449
XXXVII. Two Woeful Souls Released 463
PART FOURTH
SAULUS IN ROME
XXXVIII. Awaiting Trial Before Nero 481
XXXIX. Antipodes Brought Face to Face 492
XL. The Visible Form Laid Aside 500
[pg 1]
VICTOR SERENUS

A STORY OF THE PAULINE ERA

PART FIRST
 CHAPTER I
A RELIGIOUS PROCESSION IN TARSUS

In an ancient city, late in the afternoon of a warm day in early

autumn, a little procession was winding its way through the narrow
crowded streets. The calm, measured pace and solemn
countenances of the group plainly indicated its character as a
religious ceremonial. Slightly in the lead were two priests, of such
official and dignified mien that they appeared as though they knew
the God of Israel face to face. It was as if the little Hebrew band, in
threading a great throng of Gentiles, were laden with the
accumulated weight of all the traditions of the Chosen and
Circumcised since the time of Abraham. The reverberation of every
sandal, as it struck upon the well-worn pavement, proclaimed, as
loudly as words, “We are separate.” Even the flocks of pigeons that
were in the air seemed to hover over the moving column, as if to
lend the gleam of their white wings to its stately rhythm.

[pg 2]
The priests wore tall turbans of cup-shaped form, and were clad in
long robes having broad borders decorated with a deep fringe, and
gathered about the body with an ornamented girdle. Broad
phylacteries, square in form, were bound by thongs, one upon the
forehead, and one upon the left arm, each containing inscribed
passages from the Law. They also wore embroidered ephods
covering the back and breast, held together on the shoulders by
brooches of onyx stones richly set in gold, and fastened below by a
black band garnished with jewels. Their hands were crossed upon
the breast, and eyes turned toward heaven.
Following just behind the priests were men and women in costumes
such as were usually worn in the synagogue, which indicated that
they were returning from a sacred service. At intervals the low,
monotonous tones of a religious chant, or some soft rendering of
passages from the Mosaic ritual, might have been audible to those in
the near vicinity. They formed an embodied fragment of that long
line of the faithful, who forget not the patriarchs and the lawgivers,
and whose eyes are always turned towards Jerusalem and the
Temple.

In the arms of one of the women was a young infant, and around
this least personage there seemed to gather an interest which
showed that whatever the nature of the service just concluded, the
babe must have been the central figure. The fond glances of the
women and evident attention of the men plainly revealed that
thorough satisfaction which comes from holy duty well performed.

The city of Tarsus was the place, and the time about the middle of
the first decade of the Christian era. [pg 3]Tarsus was a great
commercial metropolis. It was located in the midst of a broad, fertile
plain which mainly made up the province of Eastern or Flat Cilicia, as
distinguished from Rugged Cilicia which bordered it on the north and
west. The prolific soil, central location, and peculiar physical
configuration, all tended to give it great political importance. Leading
from the great plain through the high barrier of mountains which
sweep from the coast irregularly around it are two passes, one
leading up to the interior of Asia Minor, and the other giving access
to the valley of the Orontes. It was naturally the meeting-place, and
on the highway of trading caravans and military expeditions.
Through this richly historic country, Cyrus marched to depose his
brother from the Persian throne. It was on this plain that Alexander
gained his decisive victory over Darius. Here have since been
encamped the great hosts of western crusaders, and indeed, from
the early dawn of history, this plain was the theatre of great events
and conflicts, which had much to do with the shaping of empires,
and the progress of the world’s civilization.
The cold and rapid river Cydnus, fed by the snows of the Taurus
range of mountains, flows through this fertile country; and Tarsus,
the capital of the whole province, which was “no mean city,” was
located upon its banks. Its coins reveal its importance during the
period between Xerxes and Alexander, and also while under Roman
sway, when it was dignified by the name of Metropolis. Strabo says
that in all that relates to philosophy and general education it was
more illustrious than Athens or Alexandria. In the main it had the
character [pg 4]of a Greek city; and the Grecian language, literature,
and philosophy were generally cultivated. But there were also many
Romans, Hebrews, Persians, and Syrians, with a sprinkling of other
tribes and peoples, such as characterized an Oriental metropolis. On
its busy wharves were great piles of merchandise, surrounded by
groups of merchants and traders in many costumes, and speaking a
variety of dialects.

It was one of the most important epochs of history; a time when

colossal personalities and events were stamping their impress upon
the destiny of races and nations. The shores of the Mediterranean
formed the heart of the world’s civilization; and Roman militarism,
legality, and control were permeating and compacting that great
empire, east and west. The Greek and Hebrew were important but
subordinate elements in the human conglomerate of that eventful
period. Various and unlike races were commingling; their customs
and even their religions were shading into each other, and their
languages becoming considerably interchangeable. The Roman
represented law, government, conquest, and dominion; the Greek
the more subtile ideals of philosophy, art, and intellectuality; while
the Hebrew, intense and tenacious, was unconsciously laying the
foundation, through his religious zeal, for the coming spread of
Judaism’s great outgrowth, rival, and successor, Christianity. His hard
religiosity and punctilious ceremonialism were not perceptibly
softened even by close contact with Grecian poetry and idealism.
Even Roman jurisprudence on the one hand, and idolatry on the
other, could not penetrate them. As a rule, the various tribu[pg
5]taries to the great current of human history in its evolutionary
course gradually mingle, each adding something of its own hue to
the common volume, but the Hebraistic economy was the rare
exception. Its oil would not mix with the general water of other
systems.

At the particular time with which we are dealing, general peace

prevailed. There was one of those alternations of calmness which
intervene between the fierce storms of racial conflict and religious
strife and persecution.

The Jewish procession, small in numbers, but important in spirit and

destiny, threaded its way through the winding thoroughfares,
attracting but a passing glance from the cosmopolitans which made
up the multiform currents of every-day life in Tarsus. At length it
halted in front of a family residence in the better part of the Hebrew
quarter, into which one of the priests with the father of the child
entered, followed by the mother with her young son in her arms,
while the others dispersed. The babe, Saulus Paulus, was forty days
old, and, in conformity to the Jewish ritual, had been taken to the
synagogue for the prescribed presentation service.

Before leaving the household, the priest tenderly took the child in his
arms to give him a final blessing. Raising his eyes toward heaven, he
seemed to feel a spirit of prophetic inspiration. With his right hand
upon the head of the child, he reverently presumed to lift the curtain
which veils the future, fervently exclaiming,—

“Son of Abraham, scion of the tribe of Benjamin, and heir of Benoni!

The living blood of the Covenant flows in thy veins! Thou shalt wax
strong, and be [pg 6]learned in all that pertaineth to the Law! Thou
shalt be a tongue of the God of Jacob, and many shall tremble when
thou speakest! Thou shalt be a defender of Israel, and bring
judgment to the Gentiles! Thou shalt open thy mouth and utter
mighty things that are hidden from the Greek and Roman! Thou
shalt sorely vex the enemies of the Circumcision, and bring them to
naught! With holy zeal shalt thou pursue them”—
Then his visage became fixed, and he was like one in a trance. A
voice, not his own, seemed to use his lips. “I behold—judgment—
defeat—darkness! The uncircumcised prevail!”

Abdiel, the priest, trembled like an aspen, and upon coming to

himself, declared that he had seen a disturbing vision.

The ancient Judaism accepted no compromise, and bowed to no

defeat. When surrounded, and even almost submerged, by
prevailing idolatry, polytheism, and heathenism, like a bow
temporarily bent, it at length sprang back, and regained its original
integrity. It was a casting in rigid form of a conglomerate of truth
and error, righteousness and pride. It loathed other creeds and
philosophies, and its Deity was limited by a racial boundary. It was a
political theocracy.

Phariseeism, which was the leading element of Jewish religiosity,

was a compound of spiritual pride, exclusiveness, and intolerance.
Missionary effort among other nations was not thought of because
they were not worth it. God was the God of Israel. The Chosen
People felt that they had a monopoly of the divine favor, and they
proposed to keep it. But the teaching of the ancient [pg 7]seers and
expounders of righteousness, originally good, had become incrusted
with a superficial formalism, and all vitality had left it. Even the
Mosaic Law and the later sublime poems and religious compositions,
though constantly and formally recited, were loaded down with
traditions, and had become a complex system of polished dry bones.
Notwithstanding the discipline of previous dispersions and
captivities, such was the spirit of the Chosen People during the
earliest years of the Christian era.
[pg 8]
 CHAPTER II
AN EVENING EXCURSION ON THE CYDNUS

The residence of Benoni was situated upon the more elevated

plateau which embraced the northwestern portion of the Cilician
metropolis. A little distance to the north was the Orontes Gate,
through which a thoroughfare, paved with much-worn gray and
white flags, led out to the fertile regions in the broad plain above.
Through this portal surged a continuous stream of life, alternating in
direction during the different hours of the day like the tides in an
inlet from the sea. Here were donkeys, with panniers bursting with
fruits, lentils, onions, and beans, and awkward camels, raw-boned,
rough, and gray, with great saddles hung over their backs, the
capacious folds of which contained seemingly endless resources of
baskets, boxes, and miscellaneous merchandise. Horses, roughly
harnessed to light wagons which were heaped with dates, figs,
grapes, and pomegranates, and at intervals small flocks of sheep,
calves, and other animals for the food-supply of a great city, added
to the picturesque conglomerate of life and bustle. Here entered
blatant sellers of ducks, doves, and pigeons, mingling their shrill
cries with the general din and confusion. The massive arched
gateway formed the framework for a shifting panorama of races,
tribes, costumes, and dia[pg 9]lects. Interspersed in the throng were
red and blue cloaks more or less dingy, white turbans, faded tunics,
long beards, and bare legs. Oriental display and decoration were
seen in golden ornaments, including necklaces, bracelets, and
pendants, all lending a gleam and sparkle to the motley streams of
humanity. Here and there were women of the common classes,
wearing loosely gathered long frocks, and upon their heads veils or
wimples ample enough to fall in graceful folds about the shoulders.
Some were leading brown-bodied and half-naked children, with hair
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