MANIPAL UNIVERSITY JAIPUR

School of Electrical, Electronics & Communication Engineering

Department of Electronics & Communication Engineering
Course Hand-out
Course Name: Digital Electronics | Course Code: EC2102 | Credits | 3 1 0 4
Session: July-Nov 2024 | Faculty: Dr. Chusen Duari, Dr Deepika Bansal | Class: III Semester

A. Introduction: This course comes in the class of core subject for the undergraduates. This course
provides a comprehensive study of digital logic design, covering combinational and sequential
circuits, state machines, and various logic families. Students will gain practical knowledge of
designing and analyzing digital circuits, focusing on both theoretical and application aspects.

B. Course Outcomes: At the end of the course, students will be able to

CO Statement Cognitive
Level
1 Analyse and Design Combinational circuits.
2 Describe and characterize flip-flops and it’s applications.

3 Design and analyse Sequential Circuits and analyse timing issues.

4 Design Finite State Machines and Algorithmic State Machines.

5 Understand the different Logic families and semiconductor families. 1

C. PROGRAM OUTCOMES AND PROGRAM SPECIFIC OUTCOMES

[PO.1]. Engineering knowledge: Demonstrate and apply knowledge of Mathematics,

Science, and Engineering to classical and recent problems of electronic design &
communication system.
[PO.2]. Problem analysis: Identify, formulate, research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural
sciences, and engineering sciences.
[PO.3]. Design/development of solutions: Design a component, system, or process to meet
desired needs within realistic constraints such as economic, environmental, social, political, ethical,
health and safety, manufacturability, and sustainability.

[PO.4]. Conduct investigations of complex problems: Use research-based knowledge

and research methods including design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid conclusions

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[PO.5]. Modern tool usage: Create, select, and apply appropriate techniques, resources,
and modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations
[PO.6]. The engineer and society: Apply reasoning informed by the contextual knowledge
to assess societal, health, safety, legal, and cultural issues and the consequent
responsibilities relevant to the professional engineering practice
[PO.7]. Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development
[PO.8]. Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practices
[PO.9]. Individual and team work: Function effectively as an individual, and as a member
or leader in diverse teams, and in multidisciplinary settings
[PO.10]. Communication: Communicate effectively on complex engineering activities with
the engineering community and with society at large, such as, being able to comprehend
and write effective reports and design documentation, make effective presentations, and
give and receive clear instructions
[PO.11]. Project management and finance: Demonstrate knowledge and understanding
of the engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary environments
[PO.12]. Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological
change
PROGRAM SPECIFIC OUTCOMES

[PSO.1]. An ability to understand the concepts of basic Electronics & Communication

Engineering and to apply them to various areas like Signal processing, VLSI, Embedded
systems, Communication Systems, Digital & Analog Devices, etc.
[PSO.2]. An ability to solve complex Electronics and Communication Engineering problems,
using latest hardware and software tools, along with analytical skills to arrive cost effective
and appropriate solutions.
[PSO.3]. Wisdom of social and environmental awareness along with ethical responsibility to
have a successful career and to sustain passion and zeal for real-world applications using
optimal resources as an Entrepreneur.

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 D. Assessment Plan:

Criteria Description Maximum Marks

Mid-Term Examination 30
Internal Assessment (Close Book)
(Summative) Class Work Sessional (CWS): 30
Quiz, MOOC, Research work
Assignment, etc.
End Term Exam End Term Exam (Close Book) 40
(Summative)
Total 100
Attendance A minimum of 75% Attendance is required to be maintained by a
(Formative) student to be qualified for taking up the End Semester examination.
The allowance of 25% includes all types of leaves including medical
leaves.
Make up Assignments Students who miss a class will have to report to the teacher about the
(Formative) absence. A makeup assignment on the topic taught on the day of
absence will be given which has to be submitted within a week from
the date of absence. No extensions will be given on this. The
attendance for that day of absence will be marked blank, so that the
student is not accounted for absence. These assignments are limited
to a maximum of 5 throughout the entire semester.
Homework/ Home Assignment/ There are situations where a student may have to work in home,
Activity Assignment especially before a flipped classroom. Although these works are not
(Formative) graded with marks. However, a student is expected to participate and
perform these assignments with full zeal since the activity/ flipped
classroom participation by a student will be assessed and marks will
be awarded.

E. SYLLABUS
Introduction of Combinational logic design: Overview of Boolean Algebra and K-Map, Half
and Full Adders, Subtractors, Serial and Parallel Adders, BCD Adder. MSI devices: Comparators,
Multiplexers, Encoder, Decoder, Driver & Multiplexed Display, Barrel shifter and ALU.

Sequential logic design: latch, Flip-flop, S-R FF, D FF, JK FF, T FF, and Master-Slave JK FF, Edge
triggered FF, Ripple and Synchronous counters, Shift registers, Timing Analysis of sequential
circuits.

Designing of State Machines: Finite state machines, Design of synchronous FSM, State
Reduction, Timing issues in synchronous circuits. Algorithmic State Machines, Designing
synchronous circuits like Pulse train generator, Pseudorandom Binary Sequence generator, Clock
generation. Design of asynchronous circuits.

Logic Families and Semiconductor Memories: TTL NAND gate, Specifications, Noise
margin, Propagation delay, fan-in, fan-out, Tristate TTL, ECL, CMOS families and their interfacing,
Memory elements, Concept of Programmable logic devices, Logic implementation using
Programmable Devices.

F. TEXT BOOKS
1. A. A. Kumar, FUNDAMENTALS OF DIGITAL CIRCUITS. Prentice Hall India Pvt.,
Limited, (2e), 2016.
2. R. P. Jain, Modern Digital Electronics. McGraw-Hill Education (India) Pvt Limited,
(4e), 2003.

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 3. W.H. Gothmann, Digital Electronics- An introduction to theory and practice, PHI,
(2e), 2006.
4. S. Brown and Z. Vranesic, Fundamentals of Digital logic with Verilog Design,
McGraw Hill, (3e) 2013.

5. M. Mano and M. Ciletti, “Digital Design: With an introduction to Verilog HDL”,

Pearson, 2013

G. Lecture Plan:

Mode of
Correspon Mode of
Lect. Topics Session Outcome Assessing
ding CO delivery
CO
Introduction of Understanding of
1 course and course course, objectives, NA Lecture NA
handout evaluation
Introduction to Student will 2102.1 MTE, Quiz &
Boolean algebra, understand the laws ETE
2 logic gates. of Boolean Algebra Lecture
and fundamental
logic blocks.
Implementation of Student will 2102.1 MTE, Quiz &
Boolean expression understand how to ETE
3 with basic gates, implement any logic Lecture
universal gates & using basic &
SOP, POS forms. universal gates.
Students will be able 2102.1 MTE, Quiz &
Minimization of
to understand the ETE
Boolean expression
4-5 concept minimisation Lecture
using Karnaugh Map
of Boolean
technique.
expression
Design of half Adder 2102.1 MTE, Quiz &
Full adder, Students will be able ETE
6 to design various Lecture
Half subtractor & full arithmetic circuit
subtractor
Students will be able 2102.1 MTE, Quiz &
Serial and Parallel ETE
7,8 to design various Lecture
Adders, BCD Adder
arithmetic circuit
Students will be able 2102.1 MTE, Quiz &
Design of BCD
9 to design various Lecture ETE
adder
arithmetic circuit
Design of 2102.1 MTE, Quiz &
Students will be able
Multiplexer and ETE
to understand the
demultiplexer and
10,11 importance of data Lecture
their application in
selector &
realizing various
distributor circuits.
Boolean expression
Encoders, decoders, Students will be able 2102.1 MTE, Quiz &
Priority encoder, to design various Lecture/ ETE
12-13 Implementation of encoding circuits and Flipped
the Boolean equation their application Classroom
using
Decoder, Students will be able 2102.1 MTE, Quiz &
14-15 Lecture
Comparators, Parity to design various ETE

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 generators and decoding circuits and
checker their application
Barrel shifter and Students will be able 2102.1 MTE, Quiz &
ALU. to understand the ETE
16 Lecture
design of Barrel
Shifter and ALU
Need for sequential Students will learn Lecture/ MTE, Quiz &
17 circuits, Binary cell, about memory cell. 2102.2 Flipped ETE
latches Classroom
Latches and flip-flops. Students will identify 2102.2 MTE, Quiz &
RS, JK, various memory ETE
18 Lecture
elements and their
characteristics
Master-Slave JK, D & Students will identify 2102.2 MTE, Quiz &
T flip flops. Flip-flop various memory ETE
19-20 Lecture
conversion elements and their
characteristics
Introduction to Students will learn 2102.2 MTE, Quiz &
21 Synchronous about various Lecture ETE
Sequential circuits sequential circuits.
Ripple counters Students will learn to 2102.2 MTE, Quiz &
design ETE
22-23 Lecture
asynchronous
counters
Students will learn to 2102.3 MTE, Quiz &
Design of
design process of ETE
24-25 synchronous Lecture
synchronous
Counters
counters
Shift registers, Students will learn to 2102.3 Lecture MTE, Quiz &
26-27 Timing Analysis of design registers and ETE
sequential circuits their application
Finite state machines, Students will learn to 2102.4 Lecture MTE, Quiz &
design various finite ETE
28-31
state machines and
their uses
Students will learn 2102.4 Lecture MTE, Quiz &
State Reduction in
32-33 the procedure for ETE
FSM
reduction of state
Timing issues in Students will learn 2102.4 Lecture MTE, Quiz &
34 synchronous about the timing ETE
circuits.. issues
Mid Term Examination – I
Algorithmic State Students will learn 2102.4 Lecture Quiz & ETE
35-36
Machines, about the ASMs
Students will learn 2102.4 Lecture Quiz & ETE
37 Pulse train generator, about pulse
generator circuit
Pseudorandom Students will learn to 2102.4 Lecture/ Quiz & ETE
38 Binary Sequence binary sequence Flipped
generator generator Classroom
Clock generation Students will 2102.4 Quiz & ETE
39 understand about Lecture
clock generation
Races and Hazards in Students will 2102.4 Quiz & ETE
40
asynchronous understand timing
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 circuits, Timing issues and hazards
issues in arises in digital
synchronous circuit design.
Performance metrics Students will be able 2102.5 Quiz & ETE
of logic gates, Noiseto identify the
margin, Propagation various performance
41 delay, fan-in, fan-out,
parameter that has Lecture
to be considered for
efficient design of
circuit
Transistor- Student will be able 2102.5 Quiz & ETE
Transistor Logic to understand the
42 various families of Lecture
digital logic and their
characteristics.
Tristate TTL, ECL, Students will be able 2102.5 Quiz & ETE
to understand
43 various Lecture
characteristics of
Logic gates
CMOS families and Students will learn 2102.5 Quiz & ETE
44 Lecture
their interfacing, about CMOS logics
Memory elements, Students will learn 2102.5 Quiz & ETE
45 about memory Lecture
elements
Concept of Students will learn 2102.5 Quiz & ETE
Lecture/
Programmable logic about programmable
46 Flipped
devices, logic devices and
Classroom
uses
Logic implementation Students will learn to 2102.5 Quiz & ETE
47 using Programmable implement logic Lecture
Devices circuit with PLD
Logic implementation Students will learn to 2102.5 Lecture/ Quiz & ETE
48 using Programmable implement logic Flipped
Devices circuit with PLD Classroom
End Term Examination

H. Target attainment (%) for course outcomes:

CO Target attainment (%)

1 80%

2 50%

3 80%

4 60%

5 50%

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 I. Course Articulation Matrix: (Mapping of COs with POs and PSOs)

CO Statement Correlation with Program Outcomes

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3

Analyse and Design

1 Combinational 3 1 11 1 2
circuits
Describe and
characterize flip-
2 3 1
flops and it’s
applications.
Design and analyse
Sequential Circuits
3 3 1 1 2 2
and analyse timing
issues.
Design Finite State
Machines and
4 3 1 2 1 2 2
Algorithmic State
Machines.
Understand the
different Logic
5 families and 3 1 1
semiconductor
families

1: Low Correlation 2: Moderate Correlation 3: Substantial Correlation