182 Chapter 4 Combinational Logic

PROBLEMS

(Answers to problems marked with * appear at the end of the text. Where appropriate, a logic
design and its related HDL modeling problem are cross-referenced.)
4.1 Consider the combinational circuit shown in Fig. P4.1. (HDL—see Problem 4.49.)

A
T3
B
T1
C
F1

T2
T4
D

F2

FIGURE P4.1

(a)* Derive the Boolean expressions for T1 through T4. Evaluate the outputs F1 and F2
as a function of the four inputs.
(b) List the truth table with 16 binary combinations of the four input variables. Then list
the binary values for T1 through T4 and outputs F1 and F2 in the table.
(c) Plot the output Boolean functions obtained in part (b) on maps and show that the
simplified Boolean expressions are equivalent to the ones obtained in part (a).
4.2* Obtain the simplified Boolean expressions for output F and G in terms of the input
variables in the circuit of Fig. P4.2.

A
F

B
C

G
D

FIGURE P4.2

4.3 For the circuit shown in Fig. 4.26 (Section 4.11),

(a) Write the Boolean functions for the four outputs in terms of the input variables.
(b)* If the circuit is described in a truth table, how many rows and columns would there
be in the table?
4.4 Design a combinational circuit with three inputs and one output.
(a)* The output is 1 when the binary value of the inputs is less than 3. The output is 0 otherwise.
(b) The output is 1 when the binary value of the inputs is an even number.
 Problems 183

4.5 Design a combinational circuit with three inputs, x, y, and z, and three outputs, A, B, and C.
When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When
the binary input is 4, 5, 6, or 7, the binary output is two less than the input.
4.6 A majority circuit is a combinational circuit whose output is equal to 1 if the input variables
have more 1’s than 0’s. The output is 0 otherwise.
(a)* Design a 3-input majority circuit by finding the circuit’s truth table, Boolean equation,
and a logic diagram.
(b) Write and verify a Verilog gate-level model of the circuit.
4.7 Design a combinational circuit that converts a four-bit Gray code (Table 1.6) to a bit four-
binary number.
(a)* Implement the circuit with exclusive-OR gates.
(b) Using a case statement, write and verify a Verilog model of the circuit.
4.8 Design a code converter that converts a decimal digit from
(a)* The 8, 4, –2, –1 code to BCD (see Table 1.5). (HDL—see Problem 4.50.)
(b) The 8, 4, –2, –1 code to Gray code.
4.9 An ABCD-to-seven-segment decoder is a combinational circuit that converts a decimal digit
in BCD to an appropriate code for the selection of segments in an indicator used to display
the decimal digit in a familiar form. The seven outputs of the decoder (a, b, c, d, e, f, g) select
the corresponding segments in the display, as shown in Fig. P4.9(a). The numeric display
chosen to represent the decimal digit is shown in Fig. P4.9(b). Using a truth table and
Karnaugh maps, design the BCD-to-seven-segment decoder using a minimum number of
gates. The six invalid combinations should result in a blank display. (HDL—see Problem 4.51.)

f b
g
b
e c c
d
(a) Segment designation (b) Numerical designation for display

FIGURE P4.9

4.10* Design a four-bit combinational circuit 2’s complementer. (The output generates the 2’s
complement of the input binary number.) Show that the circuit can be constructed with
exclusive-OR gates. Can you predict what the output functions are for a five-bit 2’s com-
plementer?
4.11 Using four half-adders (HDL—see Problem 4.52),
(a) Design a full-subtractor circuit incrementer. (A circuit that adds one to a four-bit
binary number.)
(b)* Design a four-bit combinational decrementer (a circuit that subtracts 1 from a four-
bit binary number).
4.12 Design a half-subtractor circuit with inputs x and y and outputs Diff and Bout. The circuit
subtracts the bits x – y and places the difference in D and the borrow in Bout.
(a) Design a full-subtractor circuit with three inputs x, y, Bin and two outputs Diff and
Bout. The circuit subtracts x – y – Bin, where Bin is the input borrow, Bout is the output
borrow, and Diff is the difference.
184 Chapter 4 Combinational Logic

4.13* The adder–subtractor circuit of Fig. 4.13 has the following values for mode input M and
data inputs A and B.

M A B
(a) 0 0111 0110
(b) 0 1000 1001
(c) 1 1100 1000
(d) 1 0101 1010
(e) 1 0000 0001

In each case, determine the values of the four SUM outputs, the carry C, and overflow V.
(HDL—see Problems 4.37 and 4.40.)
4.14* Assume that the exclusive-OR gate has a propagation delay of 10 ns and that the AND or
OR gates have a propagation delay of 5 ns. What is the total propagation delay time in the
four-bit adder of Fig. 4.12?
4.15 Derive the two-level Boolean expression for the output carry C4 shown in the lookahead
carry generator of Fig. 4.12.
4.16 Define the carry propagate and carry generate as
Pi  A i  B i
Gi  AiBi
respectively. Show that the output carry and output sum of a full adder becomes
Ci + 1 = (Ci Gi + Pi )
Si = (PiGi) { Ci
The logic diagram of the first stage of a four-bit parallel adder as implemented in IC type
74283 is shown in Fig. P4.16. Identify the Pi and Gi terminals and show that the circuit
implements a full-adder circuit.

C1

B0

S0

A0

C0

FIGURE P4.16
First stage of a parallel adder
 Problems 185

4.17 Show that the output carry in a full adder circuit can be expressed in the AND-OR-
INVERT form
Ci + 1 = Gi + PiCi = (GiPi + GiCi)
IC type 74182 is a lookahead carry generator circuit that generates the carries with AND-
OR-INVERT gates (see Section 3.8). The circuit assumes that the input terminals have
the complements of the G’s, the P’s, and of C1. Derive the Boolean functions for the
lookahead carries C2, C3, and C4 in this IC. (Hint: Use the equation-substitution method
to derive the carries in terms of Ci)
4.18 Design a combinational circuit that generates the 9’s complement of a
(a)* BCD digit. (HDL—see Problem 4.54(a).)
(b) Gray-code digit. (HDL—see Problem 4.54(b).)
4.19 Construct a BCD adder–subtractor circuit. Use the BCD adder of Fig. 4.14 and the 9’s
complementer of problem 4.18. Use block diagrams for the components. (HDL—see Prob-
lem 4.55.)
4.20 For a binary multiplier that multiplies two unsigned four-bit numbers,
(a) Using AND gates and binary adders (see Fig. 4.16), design the circuit.
(b) Write and verify a Verilog dataflow model of the circuit.
4.21 Design a combinational circuit that compares two 4-bit numbers to check if they are equal.
The circuit output is equal to 1 if the two numbers are equal and 0 otherwise.
4.22* Design an excess-3-to-binary decoder using the unused combinations of the code as
don’t-care conditions. (HDL—see Problem 4.42.)
4.23 Draw the logic diagram of a 2-to-4-line decoder using (a) NOR gates only and (b) NAND
gates only. Include an enable input. (HDL—see Problems 4.36, 4.45.)
4.24 Design a BCD-to-decimal decoder using the unused combinations of the BCD code as
don’t-care conditions.
4.25 Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and a 2-to-
4-line decoder. Use block diagrams for the components. (HDL—see Problem 4.63.)
4.26 Construct a 4-to-16-line decoder with five 2-to-4-line decoders with enable. (HDL—see
Problem 4.64.)
4.27 A combinational circuit is specified by the following three Boolean functions:
F1 1A, B, C2 = ⌺11, 4, 62
F2 1A, B, C2 = ⌺13, 52
F3 1A, B, C2 = ⌺12, 4, 6, 72
Implement the circuit with a decoder constructed with NAND gates (similar to Fig. 4.19)
and NAND or AND gates connected to the decoder outputs. Use a block diagram for the
decoder. Minimize the number of inputs in the external gates.
4.28 Using a decoder and external gates, design the combinational circui defined by the
following three Boolean functions:
(a) F1 = x⬘yz⬘ + xz (b) F1 = 1y⬘ + x2z
F2 = xy⬘z⬘ + x⬘y F2 = y⬘z⬘ + x⬘y + yz⬘
F3 = x⬘y⬘z⬘ + xy F3 = 1x + y2z
186 Chapter 4 Combinational Logic

4.29* Design a four-input priority encoder with inputs as in Table 4.8, but with input D0 having
the highest priority and input D3 the lowest priority.
4.30 Specify the truth table of an octal-to-binary priority encoder. Provide an output V to in-
dicate that at least one of the inputs is present. The input with the highest subscript num-
ber has the highest priority. What will be the value of the four outputs if inputs D2 and D6
are 1 at the same time? (HDL—see Problem 4.65.)
4.31 Construct a 16 ⫻ 1 multiplexer with two 8 ⫻ 1 and one 2 ⫻ 1 multiplexers. Use block dia-
grams. (HDL—see Problem 4.67.)
4.32 Implement the following Boolean function with a multiplexer (HDL—see Problem 4.46):
(a) F 1A, B, C, D2 = ⌺ 10, 2, 5, 8, 10, 142
(b) F 1A, B, C, D2 = ⌸ 12, 6, 112

4.33 Implement a full adder with two 4 ⫻ 1 multiplexers.

4.34 An 8 ⫻ 1 multiplexer has inputs A, B, and C connected to the selection inputs S2 , S1, and
S0, respectively. The data inputs I0 through I7 are as follows:
(a)* I1⫽ I2⫽ I7⫽ 0; I3⫽ I5⫽ 1; I0⫽ I4⫽ D; and I6⫽ D’.
(b) I1 ⫽ I2 ⫽ 0; I3 ⫽ I7 ⫽ 1; I4 ⫽ I5 ⫽ D; and I0 ⫽ I6 ⫽ D’.
Determine the Boolean function that the multiplexer implements.
4.35 Implement the following Boolean function with a 4 ⫻ 1 multiplexer and external gates.
(a)* F1 1A, B, C, D2 = ⌺ 11, 3, 4, 11, 12, 13, 14, 152
(b) F2 1A, B, C, D2 = ⌺ 11, 2, 5, 7, 8, 10, 11, 13, 152
Connect inputs A and B to the selection lines. The input requirements for the four data
lines will be a function of variables C and D. These values are obtained by expressing F as
a function of C and D for each of the four cases when AB ⫽ 00, 01, 10, and 11. These func-
tions may have to be implemented with external gates. (HDL—see Problem 4.47.)
4.36 Write the HDL gate-level description of the priority encoder circuit shown in Fig. 4.23.
(HDL—see Problem 4.45.)
4.37 Write the HDL gate-level hierarchical description of a four-bit adder–subtractor for un-
signed binary numbers. The circuit is similar to Fig. 4.13 but without output V. You can
instantiate the four-bit full adder described in HDL Example 4.2. (HDL—see Problems
4.13 and 4.40.)
4.38 Write the HDL dataflow description of a quadruple 2-to-1-line multiplexer with enable
(see Fig. 4.26).
4.39* Write an HDL behavioral description of a four-bit comparator with a six-bit output Y 3 5:0 4 .
Bit 5 of Y is for “equals,” bit 4 for “not equal to,” bit 3 for “greater than,” bit 2 for “less
than,” bit 1 for “greater than or equal,” and bit 0 for “less than or equal to.”
4.40 Using the conditional operator (?:), write an HDL dataflow description of a four-bit adder–
subtractor of unsigned numbers. (See Problems 4.13 and 4.37.)
4.41 Repeat problem 4.40 using an always statement.
 Problems 187

4.42 (a) Write an HDL gate-level description of the BCD-to-excess-3 converter circuit shown
in Fig. 4.4 (see Problem 4.22).
(b) Write a dataflow description of the BCD-to-excess-3 converter using the Boolean
expressions listed in Fig. 4.3.
(c)* Write an HDL behavioral description of a BCD-to-excess-3 converter.
(d) Write a test bench to simulate and test the BCD-to-excess-3 converter circuit in order
to verify the truth table. Check all three circuits.
4.43 Explain the function of the circuit specified by the following HDL description:
module Prob4_43 (A, B, S, E, Q);
input [1:0] A, B;
input S, E;
output [1:0] Q;
assign Q ⫽ E ? (S ? A : B) : 'bz;
endmodule
4.44 Using a case statement, write an HDL behavioral description of a eight-bit arithmetic-
logic unit (ALU). The circuit has a three-bit select bus (Sel), sixteen-bit input datapaths
(A[15:0] and B[15:0]), an eight-bit output datapath (y[15:0]), and performs the arithmetic
and logic operations listed below.
Sel Operation Description
000 y ⫽ 8⬘b0
001 y⫽A&B Bitwise AND
010 y⫽A|B Bitwise OR
011 y⫽A^B Bitwise exclusive OR
100 y ⫽ ~A Bitwise complement
101 y⫽A⫺B Subtract
110 y⫽A⫹B Add (Assume A and B are unsigned)
111 y ⫽ 8⬘hFF

4.45 Write an HDL behavioral description of a four-input priority encoder. Use a four-bit vector
for the D inputs and an always block with if–else statements. Assume that input D[3] has
the highest priority (see Problem 4.36).
4.46 Write a Verilog dataflow description of the logic circuit described by the Boolean function
in Problem 4.32.
4.47 Write a Verilog dataflow description of the logic circuit described by the Boolean function
in Problem 4.35.
4.48 Develop and modify the eight-bit ALU specified in Problem 4.44 so that it has three-state
output controlled by an enable input, En. Write a test bench and simulate the circuit.
4.49 For the circuit shown in Fig. P4.1,
(a) Write and verify a gate-level HDL model of the circuit.
(b) Compare your results with those obtained for Problem 4.1.
4.50 Using a case statement, develop and simulate a behavioral model of
(a)* The 8, 4, –2, –1 to BCD code converter described in Problem 4.8(a).
(b) The 8, 4, –2, –1 to Gray code converter described in Problem 4.8(b).
188 Chapter 4 Combinational Logic

4.51 Develop and simulate a behavioral model of the ABCD-to-seven-segment decoder

described in Problem 4.9.
4.52 Using a continuous assignment, develop and simulate a dataflow model of
(a) The four-bit incrementer described in Problem 4.11(a).
(b) The four-bit decrementer described in Problem 4.11(b).
4.53 Develop and simulate a structural model of the decimal adder shown in Fig. 4.14.
4.54 Develop and simulate a behavioral model of a circuit that generates the 9’s complement of
(a) a BCD digit (see Problem 4.18(a)).
(b) a Gray-code digit (see Problem 4.18(b).)
4.55 Construct a hierarchical model of the BCD adder–subtractor described in Problem 4.19.
The BCD adder and the 9’s complementer are to be described as behavioral models in
separate modules, and they are to be instantiated in a top-level module.
4.56* Write a continuous assignment statement that compares two 4-bit numbers to check if
their bit patterns match. The variable to which the assignment is made is to equal 1 if the
numbers match and 0 otherwise.
4.57* Develop and verify a behavioral model of the four-bit priority encoder described in
Problem 4.29.
4.58 Write a Verilog model of a circuit whose 32-bit output is formed by shifting its 32-bit input
three positions to the right and filling the vacant positions with the bit that was in the MSN
before the shift occurred (shift arithmetic right).Write a Verilog model of a circuit whose
32-bit output is formed by shifting its 32-bit input three positions to the left and filling the
vacant positions with 0 (shift logical left).
4.59 Write a Verilog model of a BCD-to-decimal decoder using the unused combinations of
the BCD code as don’t-care conditions (see Problem 4.24).
4.60 Using the port syntax of the IEEE 1364-2001 standard, write and verify a gate-level model
of the four-bit even parity checker shown in Fig. 3.34.
4.61 Using continuous assignment statements and the port syntax of the IEEE 1364-2001 standard,
write and verify a gate-level model of the four-bit even parity checker shown in Fig. 3.34.
4.62 Write and verify a gate-level hierarchical model of the circuit described in Problem 4.25.
4.63 Write and verify a gate-level hierarchical model of the circuit described in Problem 4.26.
4.64 Write and verify a Verilog model of the octal-to-binary circuit described in Problem 4.30.
4.65 Write a hierarchical gate-level model of the multiplexer described in Problem 4.31.

REFERENCES

1. Bhasker, J. 1997. A Verilog HDL Primer. Allentown, PA: Star Galaxy Press.
2. Bhasker, J. 1998. Verilog HDL Synthesis. Allentown, PA: Star Galaxy Press.
3. Ciletti, M. D. 1999. Modeling, Synthesis, and Rapid Prototyping with Verilog HDL. Upper
Saddle River, NJ: Prentice Hall.
4. Dietmeyer, D. L. 1988. Logic Design of Digital Systems, 3rd ed. Boston: Allyn Bacon.
   60  

CHAPTER 4

4.1
(a) T1 = B'C, T2 = A'B, T3 = A + T1 = A + B'C,
T4 = D ⊕ T2 = D ⊕ (A'B) = A'BD' + D(A + B') = A'BD' + AD + B'D
F1 = T3 + T4 = A + B'C + A'BD' + AD + B'D
With A + AD = A and A + A'BD' = A + BD':
F1 = A + B'C + BD' + B'D
Alternative cover: F1 = A + CD' + BD' + B'D
 
F2 = T2 + D' = A'B + D'

ABCD T1 T2 T3 T4 F1 F2
CD C
0000 0 0 0 0 0 1 00 01 11 10
0001 0 0 0 1 1 0 M0 M1 M3 M2
0010 1 0 1 0 1 1 00 1 1 1
0011 1 0 1 1 1 0
M4 M5 M7 M6
0100 0 1 0 1 1 1
01 1 1
0101 0 1 0 0 0 1
0110 0 1 0 1 1 1 M12 M13 M15 M14 B
0111 0 1 0 0 0 1 11 1 1 1 1
A M8 M9 M11 M10
1000 0 0 1 0 1 1
10 1 1 1 1
1001 0 0 1 1 1 0
1010 1 0 1 0 1 1
1011 1 0 1 1 1 0 D
1100 0 0 1 0 1 1
1101 0 0 1 1 1 0 F1 = A + B'C+ B'D + BD'
1110 0 0 1 0 1 1
1111 0 0 1 1 1 0

CD C CD C
AB 00 01 11 10 AB 00 01 11 10
M0 M1 M3 M2 M0 M1 M3 M2
00 1 1 00 1 1 1
M4 M5 M7 M6 M4 M5 M7 M6
01 1 1 1 1 01 1 1
M12 M13 M15 M14 B M12 M13 M15 M14 B
11 1 1 A 11 1 1 1 1
A M8 M9 M11 M10 M8 M9 M11 M10
10 1 1 10 1 1 1 1

D D
F2 = A'B + D' F1 = A + CD' + B'D + BD'

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   61  

4.2    
[(A'D)' A']'= A + D
A'
A
F

B BC + A'
C BC
G
D
(A'D)' = A + D’

F = (A + D)(A' + BC) = A'D + ABC + BCD += A'D + ABC

F = (A + D')(A' +BC) = A'D' + ABC + BCD' = A'D' + ABC

CD C CD C
AB 00 01 11 10 AB 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 01 1 1
m12 m13 m15 m14 B m12 m13 m15 m14 B
11 1 1 11 1 1
A m8 m9 m11 m10 A m8 m9 m11 m10
10 10

D D
F = A'D + ABC + BCD = A'D + ABC G = A'D' + ABC + BCD' = A'D' + ABC

4.3 (a) Yi = (AiS' + BiS)E' for i = 0, 1, 2, 3

(b) 1024 rows and 14 columns

4.4 (a)
xyz F
yz y
000 1 x 00 01 11 10
001 1 m0 m1 m3 m2 x'
010 1 0 1 1 1 y'
011 0
m4 m5 m7 m6 F
100 0
x 1 x'
101 0
y'
110 0
111 0 z
F = x'y' + x'z'  

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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   62  

(b)
xyz F
yz y
000 0 x
00 01 11 10
001 1 m0 m1 m3 m2
010 0 0 1 1
011 0 z F
100 0 m4 m5 m7 m6

101 0 x 1 1 1
110 0
111 0 z
F=z  
4.5
xyz ABC A
yz y
000 010 x
00 01 11 10
001 011 m0 m1 m3 m2 x'
010 100 0 1 1 y
011 101
m4 m5 m7 m6 A
100 001
x 1 1 y
101 010
z
110 011
111 100 z
A = x'y + yz

B y
yz
x 00 01 11 10
m0 m1 m3 m2 x
0 1 1 y'
m4 m5 m7 m6
x 1 1 1 y'
B
z
x
z
y
B = x'y' + y'z + xyz'
z'
C
yz y
x
00 01 11 10
m0 m1 m3 m2
0 1 1
x
m4 m5 m7 m6 C
z
x 1 1 1

z
C= x'z + xz'

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   63  

4.6
xyz F A
yz y
000 0 x 00 01 11 10
001 0 m0 m1 m3 m2 x
010 0 0 1 z
011 1 y
m4 m5 m7 m6 F
100 0 z
x 1 1 1 1 x
101 1
y
110 1
111 1 z
F = xz + yz + xy    
 
  module Prob_4_6 (output F, input x, y, z);
assign F = (x & z) | (y & z) | (x & y);
endmodule
 
 

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   64  

4.7 (a)

 
ABCD wxyz
CD C CD C
0000 0000 AB
00 01 11 10 00 01 11 10
0001 0001 m0 m1 m3 m2 m0 m1 m3 m2
0011 0010 00 00
0010 0011
m4 m5 m7 m6 m4 m5 m7 m6
0110 0100
0111 0101 01 01 1 1 1 1
0101 0110 m12 m13 m15 m14 B m12 m13 m15 m14 B
0100 0111 11 1 1 1 1 11
A m8 m9 m11 m10 A m8 m9 m11 m10
1100 1000
1101 1001 10 1 1 1 1 10 1 1 1 1
1111 1010
1110 1011
D D
1010 1100
w=A x = AB' + A'B = A B
1011 1101
1001 1110
1000 1111
CD C CD C
AB 00 01 11 10 AB 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 01 1 1
m12 m13 m15 m14 B m12 m13 m15 m14 B
11 1 1 11 1 1
A m8 m9 m11 m10 A m8 m9 m11 m10
10 1 1 10 1 1

D D
y = A'B'C A'BC' + ABC + AB'C' z=A B C D
= A'(A B) + A(B C)' =y D
=A B C
= X C

A w
B x

C y

z
D  
 
       

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   65  

(b)

module Prob_4_7(output w, x, y, z, input A, B, C, D);

always @ (A, B, C, D)
case ({A, B, C, D})
4'b0000: {w, x, y, z} = 4'b0000;
4'b0001: {w, x, y, z} = 4'b1111;
4'b0010: {w, x, y, z} = 4'b1110;
4'b0011: {w, x, y, z} = 4'b1101;
4'b0100: {w, x, y, z} = 4'b1100;
4'b0101: {w, x, y, z} = 4'b1011;
4'b0110: {w, x, y, z} = 4'b1010;
4'b0111: {w, x, y, z} = 4'b1001;

4'b1000: {w, x, y, z} = 4'b1000;

4'b1001: {w, x, y, z} = 4'b0111;
4'b1010: {w, x, y, z} = 4'b0110;
4'b1011: {w, x, y, z} = 4'b0101;
4'b1100: {w, x, y, z} = 4'b0100;
4'b1101: {w, x, y, z} = 4'b0011;
4'b1110: {w, x, y, z} = 4'b0010;
4'b1111: {w, x, y, z} = 4'b0001;
endcase
endmodule
       
Alternative  model:  
 
module Prob_4_7(output w, x, y, z, input A, B, C, D);
assign w = A;
assign x = A ^ B);
assign y = x ^ C;
assign z = y ^ D;
endmodule
 

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   66  

4.8 (a) The 8-4-2-1 code (Table 1.5) and the BCD code (Table 1.4) are identical for digits 0 – 9.
 
      (b)  
   
8421 Gray
ABCD wxyz
CD C CD C
0000 0000 AB
00 01 11 10 00 01 11 10
0001 0001 m0 m1 m3 m2 m0 m1 m3 m2
0010 0011 00 00
0011 0010
m4 m5 m7 m6 m4 m5 m7 m6
0100 0110
01 01 1 1 1 1
0101 0111
0110 0101 m12 m13 m15 m14 B m12 m13 m15 m14 B
0111 0100 11 11
1000 1100 A A
m8 m9 m11 m10 m8 m9 m11 m10
1001 1101
10 1 1 10 1 1

D D
w = AB'C' x = AB'C' + A'B

CD C CD C
AB AB
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 01 1 1
m12 m13 m15 m14 B m12 m13 m15 m14 B
11 11 1
A A
m8 m9 m11 m10 m8 m9 m11 m10
10 10

D D
y = A'BD' + A'B'D z = A'C'D + BC'D + A'CD'
 

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4.9
CD C CD C
ABCD a b c d e f g AB AB
00 01 11 10 00 01 11 10
0000 1 1 1 1 1 1 0 m0 m1 m3 m2 m0 m1 m3 m2
0001 0 1 1 0 0 0 0 00 1 1 1 00 1 1 1 1
0010 1 1 0 1 1 0 1 m4 m5 m7 m6 m4 m5 m7 m6
0011 1 1 1 1 0 0 1 01 1 1 1 01 1 1
0100 0 1 1 0 0 1 1
m12 m13 m15 m14 B m12 m13 m15 m14 B
0101 1 0 1 1 0 1 1
0110 1 0 1 1 1 1 1 11 11
0111 1 1 1 0 0 0 0 A m8 m9 m11 m10 A m8 m9 m11 m10
1000 1 1 1 1 1 1 1 10 1 1 10 1 1
1001 1 1 1 1 0 1 1

D D
a = A'C + A'BD + B'C'D' + AB'C' b = A'B' + A'C'D' + A'CD + AB'C'
 
CD C CD C
AB 00 01 11 10 AB 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 1 00 1 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 1 1 01 1 1
m12 m13 m15 m14 B m12 m13 m15 m14 B
11 11
A m8 m9 m11 m10 A m8 m9 m11 m10
10 1 1 10 1 1

D D
c = A'B + A'D + B'C'D' + AB'C' d = A'CD' + A'B' C+ B'C'D' + AB'C' + A'BC'D  
 
CD C CD C CD C
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 00 1 1
m4 m5 m7 m6 m4 m5 m7 m6 m4 m5 m7 m6
01 1 01 1 1 1 01 1 1 1
m12 m13 m15 m14 B m12 m13 m15 m14 B m12 m13 m15 m14 B
11 11 11
A m8 m9 m11 m10 A m8 m9 m11 m10 A m8 m9 m11 m10
10 1 10 1 1 10 1 1

D D D
e = A'CD' + B'C'D' f = A'BC' + A'C'D' + A'BD + AB'C' g = A'CD' + A'B'C + A'BC' + AB'C'  
 

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4.10

ABCD wxyz CD C CD C
0000 0000 AB 00 01 11 10 00 01 11 10
0001 1111 m0 m1 m3 m2 m0 m1 m3 m2
0010 1110 00 1 1 1 00 1 1 1
0011 1101
m4 m5 m7 m6 m4 m5 m7 m6
0100 1100
0101 1011 01 1 1 1 1 01 1
0110 1001 m12 m13 m15 m14 B m12 m13 m15 m14 B
0111 1000 11 11 1
A m8 m9 m11 m10 A m8 m9 m11 m10
1000 1000
1001 0111 10 1 10 1 1 1
1010 0110
1011 0101
D D
1100 0100
w = A'(B + C + D) + AB'C'D' x = B'(C + D) + CB'D'
1101 0011
= A (B + C + D) = B (C + D)
1110 0010
1111 0001
CD C CD C
AB 00 01 11 10 AB 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 01 1 1
m12 m13 m15 m14 B m12 m13 m15 m14 B
11 1 1 11 1 1
A m8 m9 m11 m10 A m8 m9 m11 m10
10 1 1 10 1 1

D D
z=D
y = CD' + C'D = C D
For a 5-bit 2's complementer with input E and output v:

v=E (A + B + C + D)

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4.11 (a)

A3 A2 A1 A0
1

x y x y x y x y

Half Adder Half Adder Half Adder Half Adder

C S C S C S C S

Note: 5-bit output  

    (b)
A3 1 A2 1 A1 1 A0 1

x y x y x y x y

Full Adder Full Adder Full Adder Half Adder

B D B D B D B D

Note: To decrement the 4-bit number, add -1 to the number. In 2's complement format ( add Fh ) to
the number. An attempt to decrement 0 will assert the borrow bit. For waveforms, see solution to
Problem 4.52.

4.12

      (a)
x y B D
0 0 0 0
D = x'y + xy'
0 1 1 1
B = x'y
1 0 0 1
1 1 0 0  
  (b)
x y Bin B D
0 0 0 0 0
Diff = x y z
0 0 1 1 1
Bout = x'y + x'z + yz
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

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4.13 Sum C V

(a) 1101 0 1

(b) 0001 1 1

(c) 0100 1 0

(d) 1011 0 1

(e) 1111 0 0

4.14 xor AND OR XOR

10 + 5 + 5 + 10 = 30 ns

4.15 C4 = G3 + P3C3 = G3 + P3(G2 + P2G1 + P2P1G0 + P2P1P0C0)

= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0  

4.16 (a)
 
(C'G'i + p'i)' = (Ci + Gi)Pi = GiPi + PiCi
= AiBi(Ai + Bi) + PiCi
= A iB i + P i C i = G i + P iC i
= AiBi + (Ai + Bi)Ci = AiBi + AiCi + BiCi = Ci+1
(PiG'i) ⊕ Ci = (Ai + Bi)(AiBi)' ⊕ Ci = (Ai + Bi)(A'i + B'i) ⊕ Ci
= (A'iBi + AiB'i) ⊕ Ci = Ai ⊕ Bi ⊕ Ci = Si

(b)

Output of NOR gate = (A0 + B0)' = P'0

Output of NAND gate = (A0B0)' = G'0
S1 = (P0G'0) ⊕ C0
C1 = (C'0G'0 + P'0)' as defined in part (a)

4.17 (a)
(C'iG'i + P'i)' = (Ci + Gi)Pi = GiPi + PiCi = AiBi(Ai + Bi) + PiCi
= A iB i + P i C i = G i + P iC i
= AiBi + (Ai + Bi)Ci = AiBi + AiCi + BiCi = Ci+1

(PiG'i)⊕Ci = (Ai + Bi)(AiBi)'⊕Ci = (Ai + Bi)(A'i + B'i)⊕Ci

= (A'iBi + AiB'i)⊕Ci = Ai⊕Bi⊕Ci = Si
(b)
Output of NOR gate = (A0 + B0)' = P'0
Output of NAND gate = (A0B0)' = G'0

S0 = (P0G'0)⊕C0
C1 = (C'0G'0 + P'0)' as defined in part (a)

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4.18
Inputs Outputs
ABCD wxyz
0000 1001
d(A, b, c, d) = Σ(10, 11, 12, 13, 14, 15)
0001 1000
0010 0111
0011 0110
0100 0101
0101 0100
0110 0011
0111 0010
1000 0001
1001 0000

CD C CD C
AB AB
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 01 1 1
m12 m13 m15 m14 B m12 m13 m15 m14 B
11 x x x x 11 x x x x
A m8 m9 m11 m10 A m8 m9 m11 m10
10 x x 10 x x

D D
w = A'B'C' x = BC' + B'C = B C
CD C CD C
00 01 11 10 AB 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 01 1 1 1
m12 m13 m15 m14 B m12 m13 m15 m14 B
11 x x x x 11 x x x x
m8 m9 m11 m10 A m8 m9 m11 m10
10 x x 10 1 x x

D D
y=C z = D'  
 
 
 

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4.19

Mode = 0 FOR Add

B3 B2 B1 B0 Mode = 1 for Subtract

9's Complementer
(See Problem 4.18)

Select
Select = 1 Select = 0
A3 A2 A1 A0
Quadruple 2 x 1 MUX
Cin

BCD Adder (See Fig. 4.14)

 

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4.20 Combine the following circuit with the 4-bit binary multiplier circuit of Fig. 4.16.

C6 C5 C4 C3 C2 C1 C0
A3
B3 B2 B1 B0

Cout
4-bit Adder Augend

D7 D6 D5 D4 D3 D2 D1 D0
 
4.21
A0
B0

A1
B1
x
A2
B2
A3
B3

x = (A0 B0)'(A1 B1)'(A2 B2)'(A3 B3)'

 
4.22
XS-3 Binary
ABCD wxyz
0011 0000
0100 0001
0101 0010
0110 0011
0111 0100
1000 0101
1001 0110
1010 0111
1011 1000
1100 1001

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CD C CD C
AB 00 01 11 10 AB 00 01 11 10
m0 m1 m3 x m0 m1 m3 m2
00 x x 00 X X X
m4 m5 m7 m6 m4 m5 m7 m6
01 01 1
m12 m13 m15 m14 B m12 m13 m15 m14 B
11 1 x x x 11 x x x
A m8 m9 m11 m10 A m8 m9 m11 m10
10 1 10 1 1 1

D D
w = AB + ACD x = B'C' + B'D' + BCD
y = C'D + CD'
z = D'
4.23
D0 = A1'A0' = (A1 + A0)' (NOR) D0' = (A1'A0')' (NAND)
D1 = A1'A0 = (A1 + A0')' (NOR) D1' = (A1'A0)' (NAND)
D2 = A1A0' = (A1' + A0)' (NOR) D2' = (A1A0')' (NAND)
D3 = A1A0 = (A1' + A0)' (NOR) D0' = (A1A0)' (NAND)

A1
A0 D0 = (A1 + A0 + E' )' = A'1A'0E

D1 = (A1 + A'0 + E' )' = A'1A0E

D2 = (A'1 + A0 + E' ) = A1A'0E

D3 = (A'1 + A'0 + E' )' = A1A0E

E

E A1 A0

D0' = (A1 + A0 + E' ) = (A'1A'0E)'

D0
D1' = (A1 + A'0 + E' ) = (A'1A0E)'
D1
D2' = (A1' + A0 + E' ) = (A1A0'E)'
D2
D3' = (A1' + A0' + E' ) = (A1A0E)'
D3

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4.24
CD C
AB 00 01 11 10
m0 m1 m3 x
00 D0 D1 D3 D2
Inputs: A, B, C, D
Outputs: D0, D1, ... D9 m4 m5 m7 m6
D0 = A'B'C'D' D5 = BC'D 01 D4 D5 D7 D6
D1 = A'B'C'D D6 = BCD' m12 m13 m15 m14 B
D2 = B'CD' D7 = BCD 11 x x x x
D3 = B'CD D8 = AD'
D4 = BC'D' D9 = AD A m8 m9 m10
m11
10 D8 D9 x x

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4.25
A0 3x8 8
A1 D0 - D7
A2 Decoder
E

8
3x8
Decoder D8 - D15
E

0
A3 20
2x4 1
Decoder 2 8
3x8
A4 21 D16 - D23
3 Decoder
E E

3x8 8
D24 - D31
Decoder
E

4.26
A0 20 2x4 4
D0 - D3
A1 2 1 Decoder
E

20 2x4
4
1 Decoder D4 - D7
2 E

0
A2 20
2x4 1
Decoder 2 20 4
2x4
A3 21 D8 - D11
3 2 1 Decoder
E E

20 2x4 4
D12 - D15
2 1 Decoder
E

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4.27

F1 = Σ(1, 4, 6)
0
1
A 2 3x8 2
2

B 21 Decoder
3   F2 = Σ(3, 5)
C 20 4
5
6
7

F3 = Σ(2, 4, 6, 7)

4.28 (a)

F1 = x(y + y')z + x'yz' =xyx + xy'z + x'yz' = Σ(2, 5, 7)

F2 = xy'z' + x'y = xy'z' + x'yz + x'yz' = Σ(2, 3, 4)
F3 = x'y'z' + xy(z + z') =x'y'z' + xyz + xyz' = Σ(0, 6, 7)

0
F1 = Σ((2, 5, 7)
1

x 22 3 x 8 2
y 21 Decoder 3
4 F1 = Σ((2, 3, 4)
z 20
5
6
7 F1 = Σ(0, 6, 7)

(b)

   

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4.29
D1D0 D1
D3D2 00 01 11 10
m0 m1 m3 m2

Inputs Outputs 00 1 1 1
D3 D2 D1 D0 x y V m4 m5 m7 m6
01 1 1 1 1
0 0 0 0 x x 0 D2
m12 m13 m15 m14
x x x 1 0 0 1
x x 1 0 0 1 1 11 1 1 1 1
x 1 0 0 1 0 1 D3 m8 m9 m11 m10
1 0 0 0 1 1 1 10 1 1 1 1

D0
V = D0 + D1 + D2 + D3

D1D0 D1D0 D1
D3D2 00 01 11 10 D3D2 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 x 00 x 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 01 1
D2 D2
m12 m13 m15 m14 m12 m13 m15 m14
11 1 11 1
m8 m9 m11 m10 D3 m8 m9 m11 m10
10 1 10 1 1

D0 D0
x = D1'D0'
y = D0'D2' + D1D0'

D0
x
D1

y
D2
D0
D1
D2 V
D3  
 

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4.30
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 x y z V

0 0 0 0 0 0 0 0 x x x 0
1 0 0 0 0 0 0 0 0 0 0 1
x 1 0 0 0 0 0 0 0 0 1 1
x x 1 0 0 0 0 0 0 1 0 1
x x x 1 0 0 0 0 0 1 1 1
x x x x 1 0 0 0 1 0 0 1
x x x x x 1 0 0 1 0 1 1
x x x x x x 1 0 1 0 0 1
x x x x x x x 1 1 1 1 1

If D2 = 1, D6 = 1, all others = 0
Output xyz = 100 and V = 1  
4.31

s0 s0
s1 s1
s2 s2
s3 0 0
1 1
8x1
2 2
MUX
3 3
4 4
5 5
6 6
7 7
s
2x1 y
0
MUX
1
s0
s1
s2
8 0
9 1
8x1
10 2
MUX
11 3
12 4
13 5
14 6
15 7
 
 

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4.32 (a) F = Σ (0, 2, 5, 8, 10, 14)

 

Mux input line (ABC)

Value
Inputs F = Σ(0, 2, 5, 8, 10, 14)
ABCD
000 0 0 0 1 F = D'
000 1 0 1 0
001 0 1 2 1 A s0
F = D'
001 1 1 3 0 B s1
010 0 2 4 0 C s2
F=D
010 1 2 5 1 0
011 0 3 6 0F=0 1 F
011 1 3 7 0 8x1
D 2 Y
100 0 4 8 1 MUX
F = D' 3
100 1 4 9 0 4
101 0 5 10 1 5
F = D'
101 1 5 11 0 0 6
110 0 6 12 0F=0 7
110 1 6 13 0
111 0 7 14 1
F = D'
111 1 7 15 0  
 

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(b)

Mux input line (ABC)

F = Π(2, 6, 11) = (A' +B' + C + D')(A' +B + C + D')(A +B' + C + D)
F' = (A' +B' + C + D')' + (A' +B + C + D')' + (A +B' + C + D)'
F' = (ABC'D) + (AB'C'D) + (A'BC'D') = Σ(13, 9, 4)
F = Σ(0, 1, 2, 3, 5, 6, 7, 8, 10, 11, 12, 14, 15)

Value
Inputs
ABCD
000 0 0 0 1F = 1
000 1 0 1 1
001 0 1 2 1 A s0
F=1
001 1 1 3 1 B s1
010 0 2 4 0 C s2
F=D
010 1 2 5 1 0
011 0 3 6 1F = 1 1 F
011 1 3 7 1 8x1
2 Y
100 0 4 8 1 MUX
F = D' 3
100 1 4 9 0 D 4
101 0 5 10 1 5
F=1 1
101 1 5 11 1 6
110 0 6 12 1F = D' 7
110 1 6 13 0
111 0 7 14 1
F=1
111 1 7 15 1

4.33
x 0
S(x, y, z) = Σ(1, 2, 4, 7) 1
C(x, y, z) = Σ(3, 5, 6, 7) 2
S
3
Dual
S I0 I1 I2 I3 I0 I1 I2 I3 4x1 Y
C
MUX
x' 0 1 2 3 x' 0 1 2 3 0 0
C
x 4 5 6 7 x 4 5 6 7 1
x x' x' x 0 x' x' 1 2
1 3

y z

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4.34 (a)
A B C D F CD C
AB 00 01 11 10
I3 = 1 0 1 1 0 1 m0 m1 m3 m2
0 1 1 1 1 00 1
1 0 1 0 1
I5 = 1 m4 m5 m7 m6
1 0 1 1 1
0 0 0 0 0 01 1 1
I0 = D B
0 0 0 1 1 m12 m13 m15 m14
1 0 0 0 0 11 1
I4 = D 1 0 0 1 1 A m8 m9 m11 m10
1 1 0 0 1
I6 = D' 10 1 1 1
1 1 0 1 0

D
Other minterms = 0
since I1 = I2 = I7 = 0 F(A, B, C, D) = Σ(1, 6, 7, 9, 10, 11, 12)
 
      (b)
A B C D F CD C
AB
00 01 11 10
I1 = 0 0 0 1 0 0 m0 m1 m3 m2
0 0 1 1 0 00 1 1
I2 = 0 0 1 0 0 0 m4 m5 m7 m6
0 1 0 1 0 01 1 1
0 1 1 0 1
I3 = 1 B
0 1 1 1 1 m12 m13 m15 m14
1 1 1 0 1 11 1 1 1
I7 = 1
1 1 1 1 1 A m8 m9 m11 m10
I4 = D 1 0 0 0 0 10 1
1 0 0 1 1
0 0 0 0 1
I0 = D' 0 0 0 1 0 D
1 1 0 0 1
I6= D' 1 1 0 1 0 F(A, B, C, D) = Σ(0, 1, 6, 7, 9, 13, 14, 15)
Other minterms = 0
since I1 = I2 = 0
 
 
4.35 (a)
Inputs
ABCD F
0000 0
0001 1 AB = 00
0010 0 F=D A s0
0011 1 s1
B
0100 1
AB = 01
0101 0 0 4x1
F = C'D'
0110 0 C 1 MUX
= (C + D)' D F
0111 0 Y
1000 0 2
1001 0 AB = 10 3
1010 0 F = CD
1011 1 1
1100 1
AB = 11
1101 1
F=1
1110 1
1111 1  

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(b) F = S(1, 2, 5, 7, 8, 10, 11, 13, 15)

 
Inputs
ABCD F2 = Σ(1, 2, 5, 7, 8, 10, 11, 13, 15)
0000 0 A
0001 1 AB = 00 B
0010 1 F = C'D + CD' s0
0011 0 s1
0100 0 C
AB = 01
0101 1 0 4x1 F2
F = C'D + CD = D Y
0110 0 D 1 MUX
0111 1
1000 1 2
1001 0 3
1010 1 AB = 10
1011 1 F = C'D' + C'D + CD = C'D' + D
1100 0
AB = 11
1101 1
F=D
1110 0
1111 1  
4.36
      module priority_encoder_gates (output x, y, V, input D0, D1, D2, D3); // V2001
wire w1, D2_not;
not (D2_not, D2);
or (x, D2, D3);
or (V, D0, D1, x);
and (w1, D2_not, D1);
or (y, D3, w1);
endmodule
         
      Note:  See  Problem  4.45  for  testbench)  
 
4.37
module Add_Sub_4_bit (
output [3: 0] S,
output C,
input [3: 0] A, B,
input M
);
wire [3: 0] B_xor_M;
wire C1, C2, C3, C4;
assign C = C4; // output carry
xor (B_xor_M[0], B[0], M);
xor (B_xor_M[1], B[1], M);
xor (B_xor_M[2], B[2], M);
xor (B_xor_M[3], B[3], M);
// Instantiate full adders
full_adder FA0 (S[0], C1, A[0], B_xor_M[0], M);
full_adder FA1 (S[1], C2, A[1], B_xor_M[1], C1);
full_adder FA2 (S[2], C3, A[2], B_xor_M[2], C2);
full_adder FA3 (S[3], C4, A[3], B_xor_M[3], C3);
endmodule

module full_adder (output S, C, input x, y, z); // See HDL Example 4.2

wire S1, C1, C2;
// instantiate half adders
half_adder HA1 (S1, C1, x, y);
half_adder HA2 (S, C2, S1, z);
or G1 (C, C2, C1);
endmodule

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   84  

 
module half_adder (output S, C, input x, y); // See HDL Example 4.2
xor (S, x, y);
and (C, x, y);
endmodule  

module t_Add_Sub_4_bit ();

wire [3: 0] S;
wire C;
reg [3: 0] A, B;
reg M;

Add_Sub_4_bit M0 (S, C, A, B, M);

initial #100 $finish;

initial fork
#10 M = 0;
#10 A = 4'hA;
#10 B = 4'h5;
#50 M = 1;
#70 B = 4'h3;
join
endmodule

Name 0 50 100

A[3:0] x a
B[3:0] x 5 3
M

S[3:0] x f 5 7
C
 
4.38
module quad_2x1_mux ( // V2001
input [3: 0] A, B, // 4-bit data channels
input enable_bar, select, // enable_bar is active-low)
output [3: 0] Y // 4-bit mux output  
);
//assign Y = enable_bar ? 0 : (select ? B : A); // Grounds output
assign Y = enable_bar ? 4'bzzzz : (select ? B : A); // Three-state output
endmodule
//  Note  that  this  mux  grounds  the  output  when  the  mux  is  not  active.  
 
module t_quad_2x1_mux ();
reg [3: 0] A, B, C; // 4-bit data channels
reg enable_bar, select; // enable_bar is active-low)
wire [3: 0] Y; // 4-bit mux

quad_2x1_mux M0 (A, B, enable_bar, select, Y);

initial #200 $finish;

initial fork
enable_bar = 1;
select = 1;
A = 4'hA;
B = 4'h5;
#10 select = 0; // channel A

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   85  

#20 enable_bar = 0;
#30 A = 4'h0;
#40 A = 4'hF;
#50 enable_bar = 1;
#60 select = 1; // channel B
#70 enable_bar = 0;
#80 B = 4'h00;
#90 B = 4'hA;
#100 B = 4'hF;
#110 enable_bar = 1;
#120 select = 0;
#130 select = 1;
#140 enable_bar = 1;
join
endmodule
Name 0 70 140

A[3:0] a 0 f
B[3:0] 5 0 a f
enable_bar
select

Y[3:0] 0 a 0 f 0 5 0 a f 0

With three-state output:

Name 0 70 140

A[3:0] a 0 f
B[3:0] 5 0 a f
enable_bar
select

Y[3:0] z a 0 f z 5 0 a f z

4.39 // Verilog 1995

module Compare (A, B, Y);
input [3: 0] A, B; // 4-bit data inputs.
output [5: 0] Y; // 6-bit comparator output.
reg [5: 0] Y; // EQ, NE, GT, LT, GE, LE

always @ (A or B)
if (A==B) Y = 6'b10_0011; // EQ, GE, LE
else if (A < B) Y = 6'b01_0101; // NE, LT, LE
else Y = 6'b01_1010; // NE, GT, GE
endmodule

// Verilog 2001, 2005

module Compare (input [3: 0] A, B, output reg [5:0] Y);

always @ (A, B)
if (A==B) Y = 6'b10_0011; // EQ, GE, LE
else if (A < B) Y = 6'b01_0101; // NE, LT, LE
else Y = 6'b01_1010; // NE, GT, GE
endmodule

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All  rights  reserved.  
   86  

 
4.40
module Prob_4_40 (
output [3: 0] sum_diff, output carry_borrow,
input [3: 0] A, B, input sel_diff
);

always @(sel_diff, A, B) {carry_borrow, sum_diff} = sel_diff ? A - B : A + B;

endmodule

module t_Prob_4_40;
wire [3: 0] sum_diff;
wire carry_borrow;
reg [3:0] A, B;
reg sel_diff;

integer I, J, K;
Prob_4_40 M0 ( sum_diff, carry_borrow, A, B, sel_diff);
initial #4000 $finish;
initial begin
for (I = 0; I < 2; I = I + 1) begin
sel_diff = I;
for (J = 0; J < 16; J = J + 1) begin
A = J;
for (K = 0; K < 16; K = K + 1) begin B = K; #5 ; end
end
end
end
endmodule
   
4.41
module Prob_4_41 (
output reg [3: 0] sum_diff, output reg carry_borrow,
input [3: 0] A, B, input sel_diff
);

always @ (A, B, sel_diff)

{carry_borrow, sum_diff} = sel_diff ? A - B : A + B;

endmodule

module t_Prob_4_41;
wire [3: 0] sum_diff;
wire carry_borrow;
reg [3:0] A, B;
reg sel_diff;

integer I, J, K;
Prob_4_46 M0 ( sum_diff, carry_borrow, A, B, sel_diff);
initial #4000 $finish;
initial begin
for (I = 0; I < 2; I = I + 1) begin
sel_diff = I;
for (J = 0; J < 16; J = J + 1) begin
A = J;
for (K = 0; K < 16; K = K + 1) begin B = K; #5 ; end
end
end
end
endmodule

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All  rights  reserved.  
   87  

 
780 810 840 870
Name

sel_diff

A[3:0] 9 a b

B[3:0] c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2

sum_diff[3:0] 5 6 7 8 a b c d e f 0 1 2 3 4 5 6 7 8 9 b c d

carry_borrow

 
 
2064 2094 2124 2154
Name

sel_diff

A[3:0] 9 a b

B[3:0] d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2

sum_diff[3:0] c b a 9 8 7 6 5 4 3 2 1 0 f e d c b a 9

carry_borrow

 
4.42 (a)
module Xs3_Gates (input A, B, C, D, output w, x, y, z);
wire B_bar, C_or_D_bar;
wire CD, C_or_D;
or (C_or_D, C, D);
not (C_or_D_bar, C_or_D);
not (B_bar, B);
and (CD, C, D);
not (z, D);
or (y, CD, C_or_D_bar);
and (w1, C_or_D_bar, B);
and (w2, B_bar, C_or_D);
and (w3, C_or_D, B);
or (x, w1, w2);
or (w, w3, A);
endmodule
(b)
module Xs3_Dataflow (input A, B, C, D, output w, x, y, z);
assign {w, x, y, z} = {A, B, C, D} + 4'b0011;
endmodule
(c)
module Xs3_Behavior_95 (A, B, C, D, w, x, y, z);
input A, B, C, D;
output w, x, y, z;
reg w, x, y, z;

always @ (A or B or C or D) begin {w, x, y, z} = {A, B, C, D} + 4'b0011; end

endmodule

module Xs3_Behavior_01 (input A, B, C, D, output reg w, x, y, z);

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   88  

always @ (A, B, C, D) begin {w, x, y, z} = {A, B,C, D} + 4'b0011; end

endmodule
   
module t_Xs3_Converters ();
reg A, B, C, D;
wire w_Gates, x_Gates, y_Gates, z_Gates;
wire w_Dataflow, x_Dataflow, y_Dataflow, z_Dataflow;
wire w_Behavior_95, x_Behavior_95, y_Behavior_95, z_Behavior_95;
wire w_Behavior_01, x_Behavior_01, y_Behavior_01, z_Behavior_01;
integer k;
wire [3: 0] BCD_value;
wire [3: 0] Xs3_Gates = {w_Gates, x_Gates, y_Gates, z_Gates};
wire [3: 0] Xs3_Dataflow = {w_Dataflow, x_Dataflow, y_Dataflow, z_Dataflow};
wire [3: 0] Xs3_Behavior_95 = {w_Behavior_95, x_Behavior_95, y_Behavior_95, z_Behavior_95};
wire [3: 0] Xs3_Behavior_01 = {w_Behavior_01, x_Behavior_01, y_Behavior_01, z_Behavior_01};

assign BCD_value = {A, B, C, D};

Xs3_Gates M0 (A, B, C, D, w_Gates, x_Gates, y_Gates, z_Gates);
Xs3_Dataflow M1 (A, B, C, D, w_Dataflow, x_Dataflow, y_Dataflow, z_Dataflow);
Xs3_Behavior_95 M2 (A, B, C, D, w_Behavior_95, x_Behavior_95, y_Behavior_95, z_Behavior_95);
Xs3_Behavior_01 M3 (A, B, C, D, w_Behavior_01, x_Behavior_01, y_Behavior_01, z_Behavior_01);

initial #200 $finish;

initial begin
k = 0;
repeat (10) begin {A, B, C, D} = k; #10 k = k + 1; end
end
endmodule

Name 0 30 60 90

k 0 1 2 3 4 5 6 7 8 9
A
B
C
D

BCD_value[3:0] 0 1 2 3 4 5 6 7 8 9
w_Gates
x_Gates
y_Gates
z_Gates
Xs3_Gates[3:0] 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100
Xs3_Gates[3:0] 3 4 5 6 7 8 9 a b c
Xs3_Dataflow[3:0] 3 4 5 6 7 8 9 a b c
Xs3_Behavior_95[3:0] 3 4 5 6 7 8 9 a b c
Xs3_Behavior_01[3:0] 3 4 5 6 7 8 9 a b c

4.43 Two-channel mux with 2-bit data paths, enable, and three-state output.

4.44
module ALU (output reg [7: 0] y, input [7: 0] A, B, input [2: 0] Sel);
always @ (A, B, Sel) begin
y = 0;
case (Sel)
3'b000: y = 8'b0;
3'b001: y = A & B;
3'b010: y = A | B;
3'b011: y = A ^ B;
3'b100: y = A + B;

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   89  

3'b101: y = A - B;
3'b110: y = ~A;
3'b111: y = 8'hFF;
endcase
end

endmodule

module t_ALU ();

wire[7: 0]y;
reg [7: 0] A, B;
reg [2: 0] Sel;

ALU M0 (y, A, B, Sel);

initial #200 $finish;

initial fork
#5 begin A = 8'hAA; B = 8'h55; end // Expect y = 8'd0
#10 begin Sel = 3'b000; A = 8'hAA; B = 8'h55; end // y = 8'b000 Expect y = 8'd0
#20 begin Sel = 3'b001; A = 8'hAA; B = 8'hAA; end // y = A & B Expect y = 8'hAA = 8'1010_1010
#30 begin Sel = 3'b001; A = 8'h55; B = 8'h55; end // y = A & B Expect y = 8'h55 = 8'b0101_0101
#40 begin Sel = 3'b010; A = 8'h55; B = 8'h55; end // y = A | B Expect y = 8'h55 = 8'b0101_0101
#50 begin Sel = 3'b010; A = 8'hAA; B = 8'hAA; end // y = A | B Expect y = 8'hAA = 8'b1010_1010
#60 begin Sel = 3'b011; A = 8'h55; B = 8'h55; end // y = A ^ B Expect y = 8'd0
#70 begin Sel = 3'b011; A = 8'hAA; B = 8'h55; end // y = A ^ B Expect y = 8'hFF = 8'b1111_1111
#80 begin Sel = 3'b100; A = 8'h55; B = 8'h00; end // y = A + B Expect y = 8'h55 = 8'b0101_0101
#90 begin Sel = 3'b100; A = 8'hAA; B = 8'h55; end // y = A + B Expect y = 8'hFF = 8'b1111_1111
#110 begin Sel = 3'b101; A = 8'hAA; B = 8'h55; end // y = A – B Expect y = 8'h55 = 8'b0101_0101
#120 begin Sel = 3'b101; A = 8'h55; B = 8'hAA; end // y = A – B Expect y = 8'hab = 8'b1010_1011
#130 begin Sel = 3'b110; A = 8'hFF; end // y = ~A Expect y = 8'd0
#140 begin Sel = 3'b110; A = 8'd0; end // y = ~A Expect y = 8'hFF = 8'b1111_1111
#150 begin Sel = 3'b110; A = 8'hFF; end // y = ~A Expect y = 8'd0
#160 begin Sel = 3'b111; end // y = 8'hFF Expect y = 8'hFF = 8'b1111_1111
join
endmodule

Name 0 60 120 180

Sel[2:0] 001 010 011 100 101 110 111

A[7:0] aa 55 aa 55 aa 55 aa 55 ff 00 ff
B[7:0] 55 aa 55 aa 55 00 55 aa

y[7:0] 00 aa 55 aa 00 ff 55 ff 55 ab 00 ff 00 ff

Note that the subtraction operator performs 2's complement subtraction. So 8'h55 – 8'hAA adds the 2's
complement of 8'hAA to 8'h55 and gets 8'hAB. The sign bit is not included in the model, but hand
calculation shows that the 9th bit is 1, indicating that the result of the operation is negative. The magnitude
of the result can be obtained by taking the 2's complement of 8'hAB.

4.45
module priority_encoder_beh (output reg X, Y, V, input D0, D1, D2, D3); // V2001
always @ (D0, D1, D2, D3) begin
X = 0;
Y = 0;
V = 0;
casex ({D0, D1, D2, D3})

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All  rights  reserved.  
   90  

4'b0000: {X, Y, V} = 3'bxx0;

4'b1000: {X, Y, V} = 3'b001;
4'bx100: {X, Y, V} = 3'b011;
4'bxx10: {X, Y, V} = 3'b101;
4'bxxx1: {X, Y, V} = 3'b111;
default: {X, Y, V} = 3'b000;
endcase
end
endmodule

module t_priority_encoder_beh (); // V2001

wire X, Y, V;
reg D0, D1, D2, D3;
integer k;

priority_encoder_beh M0 (X, Y, V, D0, D1, D2, D3);

initial #200 $finish;

initial begin
k = 32'bx;
#10 for (k = 0; k <= 16; k = k + 1) #10 {D0, D1, D2, D3} = k;
end
endmodule

Name 0 60 120 180

k 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

D0
D1
D2
D3

X
Y
V

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   91  

4.46 (a)
F = Σ(0, 2, 5, 7, 11, 14)
See code below.

(b) From prob 4.32:

F = Π (3, 8, 12) = (A' + B' + C + D)(A + B' + C' + D')(A + B + C' + D')
F' = ABC'D' + A'BCD + A'B'CD = Σ(12, 7, 3)
F = Σ(0, 1, 2, 4, 5, 6, 8, 9, 10, 11, 13, 14, 15)

module Prob_4_46a (output F, input A, B, C, D);

assign F = (~A&~B&~C&~D) | (~A&~B&C&~D) | (~A&B&~C&D) | (~A&B&C&D) | (A&~B&C&D) |
(A&B&C&~D);
endmodule
 
 
module Prob_4_46b (output F, input A, B, C, D);
assign F = (~A&~B&~C&~D) | (~A&~B&~C&D) | (~A&~B&C&~D) | (~A&B&~C&~D) | (~A&B&~C&D) |
(~A&B&C&~D) | (A&~B&~C&~D) | (A&~B&~C&D) | (A&~B&C&~D) | (A&~B&C&D) | (A&B&~C&D) |
(A&B&C&~D) | (A&B&C&D);
endmodule
 
module t_Prob_4_46a ();
wire F_a, F_b;
reg A, B, C, D;
integer k;
Prob_4_46a M0 (F_a, A, B, C, D);
Prob_4_46b M1 (F_b, A, B, C, D);

   initial  #200  $finish;  

initial begin
k = 0;
#10 repeat (15) begin {A, B, C, D} = k; #10 k = k + 1; end
end
endmodule  

Name 0 60 120 180

k 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

D0
D1
D2
D3

X
Y
V

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   92  

4.47
module Add_Sub_4_bit_Dataflow (
output [3: 0] S,
output C, V,
input [3: 0] A, B,
input M
);
wire C3;  

assign {C3, S[2: 0]} = A[2: 0] + ({M, M, M} ^ B[2: 0]) + M;

assign {C, S[3]} = A[3] + M ^ B[3] + C3;
assign V = C ^ C3;
endmodule

module t_Add_Sub_4_bit_Dataflow ();

wire [3: 0] S;
wire C, V;
reg [3: 0] A, B;
reg M;

Add_Sub_4_bit_Dataflow M0 (S, C, V, A, B, M);

initial #100 $finish;

initial fork
#10 M = 0;
#10 A = 4'hA;
#10 B = 4'h5;
#50 M = 1;
#70 B = 4'h3;
join
endmodule
Name 0 50 100

A[3:0] x a
B[3:0] x 5 3
M

S[3:0] x f 5 7
C

4.48
module ALU_3state (output [7: 0] y_tri, input [7: 0] A, B, input [2: 0] Sel, input En);
reg [7: 0] y;
assign y_tri = En ? y: 8'bz;
always @ (A, B, Sel) begin
y = 0;
case (Sel)
3'b000: y = 8'b0;
3'b001: y = A & B;
3'b010: y = A | B;
3'b011: y = A ^ B;
3'b100: y = A + B;
3'b101: y = A - B;
3'b110: y = ~A;
3'b111: y = 8'hFF;
endcase
end

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   93  

endmodule

module t_ALU_3state ();

wire[7: 0] y;
reg [7: 0] A, B;
reg [2: 0] Sel;
reg En;

ALU_3state M0 (y, A, B, Sel, En);

initial #200 $finish;

initial fork
#5 En = 1;

#5 begin A = 8'hAA; B = 8'h55; end // Expect y = 8'd0

#10 begin Sel = 3'b000; A = 8'hAA; B = 8'h55; end // y = 8'b000 Expect y = 8'd0
#20 begin Sel = 3'b001; A = 8'hAA; B = 8'hAA; end // y = A & B Expect y = 8'hAA = 8'1010_1010
#30 begin Sel = 3'b001; A = 8'h55; B = 8'h55; end // y = A & B Expect y = 8'h55 = 8'b0101_0101
#40 begin Sel = 3'b010; A = 8'h55; B = 8'h55; end // y = A | B Expect y = 8'h55 = 8'b0101_0101
#50 begin Sel = 3'b010; A = 8'hAA; B = 8'hAA; end // y = A | BExpect y = 8'hAA = 8'b1010_1010
#60 begin Sel = 3'b011; A = 8'h55; B = 8'h55; end // y = A ^ B Expect y = 8'd0
#70 begin Sel = 3'b011; A = 8'hAA; B = 8'h55; end // y = A ^ B Expect y = 8'hFF = 8'b1111_1111
#80 begin Sel = 3'b100; A = 8'h55; B = 8'h00; end // y = A + B Expect y = 8'h55 = 8'b0101_0101
#90 begin Sel = 3'b100; A = 8'hAA; B = 8'h55; end // y = A + B Expect y = 8'hFF = 8'b1111_1111
#100 En = 0;
#115 En = 1;
#110 begin Sel = 3'b101; A = 8'hAA; B = 8'h55; end // y = A – B Expect y = 8'h55 = 8'b0101_0101
#120 begin Sel = 3'b101; A = 8'h55; B = 8'hAA; end // y = A – B Expect y = 8'hab = 8'b1010_1011
#130 begin Sel = 3'b110; A = 8'hFF; end // y = ~A Expect y = 8'd0
#140 begin Sel = 3'b110; A = 8'd0; end // y = ~A Expect y = 8'hFF = 8'b1111_1111
#150 begin Sel = 3'b110; A = 8'hFF; end // y = ~A Expect y = 8'd0
#160 begin Sel = 3'b111; end // y = 8'hFF Expect y = 8'hFF = 8'b1111_1111
join
endmodule
4.49
// See Problem 4.1
module Problem_4_49_Gates (output F1, F2, input A, B, C, D);
wire A_bar = !A;
wire B_bar = !B;

and (T1, B_bar, C);

and (T2, A_bar, B);
or (T3, A, T1);
xor (T4, T2, D);
or (F1, T3, T4);
or (F2, T2, D);
endmodule

module Problem_4_49_Boolean_1 (output F1, F2, input A, B, C, D);

wire A_bar = !A;
wire B_bar = !B;
wire T1 = B_bar && C;
wire T2 = A_bar && B;
wire T3 = A || T1;
wire T4 = T2 ^ D;
assign F1 = T3 || T4;
assign F2 = T2 || D;
endmodule

module Problem_4_49_Boolean_2(output F1, F2, input A, B, C, D);

assign F1 = A || (!B && C) || (B && (!D)) || (!B && D);
assign F2 = ((!A) && B) || D;
endmodule

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All  rights  reserved.  
   94  

module t_Problem_4_49;
reg A, B, C, D;
wire F1_Gates, F2_Gates;
wire F1_Boolean_1, F2_Boolean_1;
wire F1_Boolean_2, F2_Boolean_2;

Problem_4_48_Gates M0 (F1_Gates, F2_Gates, A, B, C, D);

Problem_4_48_Boolean_1 M1 (F1_Boolean_1, F2_Boolean_1, A, B, C, D);
Problem_4_48_Boolean_2 M2 (F1_Boolean_2, F2_Boolean_2, A, B, C, D);

initial #100 $finish;

integer K;
initial begin
for (K = 0; K < 16; K = K + 1) begin {A, B, C, D} = K; #5; end
end
endmodule  

4.50 (a) 84-2-1 to BCD code converter

//  See  Problem  4.8  and  Table  1.5.  
//  Verilog  1995  
 
// module Prob_4_50a (Code_BCD, Code84_m2_m1);
// output [3: 0] Code_BCD;
// input [3:0];
// reg [3: 0] Code_BCD;
// ...

// Verilog 2001, 2005

module Prob_4_50a (output reg [3: 0] Code_BCD, input [3: 0] Code_84_m2_m1);

always @ (Code_84_m2_m1) // always @ (A or B or C or D)

case (Code_84_m2_m1)
4'b0000: Code_BCD = 4'b0000; // 0
4'b0111: Code_BCD = 4'b0001; // 1
4'b0110: Code_BCD = 4'b0010; // 2
4'b0101: Code_BCD = 4'b0011; // 3
4'b0100: Code_BCD = 4'b0100; // 4
4'b1011: Code_BCD = 4'b0101; // 5
4'b1010: Code_BCD = 4'b0110; // 6
4'b1001: Code_BCD = 4'b0111; // 7
4'b1000: Code_BCD = 4'b1000; // 8
4'b1111: Code_BCD = 4'b1001; // 9

4'b0001: Code_BCD = 4'b1010; // 10

4'b0010: Code_BCD = 4'b1011; // 11
4'b0011: Code_BCD = 4'b1100; // 12
4'b1100: Code_BCD= 4'b1101; // 13
4'b1101: Code_BCD = 4'b1110; // 14
4'b1110: Code_BCD = 4'b1111; // 15
endcase
endmodule

module t_Prob_4_50a;
wire [3: 0] Code_BCD;
reg [3: 0]; Code_84_m2_m1;
integer K;

Prob_4_50a M0 ( Code_BCD, Code_84_m2_m1); // Unit under test (UUT)

initial #100 $finish;

initial begin
for (K = 0; K < 16; K = K + 1) begin Code_84_m2_m1 = K; #5 ; end
end

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All  rights  reserved.  
   95  

endmodule

(b) 84-2-1 to Gray code converter

module Prob_4_50b (output reg [3: 0] Code_BCD, input [3: 0] Code_84_m2_m1);

always @ (Code_84_m2_m1)
case (Code_84_m2_m1)
4'b0000: Code_Gray = 4'b0000; // 0
4'b0111: Code_Gray = 4'b0001; // 1
4'b0110: Code_Gray = 4'b0011; // 2
4'b0101: Code_Gray = 4'b0010; // 3
4'b0100: Code_Gray = 4'b0110; // 4
4'b1011: Code_Gray = 4'b0111; // 5
4'b1010: Code_Gray = 4'b0101; // 6
4'b1001: Code_Gray = 4'b0100; // 7
4'b1000: Code_Gray = 4'b1100; // 8
4'b1111: Code_Gray = 4'b1101; // 9

4'b0001: Code_Gray = 4'b1111; // 10

4'b0010: Code_Gray = 4'b1110; // 11
4'b0011: Code_Gray = 4'b1010; // 12
4'b1100: Code_Gray= 4'b1011; // 13
4'b1101: Code_Gray = 4'b1001; // 14
4'b1110: Code_Gray = 4'b1000; // 15
endcase
endmodule

module t_Prob_4_50b;
wire [3: 0] Code_Gray;
reg [3: 0] Code_84_m2_m1;
integer K;

Prob_4_50b M0 (Code_Gray, Code_84_m2_m1); // Unit under test (UUT)

initial #100 $finish;

initial begin
for (K = 0; K < 16; K = K + 1) begin Code_84_m2_m1 = K; #5 ; end
end
endmodule

4.51 Assume that that the LEDs are asserted when the output is high.

module Seven_Seg_Display_V2001 (
output reg [6: 0] Display,
input [3: 0] BCD
);

// abc_defg
parameter BLANK = 7'b000_0000;
parameter ZERO = 7'b111_1110; // h7e
parameter ONE = 7'b011_0000; // h30
parameter TWO = 7'b110_1101; // h6d
parameter THREE = 7'b111_1001; // h79
parameter FOUR = 7'b011_0011; // h33

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All  rights  reserved.  
   96  

parameter FIVE = 7'b101_1011; // h5b

parameter SIX = 7'b101_1111; // h5f
parameter SEVEN = 7'b111_0000; // h70
parameter EIGHT = 7'b111_1111; // h7f
parameter NINE = 7'b111_1011; // h7b

always @ (BCD)
case (BCD)
0: Display = ZERO;
1: Display = ONE;
2: Display = TWO;
3: Display = THREE;
4: Display = FOUR;
5: Display = FIVE;
6: Display = SIX;
7: Display = SEVEN;
8: Display = EIGHT;
9: Display = NINE;
default: Display = BLANK;
endcase
endmodule

module t_Seven_Seg_Display_V2001 ();

wire [6: 0] Display;
reg [3: 0] BCD;

parameter BLANK = 7'b000_0000;

parameter ZERO = 7'b111_1110; // h7e
parameter ONE = 7'b011_0000; // h30
parameter TWO = 7'b110_1101; // h6d
parameter THREE = 7'b111_1001; // h79
parameter FOUR = 7'b011_0011; // h33
parameter FIVE = 7'b101_1011; // h5b
parameter SIX = 7'b001_1111; // h1f
parameter SEVEN = 7'b111_0000; // h70
parameter EIGHT = 7'b111_1111; // h7f
parameter NINE = 7'b111_1011; // h7b

initial #120 $finish;

initial fork
#10 BCD = 0;
#20 BCD = 1;
#30 BCD = 2;
#40 BCD = 3;
#50 BCD = 4;
#60 BCD = 5;
#70 BCD = 6;
#80 BCD = 7;
#90 BCD = 8;
#100 BCD = 9;

join

Seven_Seg_Display_V2001 M0 (Display, BCD);

endmodule

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All  rights  reserved.  
   97  

0 60 120
Name

BCD[3:0] x 0 1 2 3 4 5 6 7 8 9
Display[6:0] xx 7e 30 6d 79 33 5b 5f 70 7f 7b

Alternative with continuous assignments (dataflow):

module Seven_Seg_Display_V2001_CA (
output [6: 0] Display,
input [3: 0] BCD
);

// abc_defg
parameter BLANK = 7'b000_0000;
parameter ZERO = 7'b111_1110; // h7e
parameter ONE = 7'b011_0000; // h30
parameter TWO = 7'b110_1101; // h6d
parameter THREE = 7'b111_1001; // h79
parameter FOUR = 7'b011_0011; // h33
parameter FIVE = 7'b101_1011; // h5b
parameter SIX = 7'b101_1111; // h5f
parameter SEVEN = 7'b111_0000; // h70
parameter EIGHT = 7'b111_1111; // h7f
parameter NINE = 7'b111_1011; // h7b
wire A, B, C, D, a, b, c, d, e, f, g;

assign A = BCD[3];
assign B = BCD[2];
assign C = BCD[1];
assign D = BCD[0];
assign Display = {a,b,c,d,e,f,g};
assign a = (~A)&C | (~A)&B&D | (~B)&(~C)&(~D) | A & (~B)&(~C);
assign b = (~A)&(~B) | (~A)&(~C)&(~D) | (~A)&C&D | A&(~B)&(~C);
assign c = (~A)&B | (~A)&D | (~B)&(~C)&(~D) | A&(~B)&(~C);
assign d = (~A)&C&(~D) | (~A)&(~B)&C | (~B)&(~C)&(~D) | A&(~B)&(~C) | (~A)&B&(~C)&D;
assign e = (~A)&C&(~D) | (~B)&(~C)&(~D);
assign f = (~A)&B&(~C) | (~A)&(~C)&(~D) | (~A)&B&(~D) | A&(~B)&(~C);
assign g = (~A)&C&(~D) | (~A)&(~B)&C | (~A)&B&(~C) | A&(~B)&(~C);
endmodule

module t_Seven_Seg_Display_V2001_CA ();

wire [6: 0] Display;
reg [3: 0] BCD;

parameter BLANK = 7'b000_0000;

parameter ZERO = 7'b111_1110; // h7e
parameter ONE = 7'b011_0000; // h30
parameter TWO = 7'b110_1101; // h6d
parameter THREE = 7'b111_1001; // h79
parameter FOUR = 7'b011_0011; // h33
parameter FIVE = 7'b101_1011; // h5b
parameter SIX = 7'b001_1111; // h1f
parameter SEVEN = 7'b111_0000; // h70
parameter EIGHT = 7'b111_1111; // h7f
parameter NINE = 7'b111_1011; // h7b

initial #120 $finish;

initial fork

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   98  

#10 BCD = 0;
#20 BCD = 1;
#30 BCD = 2;
#40 BCD = 3;
#50 BCD = 4;
#60 BCD = 5;
#70 BCD = 6;
#80 BCD = 7;
#90 BCD = 8;
#100 BCD = 9;

join

Seven_Seg_Display_V2001_CA M0 (Display, BCD);

endmodule

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All  rights  reserved.  
   99  

4.52 (a) Incrementer for unsigned 4-bit numbers

   
module Problem_4_52a_Data_Flow (output [3: 0] sum, output carry, input [3: 0] A);
assign {carry, sum} = A + 1;
endmodule

module t_Problem_4_52a_Data_Flow;
wire [3: 0] sum;
wire carry;
reg [3: 0] A;

Problem_4_52a_Data_Flow M0 (sum, carry, A);

initial # 100 $finish;

integer K;
initial begin
for (K = 0; K < 16; K = K + 1) begin A = K; #5; end
end
endmodule

(b) Decrementer for unsigned 4-bit numbers

module Problem_4_52b_Data_Flow (output [3: 0] diff, output borrow, input [3: 0] A);
assign {borrow, diff} = A - 1;
endmodule

module t_Problem_4_52b_Data_Flow;
wire [3: 0] diff;
wire borrow;
reg [3: 0] A;

Problem_4_52b_Data_Flow M0 (diff, borrow, A);

initial # 100 $finish;

integer K;
initial begin
for (K = 0; K < 16; K = K + 1) begin A = K; #5; end
end
endmodule

Name 0 30 60 90

A[3:0] 0 1 2 3 4 5 6 7 8 9 a b c d e f
diff[3:0] f 0 1 2 3 4 5 6 7 8 9 a b c d e
borrow

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All  rights  reserved.  
   100  

4.53 // BCD Adder

module Problem_4_53_BCD_Adder (
output Output_carry,
output [3: 0] Sum,
input [3: 0] Addend, Augend,
input Carry_in);
supply0 gnd;
wire [3: 0] Z_Addend;
wire Carry_out;
wire C_out;
assign Z_Addend = {1'b0, Output_carry, Output_carry, 1'b0};
wire [3: 0] Z_sum;

and (w1, Z_sum[3], Z_sum[2]);

and (w2, Z_sum[3], Z_sum[1]);
or (Output_carry, Carry_out, w1, w2);

Adder_4_bit M0 (Carry_out, Z_sum, Addend, Augend, Carry_in);

Adder_4_bit M1 (C_out, Sum, Z_Addend, Z_sum, gnd);
endmodule

module Adder_4_bit (output carry, output [3:0] sum, input [3: 0] a, b, input c_in);
assign {carry, sum} = a + b + c_in;
endmodule

module t_Problem_4_53_Data_Flow;
wire [3: 0] Sum;
wire Output_carry;
reg [3: 0] Addend, Augend;
reg Carry_in;

Problem_4_53_BCD_Adder M0 (Output_carry, Sum, Addend, Augend, Carry_in);

initial # 1500 $finish;

integer i, j, k;
initial begin
for (i = 0; i <= 1; i = i + 1) begin Carry_in = i; #5;
for (j = 0; j <= 9; j = j +1) begin Addend = j; #5;
for (k = 0; k <= 9; k = k + 1) begin Augend = k; #5;
end
end
end
end
endmodule
Name 68 98 128 158 188

Addend[3:0] 1 2 3
Augend[3:0] 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5
Carry_in
Sum[3:0] 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
Output_carry
 

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All  rights  reserved.  
   101  

4.54 (a) 9s Complement of BCD

module Nines_Complementer ( // V2001
output reg [3: 0] Word_9s_Comp,
input [3: 0] Word_BCD
);
always @ (Word_BCD) begin
Word_9s_Comp = 4'b0;
case (Word_BCD)
4'b0000: Word_9s_Comp = 4'b1001; // 0 to 9
4'b0001: Word_9s_Comp = 4'b1000; // 1 to 8
4'b0010: Word_9s_Comp = 4'b0111; // 2 to 7
4'b0011: Word_9s_Comp = 4'b0110; // 3 to 6
4'b0100: Word_9s_Comp = 4'b0101; // 4 to 5
4'b0101: Word_9s_Comp = 4'b0100; // 5 to 4
4'b0110: Word_9s_Comp = 4'b0011; // 6 to 3
4'b0111: Word_9s_Comp = 4'b0010; // 7 to 2
4'b1000: Word_9s_Comp = 4'b0001; // 8 to 1
4'b1001: Word_9s_Comp = 4'b0000; // 9 to 0
default: Word_9s_Comp = 4'b1111; // Error detection
endcase
end
endmodule
 
module t_Nines_Complementer ();
wire [3: 0] Word_9s_Comp;
reg [3: 0] Word_BCD;

Nines_Complementer M0 (Word_9s_Comp, Word_BCD);

initial #11$finish;
initial fork
Word_BCD = 0;
#10 Word_BCD = 1;
#20 Word_BCD = 2;
#30 Word_BCD = 3;
#40 Word_BCD = 4;
#50 Word_BCD = 5;
#60 Word_BCD = 6;
#70 Word_BCD = 7;
#20 Word_BCD = 8;
#90 Word_BCD = 9;
#100 Word_BCD = 4'b1100; // Confirm error detection
join
endmodule

Name 0 60

Word_BCD[3:0] 0 1 2 3 4 5 6 7 9
Word_9s_Comp[3:0] 9 8 7 6 5 4 3 2 0

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All  rights  reserved.  
   102  

(b) 9s complement of Gray Code

module Nines_Complementer ( // V2001

output reg [3: 0] Word_9s_Comp,
input [3: 0] Word_Gray
);
always @ (Word_Gray) begin
Word_9s_Comp = 4'b0;
case (Word_BCD)
4'b0000: Word_9s_Comp = 4'b1101; // 0 to 9
4'b0001: Word_9s_Comp = 4'b1100; // 1 to 8
4'b0010: Word_9s_Comp = 4'b0100; // 2 to 7
4'b0011: Word_9s_Comp = 4'b0101; // 3 to 6
4'b0100: Word_9s_Comp = 4'b0111; // 4 to 5
4'b0101: Word_9s_Comp = 4'b0110; // 5 to 4
4'b0110: Word_9s_Comp = 4'b0010; // 6 to 3
4'b0111: Word_9s_Comp = 4'b0011; // 7 to 2
4'b1000: Word_9s_Comp = 4'b0001; // 8 to 1
4'b1001: Word_9s_Comp = 4'b0000; // 9 to 0
default: Word_9s_Comp = 4'b1111; // Error detection
endcase
end
endmodule
 
module t_Nines_Complementer ();
wire [3: 0] Word_9s_Comp;
reg [3: 0] Word_Gray;

Nines_Complementer M0 (Word_9s_Comp, Word_Gray);

initial #11$finish;
initial fork
Word_Gray = 0;
#10 Word_Gray = 1;
#20 Word_Gray = 2;
#30 Word_Gray = 3;
#40 Word_Gray = 4;
#50 Word_Gray = 5;
#60 Word_Gray = 6;
#70 Word_Gray = 7;
#20 Word_Gray = 8;
#90 Word_Gray = 9;
#100 Word_Gray = 4'b1100; // Confirm error detection
join
endmodule

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   103  

4.55 From Problem 4.19:

Mode = 0 FOR Add
B3 B2 B1 B0 Mode = 1 for Subtract

9's Complementer
(See Problem 4.18)

Select
Select = 1 Select = 0
A3 A2 A1 A0
Quadruple 2 x 1 MUX
Cin

BCD Adder (See Fig. 4.14)

// BCD Adder – Subtractor

module Problem_4_55_BCD_Adder_Subtractor (
output [3: 0] BCD_Sum_Diff,
output Carry_Borrow,
input [3: 0] B, A,
input Mode

);
wire [3: 0] Word_9s_Comp, mux_out;
Nines_Complementer M0 (Word_9s_Comp, B);
Quad_2_x_1_mux M2 (mux_out, Word_9s_Comp, B, Mode);
BCD_Adder M1 (Carry_Borrow, BCD_Sum_Diff, mux_out, A, Mode);
endmodule

module Nines_Complementer ( // V2001

output reg [3: 0] Word_9s_Comp,
input [3: 0] Word_BCD
);
always @ (Word_BCD) begin
Word_9s_Comp = 4'b0;
case (Word_BCD)
4'b0000: Word_9s_Comp = 4'b1001; // 0 to 9
4'b0001: Word_9s_Comp = 4'b1000; // 1 to 8
4'b0010: Word_9s_Comp = 4'b0111; // 2 to 7
4'b0011: Word_9s_Comp = 4'b0110; // 3 to 6
4'b0100: Word_9s_Comp = 4'b1001; // 4 to 5
4'b0101: Word_9s_Comp = 4'b0100; // 5 to 4
4'b0110: Word_9s_Comp = 4'b0011; // 6 to 3
4'b0111: Word_9s_Comp = 4'b0010; // 7 to 2
4'b1000: Word_9s_Comp = 4'b0001; // 8 to 1
4'b1001: Word_9s_Comp = 4'b0000; // 9 to 0
default: Word_9s_Comp = 4'b1111; // Error detection
endcase
end
endmodule

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All  rights  reserved.  
   104  

module Quad_2_x_1_mux (output reg [3: 0] mux_out, input [3: 0] b, a, input select);
always @ (a, b, select)
case (select)
0: mux_out = a;
1: mux_out = b;
endcase
endmodule

module BCD_Adder (
output Output_carry,
output [3: 0] Sum,
input [3: 0] Addend, Augend,
input Carry_in);
supply0 gnd;
wire [3: 0] Z_Addend;
wire Carry_out;
wire C_out;
assign Z_Addend = {1'b0, Output_carry, Output_carry, 1'b0};
wire [3: 0] Z_sum;

and (w1, Z_sum[3], Z_sum[2]);

and (w2, Z_sum[3], Z_sum[1]);
or (Output_carry, Carry_out, w1, w2);

Adder_4_bit M0 (Carry_out, Z_sum, Addend, Augend, Carry_in);

Adder_4_bit M1 (C_out, Sum, Z_Addend, Z_sum, gnd);
endmodule

module Adder_4_bit (output carry, output [3:0] sum, input [3: 0] a, b, input c_in);
assign {carry, sum} = a + b + c_in;
endmodule

module t_Problem_4_55_BCD_Adder_Subtractor();
wire [3: 0] BCD_Sum_Diff;
wire Carry_Borrow;
reg [3: 0] B, A;
reg Mode;

Problem_4_55_BCD_Adder_Subtractor M0 (BCD_Sum_Diff, Carry_Borrow, B, A, Mode);

initial #1000 $finish;

integer J, K, M;
initial begin
for (M = 0; M < 2; M = M + 1) begin
for (J = 0; J < 10; J = J + 1) begin
for (K = 0; K < 10; K = K + 1) begin
A = J; B = K; Mode = M; #5 ;
end
end
end
end
endmodule

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   105  

Name 258 288 318 348

M 0
A[3:0] 5 6 7
B[3:0] 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
Word_9s_Comp[3:0] 7 6 9 4 3 2 1 0 9 8 7 6 9 4 3 2 1 0 9 8 7 6
mux_out[3:0] 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
BCD_Sum_Diff[3:0] 7 8 9 0 1 2 3 4 6 7 8 9 0 1 2 3 4 5 7 8 9 0
Carry_Borrow

Note: For subtraction, Carry_Borrow = 1 indicates a positive result; Carry_Borrow = 0 indicates a

negative result.

768 798 828 858

Name

M 1

A[3:0] 5 6 7

B[3:0] 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5

Word_9s_Comp[3:0] 9 4 3 2 1 0 9 8 7 6 9 4 3 2 1 0 9 8 7 6 9 4

mux_out[3:0] 9 4 3 2 1 0 9 8 7 6 9 4 3 2 1 0 9 8 7 6 9 4

BCD_Sum_Diff[3:0] 5 0 9 8 7 6 5 4 3 6 1 0 9 8 7 6 5 4 7 2

Carry_Borrow

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   106  

4.56
assign  match  =  (A  ==  B);   //  Assumes  reg  [3:  0]  A,  B;  

4.57
// Priority encoder (See Problem 4.29)
// Caution: do not confuse logic value x with identifier x.
// Verilog 1995

module Prob_4_57 (x, y, v, D3, D2, D1, D0);

output x, y, v;
input D3, D2, D1, D0;
reg x, y, v;
...

// Verilog 2001, 2005

module Prob_4_57 (output reg x, y, v, input D3, D2, D1, D0);

always @ (D3, D2, D1, D0) begin // always @ (D3 or D2 or D1 or D0)
x = 0;
y = 0;
v = 0;
casex ({D3, D2, D1, D0})
4'b0000: {x, y, v} = 3'bxx0;
4'bxxx1: {x, y, v} = 3'b001;
4'bxx10: {x, y, v} = 3'b011;
4'bx100: {x, y, v} = 3'b101;
4'b1000: {x, y, v} = 3'b110;
endcase
end
endmodule

module t_Prob_4_57;
wire x, y, v;
reg D3, D2, D1, D0;
integer K;
Prob_4_57 M0 (x, y, v, D3, D2, D1, D0);
initial #100 $finish;
initial begin
for (K = 0; K < 16; K = K + 1) begin {D3, D2, D1, D0} = K; #5 ; end
end
endmodule
 

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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   107  

4.58 (a)
//module shift_right_by_3_V2001 (output [31: 0] sig_out, input [31: 0] sig_in);
// assign sig_out = sig_in >>> 3;
//endmodule

module shift_right_by_3_V1995 (output reg [31: 0] sig_out, input [31: 0] sig_in);

always @ (sig_in)
sig_out = {sig_in[31], sig_in[31], sig_in[31], sig_in[31: 3]};
endmodule

module t_shift_right_by_3 ();

wire [31: 0] sig_out_V1995;
wire [31: 0] sig_out_V2001;

reg [31: 0] sig_in;

//shift_right_by_3_V2001 M0 (sig_out_V2001, sig_in);

shift_right_by_3_V1995 M1 (sig_out_V1995, sig_in);

integer k;
initial #1000 $finish;
initial begin
sig_in = 32'hf000_0000;
#100 sig_in = 32'h8fff_ffff;
#500 sig_in = 32'h0fff_ffff;
end
endmodule

Name 609 619 629 639

sig_in[31:0] 00001111111111111111111111111111
sig_out_V1995[31:0] 00000001111111111111111111111111

Name 34 44 54 64

sig_in[31:0] 11110000000000000000000000000000
sig_out_V1995[31:0] 11111110000000000000000000000000

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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   108  

(b)

//module shift_left_by_3_V2001 (output [31: 0] sig_out, input [31: 0] sig_in);

assign sig_out = sig_in <<< 3;

//module shift_left_by_3_V1995 (output reg [31: 0] sig_out, input [31: 0] sig_in);

//always @ (sig_in)
// sig_out = {sig_in[31: 3], 3'b0};
endmodule

module t_shift_left_by_3 ();

wire [31: 0] sig_out_V1995;
wire [31: 0] sig_out_V2001;

reg [31: 0] sig_in;

shift_left_by_3_V2001 M0 (sig_out_V2001, sig_in);

integer k;
initial #1000 $finish;
initial begin
sig_in = 32'hf000_0000;
#100 sig_in = 32'h8fff_ffff;
#500 sig_in = 32'h0fff_ffff;
end
endmodule

Name 0 50 100 150

sig_in[31:0] xxxxxxxx 0000000f

sig_out_V1995[31:0] xxxxxxxx 00000078

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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   109  

4.59
module BCD_to_Decimal (output reg [3: 0] Decimal_out, input [3: 0] BCD_in);
always @ (BCD_in) begin
Decimal_out = 0;
case (BCD_in)
4'b0000: Decimal_out = 0;
4'b0001: Decimal_out = 1;
4'b0010: Decimal_out = 2;
4'b0011: Decimal_out = 3;
4'b0100: Decimal_out = 4;
4'b0101: Decimal_out = 5;
4'b0110: Decimal_out = 6;
4'b0111: Decimal_out = 7;
4'b1000: Decimal_out = 8;
4'b1001: Decimal_out = 9;
default: Decimal_out = 4'bxxxx;
endcase
end
endmodule  

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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   110  

4.60
module Even_Parity_Checker_4 (output P, C, input x, y, z);
xor (w1, x, y);
xor (P, w1, z);
xor (C, w1, w2);
xor (w2, z, P);
endmodule

See Problem 4.62 for testbench and waveforms.

4.61
module Even_Parity_Checker_4 (output P, C, input x, y, z);
assign w1 = x ^ y;
assign P = w1 ^ z;
assign C = w1 ^ w2;
assign w2 = z ^ P;
endmodule

Name 0 140 280 420

x
y
z
P
C

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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   111  

4.62
A0 3x8 8
A1 D0 - D7
A2 Decoder
E

8
3x8
Decoder D8 - D15
E

0
A3 20
2x4 1
Decoder 2 8
3x8
A4 21 D16 - D23
3 Decoder
E E

3x8 8
D24 - D31
Decoder
E

module Decoder_3x8 (output D7, D6, D5, D4, D3, D2, D1, D0, input in2, in1, in0, E);
not (in2_bar, in2);
not (in1_bar, in1);
not (in0_bar, in0);
and (D0, in2_bar, in1_bar, in0_bar, E);
and (D1, in2_bar, in1_bar, in0, E);
and (D2, in2_bar, in1, in0_bar, E);
and (D3, in2_bar, in1, in0, E);
and (D4, in2, in1_bar, in0_bar, E);
and (D5, in2, in1_bar, in0, E);
and (D6, in2, in1, in0_bar, E);
and (D7, in2, in1, in0, E);
endmodule

module Decoder_5x32 (
output D31, D30, D29, D28, D27, D26, D25, D24, D23, D22, D21, D20, D19, D18, D17, D16,
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0,
input A4, A3, A2, A1, A0, E;
wire E3, E2, E1, E0;
Decoder_3x8 M0 (D7, D6, D5, D4, D3, D2, D1, D0, A2, aA1, A0, E0);
Decoder_3x8 M1 (D15, D14, D13, D12, D11, D10, D9, D8, A2, A1, A0, E1);
Decoder_3x8 M2 (D23, D22, D21, D20, D19, D18, D17, D16, in2, in1, in0, E2);
Decoder_3x8 M3 (D31, D30, D29, D28, D27, D26, D25, D24, A2, A1, A0, E3);
Decoder_2x4 M4 (E3, E2, E1, E0, A4, A3, E);
endmodule

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.  
   112  

4.63

A0 20 2x4 4
D0 - D3
A1 2 1 Decoder
E

20 2x4
4
1 Decoder D4 - D7
2 E

0
A2 20
2x4 1
Decoder 2 20 4
2x4
A3 21 D8 - D11
3 21 Decoder
E E

20 2x4 4
D12 - D15
21 Decoder
E

module Decoder_2x4 (output D3, D2, D1, D0, input in1, in0, E);
not (in1_bar, in1);
not (in0_bar, in0);
and (D0, in1_bar, in0_bar, E);
and (D1, in1_bar, in0, E);
and (D2, in1, in0_bar, E);
and (D3, in1, in0, E);
endmodule

module Decoder_4x16 (
output D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0,
input A3, A2, A1, A0, E);
wire E3, E2, E1, E0;
Decoder_2x4 M0 (output D3, D2, D1, D0, input in1, in0, E0);
Decoder_2x4 M1 (output D7, D6, D5, D4, input in1, in0, E1);
Decoder_2x4 M2 (output D11, D10, D9, D8, input in1, in0, E2);
Decoder_2x4 M3 (output D15, D14, D13, D12, input in1, in0, E3);
Decoder_2x4 M4 (output E3, E2, E1, E0, input A3, A2, E);
endmodule

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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   113  

4.64
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 x y z V

0 0 0 0 0 0 0 0 x x x 0
1 0 0 0 0 0 0 0 0 0 0 1
x 1 0 0 0 0 0 0 0 0 1 1
x x 1 0 0 0 0 0 0 1 0 1
x x x 1 0 0 0 0 0 1 1 1
x x x x 1 0 0 0 1 0 0 1
x x x x x 1 0 0 1 0 1 1
x x x x x x 1 0 1 0 0 1
x x x x x x x 1 1 1 1 1

If D2 = 1, D6 = 1, all others = 0
Output xyz = 100 and V = 1  
 
module Prob_4_64 (output x, y, x, V, input, D0, D1, D2, D3, D4,D5 D6, D7);

always @( D0, D1, D2, D3, D4,D5 D6, D7)

case({D0, D1, D2, D3, D4,D5 D6, D7})
8'b0000_0000: {x, y, x, V} = 4'bxxx0;
8'b1000_0000: {x, y, x, V} = 4'b0001;
8'b0100_0000: {x, y, x, V} = 4'b0011;
8'b0010_0000: {x, y, x, V} = 4'b0101;

8'b0001_0000: {x, y, x, V} = 4'b0111;

8'b0000_1000: {x, y, x, V} = 4'b1001;
8'b0000_0100: {x, y, x, V} = 4'b1011;
8'b0000_0010: {x, y, x, V} = 4'b1001;
8'b0000_0001: {x, y, x, V} = 4'b1111;
default: {x, y, x, V} = 4'b1010; // Use for error detection
endcase
endmodule
 
 
 
 
 
 
 

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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   114  

4.65

s0 s0
s1 s1
s2 s2
s3 0 0
1 1
8x1
2 2
MUX
3 3
4 4
5 5
6 6
7 7
s
2x1 y
0
MUX
1
s0
s1
s2
8 0
9 1
8x1
10 2
MUX
11 3
12 4
13 5
14 6
15 7

module Mux_2x1 (
output y_out,
input in1, in0, sel);
not (sel_bar, sel);
and (y0, in0, sel);
and (y1, in1, sel);
or (y_out, in0, in1, sel_bar
);
endmodule

module Mux_4x1 (
output y_out,
input in3, in2, in1, in0, sel1, sel0);
not (sel_1_bar, sel1);
and (s0, sel_1_bar, sel0);
and (s1, sel[1], sel0);
Mux_2x1 M0 (y_M0, in0, in1, s0);
Mux_2x1 M1 (y_M1, in2, in3, s1);
or (y_out, y_M0, y_M1
);
endmodule

module Mux_8x1 (
output y_out,
input in7, in6, in5, in4, in3, in2, in1, in0, sel2, sel1, sel0
);
Mux_4x1 M0 (y_M0, in3, in2, in1, in0, sel1, sel0);
Mux_4x1 M1 (y_M1, in7, in6, in5, in4, sl1, sel0);
Mux_2x1 M2 (y_out, y_M0, y_M1, sel2);
endmodule

module Mux_16x1 (
output y_out,

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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   115  

input in15, in14, in13, in12, in11, in10, in9, in8, in7, in6, in5, in4, in3, in2, in1, in0, sel3, sel2, sel1, sel0
);
Mux_8x1 M0 (y_M0, in7, in6, in5, in4, in3, in2, in1, in0, sel2, sel1, sel0);
Mux_8x1 M1 (y_M1, in15, in14, in13, in12, in11, in10, in9, in8, sel2, sel1, sel0);
Mux_2x1 M2 (y_out, y_M0, y_M1, sel3);
endmodule

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
All  rights  reserved.