Unit-4

Combinational Logic
Compiled by: Madan Nath
BMC BIT-TU

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Contents:
q Adder and Subtractor
q Parallel Binary Adders,
q Multiplexers and Demultiplexers,
q Encoders and Decoders.
q Seven segment decoder,
q Code Converters

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 Combinational circuits
— A combinational logic circuit is one in which the present
state of the combination of the logic inputs decides the
output.
— The term combination logic means combining of two or
more logic gates to form a required function where the
output at a given time depends only on the input.
— The required output data is obtained from this process by
transforming the binary information given at the input.

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Classification of Combinational Logic

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 Characteristics of Combinational Logic
— The output of combinational circuit at any instant of
time, depends only on the levels present at input
terminals.

— The combinational circuit do not use any memory.

The previous state of input does not have any effect
on the present state of the circuit.

— A combinational circuit can have an n number of

inputs and m number of outputs.

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 Half Adder
— Half adder is a combinational logic circuit with two
inputs and two outputs.
— The half adder circuit is designed to add two single bit
binary number A and B.
— It is the basic building block for addition of two single bit
numbers.
— Inputs are called Augend and Added bits and Outputs are
called Sum and Carry.
— Let us observe the addition of single bits,
◦ 0+0=00
◦ 0+1=01
◦ 1+0=01
◦ 1+1=10 (The result of 1+1 is 10, where ‘1’ is carry-
output (Cout) and ‘0’ is Sum-output)
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 Half Adder
— Block diagram:

— Truth Table:

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 Half Adder
— Logic Diagram: To draw Logic Diagram, We need
Boolean Expression, which can be obtained using K-map
(karnaugh map). Since there are two output variables ‘S’
and ‘C’, we need to define K-map for each output
variable.

— K-map is of Sum of products form. The equation obtained

is: S = AB' + A’B
or. S = A XOR B
S = A⊕B
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 Half Adder
— K-map for output variable Carry ‘C’ :

— The equation obtained from K-map is: C = AB

— Limitations:
◦ Adding of Carry is not possible in Half adder.

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 Half Adder
— Using the Boolean Expression, we can draw logic
diagram as follows..
OR

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 Full Adder
— A combinational logic circuit that performs the addition
of three single bits is called Full Adder.

— To overcome the above limitation faced with Half adders,

Full Adders are implemented.
— It is a arithmetic combinational logic circuit that performs
addition of three single bits.
— It contains three inputs (A, B, Cin) and produces two
outputs (Sum and Cout).
— Where, Cin à Carry In and Cout à Carry Out 11
 Full Adder
— Truth table of Full Adder:

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 Full Adder
— K-map Simplification for output variable Sum
‘S’ :

The equation obtained is,

S = A'B'Cin + AB’ Cin' + ABC + A'BCin’

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 Full Adder
— The equation can be simplified as,
◦ S = A'B'Cin + AB’ Cin' + ABC + A'BCin’
◦ S = B'(A'Cin+ACin') + B(AC + A'Cin’)
◦ S = B'(A xor Cin) + B (A xor Cin)’
◦ S = A xor B xor Cin
◦ S =A⊕B⊕C

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 Full Adder
— K-map Simplification for output variable ‘Cout’

— The equation obtained is: Cout = BCin + AB + ACin

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 Full Adder
— Logic Diagram of Full Adder:
S =A⊕B⊕C
Cout = BCin+AB+ACin

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 Full Adder
— Logic Diagram of Full Adder(OR):
S =A⊕B⊕C
Cout = BCin+AB+ACin

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 What is the difference between half
adder and a full adder circuit?
• The main difference between a half-adder and a full-
adder is that the full-adder has three inputs and two
outputs. The first two inputs are A and B and the third
input is an input carry designated as CIN. When a full
adder logic is designed we will be able to string eight of
them together to create a byte-wide adder and cascade the
carry bit from one adder to the next.
• The output carry is designated as COUT and the normal
output is designated as S.
 TruthTable:
• 2-input Exclusive-OR • 2-input AND Gate
Gate

Truth Table Symbol Truth Table

Symbol
B A S B A C
0 0 0
0 0 0
0 1 0
0 1 1
2-input Ex-OR 1 0 0
1 0 1 2-input AND 1 1 1
Gate
1 1 0 Gate
 Half Subtractor
— Block Diagram

— It is a combinational logic circuit designed to perform

subtraction of two single bits.
— It contains two inputs (A and B) and produces two
outputs (Difference and Borrow-output).

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 Half Subtractor
— Truth Table of Half Subtractor:

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 Half Subtractor
— K-map Simplification for output variable
‘D’:

— The equation obtained is: D = A'B + AB’

— Which can be logically written as: D = A xor B

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 Half Subtractor
— K-map Simplification for output variable ‘Bout’
:

— The equation obtained from above K-map is: Bout = A'B

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 Half Subtractor
— Logic Diagram of Half Subtractor:

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 Full Subtractor:
— Block diagram:

— It is a Combinational logic circuit designed to perform

subtraction of three single bits.
— It contains three inputs(A, B, Bin) and produces two
outputs (D, Bout).
— Where, A and B are called Minuend and Subtrahend bits.
— And, Bin à Borrow-In and Bout à Borrow-Out

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 Full Subtractor:
— Truth Table of Full Subtractor:

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 Full Subtractor:
— K-map Simplification for output variable
‘D’:

— The equation obtained from above K-map is,

D = A'B'Bin + AB’Bin' + ABBin + A'BBin’
— Which can be simplified as,
D = B'(A'Bin + ABin') + B(ABin + A'Bin’)
D = B'(A xor Bin) + B(A xor Bin)’
D = A xor B xor Bin 27
 Full Subtractor:
— K-map Simplification for output variable ‘Bout’ :

— The equation obtained is: Bout = BBin + A'B + A'Bin

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 Full Subtractor:
— Logic Diagram of Full Subtractor:

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 Full Subtractor:
— Logic Diagram of Full Subtractor:

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 Full Subtractor:
Applications:
— For performing arithmetic calculations in electronic
calculators and other digital devices.
— In Timers and Program Counters.
— Useful in Digital Signal Processing.

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Parallel Adder:–
— A single full adder performs the addition of two one bit
numbers and an input carry.
— But a Parallel Adder is a digital circuit capable of finding
the arithmetic sum of two binary numbers that is greater
than one bit in length by operating on corresponding pairs
of bits in parallel.
— It consists of full adders connected in a chain where the
output carry from each full adder is connected to the
carry input of the next higher order full adder in the
chain.
— A n bit parallel adder requires ‘n’ full adders to perform
the operation. So for the two-bit number, two adders are
needed while for four bit number, four adders are needed
and so on.
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Parallel Adder –
— Parallel adders normally incorporate carry lookahead logic
to ensure that carry propagation between subsequent
stages of addition does not limit addition speed.

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 Working of parallel Adder –
1. As shown in the figure, firstly the full adder FA1 adds A1
and B1 along with the carry C1 to generate the sum S1
(the first bit of the output sum) and the carry C2 which is
connected to the next adder in chain.
2. Next, the full adder FA2 uses this carry bit C2 to add with
the input bits A2 and B2 to generate the sum S2(the
second bit of the output sum) and the carry C3 which is
again further connected to the next adder in chain and so
on.
3. The process continues till the last full adder FAn uses the
carry bit Cn to add with its input An and Bn to generate
the last bit of the output along last carry bit Cout.

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Parallel Subtractor –
— A Parallel Subtractor is a digital circuit capable of finding
the arithmetic difference of two binary numbers that is
greater than one bit in length by operating on
corresponding pairs of bits in parallel.
— The parallel subtractor can be designed in several ways
including combination of half and full subtractors, all full
subtractors or all full adders with subtrahend complement.
input.

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Working of Parallel Subtractor –
1. As shown in the figure, the parallel binary subtractor is
formed by combination of all full adders with subtrahend
complement input.
2. This operation considers that the addition of minuend
along with the 2’s complement of the subtrahend is equal
to their subtraction.
3. Firstly the 1’s complement of B is obtained by the NOT
gate and 1 can be added through the carry to find out the
2’s complement of B. This is further added to A to carry
out the arithmetic subtraction.
4. The process continues till the last full adder FA n uses the
carry bit Cn to add with its input An and 2’s complement
of Bn to generate the last bit of the output along last carry
bit Cout.
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Advantages of parallel Adder/Subtractor
1. The parallel adder/subtractor performs the addition
operation faster as compared to serial adder/subtractor.
2. Time required for addition does not depend on the
number of bits.
3. The output is in parallel form i.e all the bits are
added/subtracted at the same time.
4. It is less costly.
Disadvantages of parallel Adder/Subtractor
1. Each adder has to wait for the carry which is to be
generated from the previous adder in chain.
2. The propagation delay( delay associated with the
travelling of carry bit) is found to increase with the
increase in the number of bits to be added.
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 Multiplexers:
— A multiplexers (MUX) is a device that allows digital
information from several sources to be routed onto a
single line for transmission over that line to a common
destination.
— In multiplexer we have 2n input lines and 1 output lines
where n is the number of selection lines.

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 Multiplexers:
— MUX Types
— 2-to-1 (1 select line)
— 4-to-1 (2 select lines)
— 8-to-1 (3 select lines)
— 16-to-1 (4 select lines)
— Selection input (N) determines the input that should be
connected to the output.

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Functional Diagram Of a Multiplexer
 2 : 1 Multiplexer

Figure : Logic diagram of 2x1 mux Figure : Schematic symbol of 2x1 mux

S Z
0 IN1
1 IN2
4-to-1 Multiplexer (MUX)

I0
I1

MUX
O
I2
I3

S1 S0

S1 S0 O

0 0 I0

0 1 I1

1 0 I2

1 1 I3
8 : 1 Multiplexer

S0 S1 S2 Z
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7
8 : 1 Multiplexer
 Demultiplexers:
— A DEMULTIPLEXER (DEMUX) basically reverses the
multiplexing function.
— Demultiplexer is a data distributor which takes a single
input and gives several outputs.
— In demultiplexer we have 1 input and 2n output lines
where n is the selection line.

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 Demultiplexers:
— A demultiplexer routes (or connects) the data input to the
selected output.
The value of the control inputs determines the
output that is selected.
— A demultiplexer performs the opposite function of a
multiplexer.

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Functional Diagram Of a
Demultiplexer
 Demultiplexers

Out0 W W =A'.B'
Out1 X X = A'.B
I In Out2 Y
Y =A.B'
Out3 Z
S1 S0 Z = A.B

A B
A B W X Y Z
0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I
1 : 2 Demultiplexer
1:4 Demultiplexer (DEMUX)
D0

DEMUX
D1
X
D2
D3

B A

B A D0 D1 D2 D3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D
 1 : 8 Demultiplexer

Fig: Block Diagram

Fig: Logical Diagram

 1 : 8 Demultiplexer (Truth Table)
S0 S1 S3 D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 D 0 0 0 0 0 0 0
0 0 1 0 D 0 0 0 0 0 0
0 1 0 0 0 D 0 0 0 0 0
0 1 1 0 0 0 D 0 0 0 0
1 0 0 0 0 0 0 D 0 0 0
1 0 1 0 0 0 0 0 D 0 0
1 1 0 0 0 0 0 0 0 D 0
1 1 1 0 0 0 0 0 0 0 D
 1 : 16 Demultiplexer:
— A demultiplexer obtains in data from one line and directs
this to any of its N outputs depending upon the status of
the selected inputs.
— If the no. of output lines is N (16), no. of select lines m is
specified by 2m = N that is, 24 = 16. Therefore, the no. of
select lines is 4.
1 : 16 Demultiplexer:
1 : 16 Demultiplexer:
Multiplexer/ Demultiplexer for
information transmission
Difference between of Multiplexer and Demultiplexer :
Multiplexer Demultiplexer

Multiplexer processes the digital Demultiplexer receives digital

information from various sources into a information from a single source and
single source. converts it into several sources

It is known as Data Selector It is known as Data Distributor

Multiplexer is a digital switch Demultiplexer is a digital circuit

It follows combinational logic type It also follows combinational logic type

It has n data input It has single data input

It has a single data output It has n data outputs

It works on many to one operational It works on one to many operational

principle principle

In time division Multiplexing, In time division Multiplexing,

multiplexer is used at the transmitter demultiplexer is used at the receiver
end end 57
 Decimal Adder
— Decimal Adder is a combinational circuit that sums up
two decimal numbers adopting particular encoding
technique. It has minimum of 9 inputs and 5 outputs. 4 bit
is required to code a decimal digit and the circuit must
have an input carry and output carry.

BCD Adder
— This combinational circuit adds up two decimal numbers
encoded in BCD form. Adding two decimal digits in BCD
together with a possible carry the output sum cannot be
greater than 9+9+1=19.

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 Encoders and Decoders
Binary code of N digits can be used to store 2N distinct
elements of coded information. This is what encoders and
decoders are used for. Encoders convert 2N lines of input into
a code of N bits and Decoders decode the N bits into
2N lines.
1. Encoders:–
— An Encoder is a combinational circuit that performs the
reverse operation of Decoder. It has maximum of 2^N
input lines and ‘N’ output lines, hence it encodes the
information from 2n inputs into an n-bit code.
— It will produce a binary code equivalent to the input,
which is active High. i.e. If I3 is active then it reflect the
output 11.

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 Encoders and Decoders
Therefore, the encoder encodes 2^N input lines with ‘N’
bits.

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 4:2 Encoder:
— The 4 to 2 Encoder consists of four inputs Y3, Y2, Y1 &
Y0 and two outputs A1 & A0. At any time, only one of
these 4 inputs can be ‘1’ in order to get the respective
binary code at the output.
— The figure below shows the logic symbol of 4 to 2
encoder :

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 4:2 Encoder:
— The Truth table of 4 to 2 encoder is as follows :

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 4:2 Encoder:
— Logical expression for A1 and A0 :
A1 = Y3 + Y2
A0 = Y3 + Y1
The above two Boolean functions A1 and A0 can be
implemented using two input OR gates :

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 8:3 Encoder (Octal to Binary):
— The 8 to 3 Encoder or octal to Binary encoder consists
of 8 inputs : Y7 to Y0 and 3 outputs : A2, A1 & A0. Each
input line corresponds to each octal digit and three
outputs generate corresponding binary code.
— The figure below shows the logic symbol of octal to
binary encoder:

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 8:3 Encoder (Octal to Binary):
— The truth table for 8 to 3 encoder is as follows :

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 8:3 Encoder (Octal to Binary):
— Logical expression for A2, A1 and A0 :
A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2
A0 = Y7 + Y5 + Y3 + Y1
— The above two Boolean functions A2, A1 and A0 can be
implemented using four input OR gates :

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 Decimal to BCD Encoder
— The decimal to binary encoder usually consists of 10
input lines and 4 output lines.
— Each input line corresponds to the each decimal digit and
4 outputs correspond to the BCD code.
— This encoder accepts the decoded decimal data as an
input and encodes it to the BCD output which is available
on the output lines.
— The figure below shows the logic symbol of decimal to
BCD encoder :

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 Decimal to BCD Encoder
The truth table for decimal to BCD encoder is as follows:

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 Decimal to BCD Encoder
The truth table for decimal to BCD encoder is as follows:

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 Decimal to BCD Encoder
Logical expression for A3, A2, A1 and A0:
A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1

The above two Boolean functions can be implemented using

OR gates :

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Decimal to BCD Encoder

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 Priority Encoder(4:2 ) –
— A 4:2 priority encoder has 4 inputs : Y3, Y2, Y1 & Y0
and 2 outputs : A1 & A0. Here, the input, Y3 has
the highest priority, whereas the input, Y0 has the lowest
priority.
— In this case, even if more than one input is ‘1’ at the same
time, the output will be the (binary) code corresponding
to the input, which is having higher priority.

Y0
(Lowest Priority) A0

Y1
Y2 4X2 A1
Encoder
Y3
(High Priority)
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 Priority Encoder –
The truth table for priority encoder is as follows:
Note: The output V indicates if the input is valid.

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Priority EncoderK-map
–

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 Priority Encoder –
The above two Boolean functions can be implemented as:

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Priority Encoder(8:3 ) –

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Drawbacks of Normal Encoders –
— There is an ambiguity, when all outputs of encoder are
equal to zero.
— If more than one input is active High, then the encoder
produces an output, which may not be the correct code.
So, to overcome these difficulties, we should assign priorities
to each input of encoder. Then, the output of encoder will be
the ( code corresponding to the active High inputs, which has
higher priority.

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Uses of Encoders –
— Encoders are very common electronic circuits used in all
digital systems.
— Encoders are used to translate the decimal values to the
binary in order to perform the binary functions such as
addition, subtraction, multiplication, etc.
— Other applications especially for Priority Encoders may
include detecting interrupts in microprocessor
applications.

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 DECODERS:
— A decoder does the opposite job of an encoder.
— It is a combinational circuit that converts n lines of input
into 2n lines of output.

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 2:4 Decoder

Y Z D0 D1 D2 D3
0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1 80
2:4 Decoder

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 3:8 Decoder
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1
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 Implementation –
— D0 is high when X = 0, Y = 0 and Z = 0. Hence,
D0 = X’ Y’ Z’
— Similarly,
D1 = X’ Y’ Z
D2 = X’ Y Z’
D3 = X’ Y Z
D4 = X Y’ Z’
D5 = X Y’ Z
D6 = X Y Z’
D7 = X Y Z

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Implementation –

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 BCD to 7 Segment Decoder
— In Binary Coded Decimal (BCD) encoding scheme each of the
decimal numbers(0-9) is represented by its equivalent binary
pattern(which is generally of 4-bits).
— Whereas, Seven segment display is an electronic device which
consists of seven Light Emitting Diodes (LEDs) arranged in a
some definite pattern (common cathode or common anode type),
which is used to display Hexadecimal numerals(in this case
decimal numbers, as input is BCD i.e., 0-9).
— Two types of seven segment LED display:
◦ Common Cathode Type: In this type of display all cathodes of the
seven LEDs are connected together to the ground or –Vcc (hence,
common cathode) and LED displays digits when some ‘HIGH’ signal
is supplied to the individual anodes.
◦ Common Anode Type: In this type of display all the anodes of the
seven LEDs are connected to battery or +Vcc and LED displays digits
when some ‘LOW’ signal is supplied to the individual cathodes.
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 BCD to 7 Segment Decoder
— But, seven segment display does not work by directly supplying
voltage to different segments of LEDs. First, our decimal number
is changed to its BCD equivalent signal then BCD to seven
segment decoder converts that signals to the form which is fed to
seven segment display.
— This BCD to seven segment decoder has four input lines (A, B, C
and D) and 7 output lines (a, b, c, d, e, f and g), this output is
given to seven segment LED display which displays the decimal
number depending upon inputs.

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 BCD to 7 Segment Decoder
— Truth Table– For common cathode type BCD to seven segment
decoder:

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 BCD to 7 Segment Decoder
— K-Maps–
#For a: #For b:

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 BCD to 7 Segment Decoder
— K-Maps–
#For c: #For d:

89
 BCD to 7 Segment Decoder
— K-Maps–
#For e: #For f:

90
 BCD to 7 Segment Decoder
— K-Maps –
#For g:

91
— Logical Diagram:

92
 BCD to 7 Segment Decoder
Note –
— For Common Anode type seven segment LED display, we only
have to interchange all ‘0s’ and ‘1s’ in the output side i.e., (for
a, b, c, d, e, f, and g replace all ‘1’ by ‘0’ and vice versa) and
solve using K-map.
— Output for first combination of inputs (A, B, C and D) in Truth
Table corresponds to ‘0’ and last combination corresponds to
‘9’. Similarly rest corresponds from 2 to 8 from top to bottom.
— BCD numbers only range from 0 to 9,thus rest inputs from 10-
F are invalid inputs.
Applications–
— Seven-segment displays are used to display the digits in
calculators, clocks, various measuring instruments, digital
watches and digital counters.
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 BCD to 7 Segment Decoder
— Explanation –
For combination where all the inputs (A, B, C and D) are
zero (see Truth Table), our output lines are a = 1, b = 1, c =
1, d = 1, e = 1, f = 1 and g = 0. So 7 segment display shows
‘zero’ as output.
— Similarly, for combination where one of the input is one (D
= 1) and rest are zero, our output lines are a = 0, b = 1, c = 1,
d = 0, e = 0, f = 0 and g = 0. So only LEDs ‘b’ and ‘c’ (see
diagram above) will glow and 7 segment display shows ‘one’
as output.

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 Design a circuit:

Fig: Test segment logic Circuit.

95
Design a circuit for 0

96
Design a circuit for 1

97
Design a circuit for 2

98
Design a circuit for 3

99
Design a circuit for 4

100
Design a circuit for 5

101
Design a circuit for 6

102
Design a circuit for 7

103
Design a circuit for 8

104
Design a circuit for 9

105
Design a circuit for 10

106
 Code Converters
— Gray Code system is a binary number system in which every
successive pair of numbers differs in only one bit.
— It is used in applications in which the normal sequence of
binary numbers generated by the hardware may produce an
error or ambiguity during the transition from one number to
the next.
— For example: The states of a system may change from
3(011) to 4(100) as: 011 — 001 — 101 — 100. Therefore
there is a high chance of a wrong state being read while the
system changes from the initial state to the final state.
— This could have serious consequences for the machine using
the information. The Gray code eliminates this problem
since only one bit changes its value during any transition
between two numbers.
107
 Converting Binary to Gray Code –
— Let b0, b1, b2 and b3
be the bits representing
the binary numbers,
where b0 is the LSB
and b3 is the MSB and
Let g0, g1, g2 and g3
be the bits representing
the gray code of the
binary numbers, where
g0 is the LSB and g3 is
the MSB.
— The truth table for the
conversion is-

108
 Converting Binary to Gray Code –
— To find the corresponding digital circuit, we will use the K-
Map technique for each of the gray code bits as output with
all of the binary bits as input.
— K-map for g0:
b1`b0` b1`b0 b1b0 b1b0`

b3`b2`

b3`b2

b3b2

b3b2`

— Boolean expression: b1’b0+ b1b0` =b1 XOR b0

109
 Converting Binary to Gray Code –
— K-map for g1:
b1`b0` b1`b0 b1b0 b1b0`

b3`b2`

b3`b2

b3b2

b3b2`

— Boolean expression: b1’b2 + b2’b1 =b1 XOR b2

110
 Converting Binary to Gray Code –
— K-map for g2:

b1`b0` b1`b0 b1b0 b1b0`

b3`b2`

b3`b2

b3b2

b3b2`

— Boolean expression: b3’b2 + b3b2’ =b2 XOR b3

111
 Converting Binary to Gray Code –
— K-map for g3:
b1`b0` b1`b0 b1b0 b1b0`

b3`b2`

b3`b2

b3b2

b3b2`

— Boolean expression: b3

112
 Converting Binary to Gray Code –
For g0: b1’b0+ b1b0` =b0 XOR b1
For g1: b1’b2 + b1b2’ =b1 XOR b2
For g2: b3’b2 + b3b2’ =b2 XOR b3
For g3: b3
— The corresponding digital circuit –

113
 Converting Gray Code to Binary
— Converting gray code
back to binary can be
done in a similar manner.
Let Let b0, b1, b2 and b3
be the bits representing
the binary numbers,
where b0 is the LSB and
b3 is the MSB and Let
g0, g1, g2 and g3 be the
bits representing the gray
code of the binary
numbers, where go is the
LSB and g3 is the MSB.

114
 Converting Gray Code to Binary
— Using K-map to get back the binary bits from the gray
code –
K-map for b0:

115
 Converting Gray Code to Binary
— K-map for b1:

116
 Converting Gray Code to Binary
— K-map for b2:

117
 Converting Gray Code to Binary
— K-map for b3:

118
 Converting Gray Code to Binary
— Corresponding Boolean expressions –

119
 Converting Gray Code to Binary
— Corresponding digital circuit –

120
 Sequential Circuits
— A Sequential circuit combinational logic circuit that
consists of inputs variable (X), logic gates (Computational
circuit), and output variable (Z).
— Combinational circuit produces an output based on input
variable only, but Sequential circuit produces an output
based on current input and previous input variables. That
means sequential circuits include memory elements which
are capable of storing binary information. That binary
information defines the state of the sequential circuit at
that time. A latch capable of storing one bit of information.
— There are two types of sequential circuit :

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 Synchronous Sequential Circuits
— These circuit uses clock signal and level inputs (or pulsed)
(with restrictions on pulse width and circuit propagation).
The output pulse is the same duration as the clock pulse
for the clocked sequential circuits. Since they wait for the
next clock pulse to arrive to perform the next operation, so
these circuits are bit slower compared to asynchronous.
Level output changes state at the start of an input pulse and
remains in that until the next input or clock pulse.

122
 Asynchronous Sequential Circuits
— These circuit do not use a clock signal but uses the pulses
of the inputs. These circuits are faster than synchronous
sequential circuits because there is clock pulse and change
their state immediately when there is a change in the input
signal. We use asynchronous sequential circuits when
speed of operation is important and independent of internal
clock pulse.

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 Synchronous Vs Asynchronous
Synchronous Circuit Asynchronous Circuit

• All the State Variable changes • The State Variables are not
are synchronized with a synchronized to change
universal clock signal. simultaneously and may
change at anytime irrespective
of each other to achieve the
next Steady Internal State

• Since all the Internal State • Since there is no such universal

changes are in the strict control clock source, the internal state
of a master clock source they changes as soon as any of the
are less prone to failure or to a inputs change and hence are
race condition and hence are more prone to a race condition.
more reliable.

• Timings of the internal state • The changes in the internal

changes are in our control. state of an asynchronous circuit
are not in our control.
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 Solved Examples:
◦ Convert 1011 into corresponding Gray code.

Step 1: record the MSB as it is

Step 2: Add the MSB to the next bit, record the sum and
neglect the carry.

Step 3: Repeat the process.

Soln:

1 0 1 1
+1 +0 +1
1 1 1 0
 Solved Examples:
— Convert 1110 Gray code into corresponding Binary.
Soln: Step 1: record the MSB as it is

Step 2: Add LSB bit of the BCD and neglect the carry.

Step 3: Repeat the process.

Gray 1 1 1 0
Code: +1 +0 +1
BCD 1 0 1 1

126
 Converting Gray Code to Binary
— Corresponding Boolean expressions –

127
 Solved Examples:
— Design circuit that can display 2,5,7 and E in seven
segments.
Soln: Step 1: The seven segment display is as follows,

128
Step 2: Truth Table for 7-segment display 2,5,7 and E is,
No. A B C D a b c d e f g
0 0 0 0 0 x x x x x x x
1 0 0 0 1 x x x x x x x
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 x x x x x x x
4 0 1 0 0 x x x x x x x
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 x x x x x x x
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 x x x x x x x
9 1 0 0 1 x x x x x x x
10 1 0 1 0 x x x x x x x
11 1 0 1 1 x x x x x x x
12 1 1 0 0 x x x x x x x
13 1 1 0 1 x x x x x x x
14 1 1 1 0 1 0 0 1 1 1 1
15 1 1 1 1 x x x x x x x 129
 CD
Step 3: K-map for a, b, c, d, e, f, g
AB (C’D’) (C’D) (CD) (CD’)
(A’B’) X0 X1 X3 12
(A’B) X4 15 17 X6
(AB) X12 X13 X15 1 14
(AB’) X8 X9 X11 X10

a =A’ + C

CD
AB (C’D’) (C’D) (CD) (CD’)
(A’B’) X0 X1 X3 12
(A’B) X4 05 17 X6
(AB) X12 X13 X15 0 14
(AB’) X8 X9 X11 X10

b = A’C 130
 CD

AB (C’D’) (C’D) (CD) (CD’)

(A’B’) X0 X1 X3 02
(A’B) X4 15 17 X6
(AB) X12 X13 X15 0 14
(AB’) X8 X9 X11 X10
c=D

CD
AB (C’D’) (C’D) (CD) (CD’)
(A’B’) X0 X1 X3 12
(A’B) X4 15 07 X6
(AB) X12 X13 X15 1 14
(AB’) X8 X9 X11 X10
d = C`+ D’ 131
 CD

AB (C’D’) (C’D) (CD) (CD’)

(A’B’) X0 X1 X3 12
(A’B) X4 05 07 X6
(AB) X12 X13 X15 1 14
(AB’) X8 X9 X11 X10
e = D’

CD
AB (C’D’) (C’D) (CD) (CD’)
(A’B’) X0 X1 X3 02
(A’B) X4 15 07 X6
(AB) X12 X13 X15 0 14
(AB’) X8 X9 X11 110

f = C’ + AB’ 132
 CD

AB (C’D’) (C’D) (CD) (CD’)

(A’B’) X0 X1 X3 12
(A’B) X4 15 07 X6
(AB) X12 X13 X15 1 14
(AB’) X8 X9 X11 X10

g =C’ + D’

Step 4: Logical Diagram for

a =A’ + C
b = A’C
c=D
d = C`+ D’
e = D’
f = C’ + AB’
g =C’ + D’
133
Step 4:
Logical
Diagram

134
 Assignment !!
1. Design circuit that can display 2,5,7 and E in seven
segments.
2. Design circuit diagram for code converter.
3. Design a circuit that display 4, 5 and 8 in 7 segment
display.
4. Convert 10101 BCD code into corresponding Gray code.

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~ The End ~

Thank u !!