Vietnam National University

Integrated Circuit Design Research and Education Center

BASIC CONSTRAINTS 2

Teacher: Nguyễn Hùng Quân

(Specification and Coding Engineer)
Email: [email protected]

Do not copy and only use for this course

CONTENTS Product in Mind

 Initial reset (cont)

 Clocks
 Handling of asynchronous circuits
 Hierarchical design

(2)
DOCUMENT CONVENTIONS Product in Mind

 Mandatory
 Recommend
– level 1
– level 2
– level 3
 Reference

(3)
 Vietnam National University
Integrated Circuit Design Research and Education Center

Integrated Circuit Design Fundamental

INITIAL RESET
Reset line hazards Product in Mind

Logic order may be replaced by synthesis

Hazards cannot be prevented in the RTL description

(5)
Reset line hazards (cont) Product in Mind

 [1] and [3]

Using EX_X to to avoid
hazards Logic order is replaced

The result of optimization

is depending on the
timing of the input signals (6)
Reset line hazards (cont) Product in Mind

 Difficult to discover a problem => [2] => generating a

separate block.
 Advantage: easier to apply synthesis constraints

Compiling

(7)
External noise on an initial reset signal Product in Mind
sự cố ,trục trặc

(8)
External noise on an initial reset signal Product in Mind

 The reset line is unstable:

– slowly sloped waveforms

– waveforms with a lot of noise are directly input from

outside the LSI
Large-Scale Intergration

Problem?
(9)
External noise on an initial reset signal Product in Mind

 May violate Setup and Hold times

rst_n

Solution?
(10)
External noise on an initial reset signal Product in Mind

 Synchronizing the reset signal

Problem?
(11)
External noise on an initial reset signal Product in Mind

 Some systems which are used the Auto reset or Power-

on reset, is not used the FF to synchronize

stable slower slowest

Synchronization is impossible
The method to
The reset signal is supplied reduce the noise?
directly
(12)
External noise on an initial reset signal Product in Mind

 Reducing the noise: Using a Schmitt trigger I/O, a VDD

and GND for the I/O pin

Why?

(13)
External noise on an initial reset signal Product in Mind

 Reducing the noise: Adding a DLY element to prevent

hazards

But no countermeasure
is perfect
(14)
 Vietnam National University
Integrated Circuit Design Research and Education Center

Integrated Circuit Design Fundamental

CLOCKS
Creating modules for clock generation
circuits Product in Mind

(16)
Creating modules for clock generation
circuits Product in Mind

 Manages easily
 Easily applied clock
constraints for each level of
hierarchy
 Easily implemented clock
controls during test design

easier to use
the clock tree
optimization function
during layout
(17)
Use clock tree synthesis for clock
balancing Product in Mind

phù hợp

 The Clock Tree Synthesis (CTS) tool is used to

synthesize the clock after the placement of each FF in
the layout.

 The clock lines extend from the center in an H-shaped

tree structure.

(18)
Use clock tree synthesis for clock
balancing Product in Mind

 Arrivel time depending on the number of FFs and the

length of the interconnect lines

Dummy buffer Adjust the

arrivel time

Don’t use
other buffers
or delay cells
(19)
Use clock tree synthesis for clock
balancing Product in Mind

 To adjust the arrival time between different clocks,

adjust by inserting delay cells.

 Too many clock lines, this adjustment process becomes

laborious (difficult)

 the designer should be aware of the approximate

number of FFs connected to each clock line for load
balancing these clock lines

(20)
Gated clocks Product in Mind

 Low-power technology: Turn off the clock, turn off the

switching on clock network

What is clock
gating?

(21)
Gated clocks Product in Mind

(22)
Gated clocks Product in Mind

 [1] Loses the clock tree balancing

 [2] Because the CTS tool cannot take the clock line
balancing => be limited to the clock generator module
located in the topmost level.

(23)
Gated clocks Product in Mind

 [4] The clock line is connected a logical gate => the

logic synthesis tool cannot perform optimization.

extremely dangerous because the

timing cannot be analyzed correctly

(24)
Gated clocks Product in Mind

 [6] the ASIC library may be two types of FFs:

– positive clock edge
– negative clock edge
 The two types of FFs are mixed có vấn đề
in a circuit => scan
register insertion becomes problematic. => not to use
FFs that work on an inverted clock.

(25)
Multiple clock systems Product in Mind

If do not creat
the sub-block?

 [1] to avoid a racing problem during simulation and to

facilitate clock synthesis during layout.
(26)
Multiple clock systems Product in Mind

 Converting the multiple clock to single clock

(27)
Multiple clock systems Product in Mind

 If external data is stable and its operating frequency is

lower than the internal clock, all signals should be
synchronized by the internal clock.
 Example 1:

(28)
Multiple clock systems Product in Mind

 Example 2: When T_internal_clk < T_external_clk

Pay attention to metastable measures

(29)
Multiple clock systems Product in Mind

 [2] provide a multiple cycle relationship as much as

possible.

 The logic synthesis tool:

– 2 clocks: 12ns and 6ns => tool optimizes with the basic
cycle set to 12ns
– 2 clocks: 12ns, 15ns => 60ns
– 2 clocks: 12ns and 14ns => 84ns

(30)
 Vietnam National University
Integrated Circuit Design Research and Education Center

Integrated Circuit Design Fundamental

ASYNCHRONOUS CIRCUITS
Consider metastable issues in signals
between asynchronous clocks Product in Mind

 Terms “metastable” – a difficult problem when

transmitting data between asynchronous clocks

 FFs have specified setup times and hold times. The

metastable problem may occur when the setup time or
hold time specifications are violated.

(32)
Consider metastable issues in signals
between asynchronous clocks Product in Mind

 Assume the left-hand loop (2) is stabilized at ’0’ and the

right side is stabilized at ’1’.
 (1) is opened when CLK is low

(33)
Consider metastable issues in signals
between asynchronous clocks Product in Mind

 Operation

Operation of D Latch?

(34)
Consider metastable issues in signals
between asynchronous clocks Product in Mind

 Metastable State
– D input changes from ’0’ to ’1’ + the CLK signal changes
from low to high (the rising edge)
– ’1’ is sent to the left-hand loop (2) for only an instant =>
the loop (2) can begin to oscillate => the loop (4)
oscillates
– => Output oscillates

Risk?

(35)
Consider metastable issues in signals
between asynchronous clocks Product in Mind

(36)
Consider metastable issues in signals
between asynchronous clocks Product in Mind

 The power supply voltages of 3.3V => 2.5V => 1.9V =>
lower
– Advantage: The I/O operating speed is faster
– Dis-advantage: More sensitive to noise
 => [4]

(37)
Consider metastable issues in signals
between asynchronous clocks Product in Mind

 Sending Data Between Asynchronous Clocks

Setup/hold time violation

solution?
metastable state The read value is wrong
(38)
Consider metastable issues in signals
between asynchronous clocks Product in Mind

 The method where CLK1 is latched by CLK2

Why?

The potential for the Insert an

metastable problem to occur additional FF
(39)
Consider metastable issues in signals
between asynchronous clocks Product in Mind

(40)
Use memory in transfers between
asynchronous same-period clocks Product in Mind

 [1]

RAM
Using a enable signal to
pause in the data being
input Why?
(41)
Guaranteeing the setup/hold margin for
synchronous RAM Product in Mind

 The RAM that is used inside LSIs and FPGAs is mostly

synchronous RAM.

 => must consider ways to ensure the hold time. [1][2]

(42)
Guaranteeing the setup/hold margin for
synchronous RAM Product in Mind

 Method 1: Using logic synthesis tools by commands

(small hold time ~ ps).
 Method 2: Inserting the buffers.

 Example: At 0.18um, 0.13um, hold time = 1ns =>

inserting 50 or more buffers (PROBLEMS?)

(43)
Guaranteeing the setup/hold margin for
synchronous RAM Product in Mind

 Method 3: Using a latch on the inverted clock.

 => the hold time value of the synchronous RAM is less
than half of the clock period.

 Two advantges: ?????????????????????

(44)
Guaranteeing the setup/hold margin for
synchronous RAM Product in Mind

 [4] To simplify:
– Inserts BIST (Built In Self Test) into the RAM for automatic
testing.
– Layout

(45)
Guaranteeing the setup/hold margin for
synchronous RAM Product in Mind

 RAM is used within the IP, RAM cell names, I/O pin
names, and specifications will vary depending on the
ASIC library used.

(46)
 Vietnam National University
Integrated Circuit Design Research and Education Center

Questions and
Discussion