PD - 96199A

IRF1324PbF
HEXFET® Power MOSFET
Applications D
VDSS 24V
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply RDS(on) typ. 1.2m:
l High Speed Power Switching max. 1.5m:
l Hard Switched and High Frequency Circuits G
ID (Silicon Limited) 353A c
Benefits S ID (Package Limited) 195A
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free S
D
G
TO-220AB
IRF1324PbF

G D S
Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 353 c
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 249 c A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Wire Bond Limited) 195
IDM Pulsed Drain Currentd 1412
PD @TC = 25°C Maximum Power Dissipation 300 W
Linear Derating Factor 2.0 W/°C
VGS Gate-to-Source Voltage ± 20 V
dv/dt Peak Diode Recovery f 0.46 V/ns
TJ Operating Junction and
-55 to + 175
TSTG Storage Temperature Range
°C
Soldering Temperature, for 10 seconds
300
(1.6mm from case)
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy e 270 mJ
IAR Avalanche Currentd See Fig. 14, 15, 22a, 22b A
EAR Repetitive Avalanche Energy g mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Casej ––– 0.50
RθCS Case-to-Sink, Flat Greased Surface 0.50 ––– °C/W
RθJA Junction-to-Ambient j ––– 62

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IRF1324PbF

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 24 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 22 ––– mV/°C Reference to 25°C, ID = 5.0mA d
RDS(on) Static Drain-to-Source On-Resistance ––– 1.2 1.5 mΩ VGS = 10V, ID = 195A g
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 24V, VGS = 0V
––– ––– 250 VDS = 24V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
RG Internal Gate Resistance ––– 2.3 ––– Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 180 ––– ––– S VDS = 10V, ID = 195A
Qg Total Gate Charge ––– 160 240 ID = 195A
Qgs Gate-to-Source Charge ––– 84 ––– VDS = 12V
Qgd Gate-to-Drain ("Miller") Charge ––– 49 –––
nC
VGS = 10V g
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 76 ––– ID = 195A, VDS =0V, VGS = 10V
td(on) Turn-On Delay Time ––– 17 ––– VDD = 16V
tr Rise Time ––– 190 ––– ID = 195A
ns
td(off) Turn-Off Delay Time ––– 83 ––– RG = 2.7Ω
tf Fall Time ––– 120 ––– VGS = 10V g
Ciss Input Capacitance ––– 7590 ––– VGS = 0V
Coss Output Capacitance ––– 3440 ––– VDS = 24V
Crss Reverse Transfer Capacitance ––– 1960 ––– pF ƒ = 1.0 MHz, See Fig. 5
Coss eff. (ER) Effective Output Capacitance (Energy Related) ––– 4700 ––– VGS = 0V, VDS = 0V to 19V i, See Fig. 11
Coss eff. (TR) Effective Output Capacitance (Time Related) ––– 4490 ––– VGS = 0V, VDS = 0V to 19V h
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current
c MOSFET symbol D

––– ––– 353

(Body Diode) showing the
A G
ISM Pulsed Source Current integral reverse
(Body Diode) d ––– ––– 1412
p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 195A, VGS = 0V g
trr Reverse Recovery Time ––– 46 ––– TJ = 25°C VR = 20V,
ns
––– 71 ––– TJ = 125°C IF = 195A
Qrr Reverse Recovery Charge ––– 160 –––
nC
TJ = 25°C di/dt = 100A/µs g
––– 430 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 7.7 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 195A. Note that current Pulse width ≤ 400µs; duty cycle ≤ 2%.
limitation arising from heating of the device leds may occur with † Coss eff. (TR) is a fixed capacitance that gives the same charging time
some lead mounting arrangements. as Coss while VDS is rising from 0 to 80% VDSS .
‚ Repetitive rating; pulse width limited by max. junction ‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as
temperature. Coss while VDS is rising from 0 to 80% VDSS.
ƒ Limited by TJmax, starting TJ = 25°C, L = 0.014mH ˆ Rθ is measured at TJ approximately 90°C
RG = 25Ω, IAS = 195A, VGS =10V. Part not recommended for use
above this value .
„ ISD ≤ 195A, di/dt ≤ 450 A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
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 IRF1324PbF
10000 10000
VGS VGS
≤60µs PULSE WIDTH TOP 15V ≤60µs PULSE WIDTH TOP 15V
Tj = 25°C 10V Tj = 175°C 10V
1000 8.0V 8.0V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
4.5V
1000 4.5V
100 BOTTOM 4.0V BOTTOM 4.0V

10
100

1
4.0V
4.0V
0.1 10
0.1 1 10 100 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.0
ID = 195A

RDS(on) , Drain-to-Source On Resistance

VGS = 10V
ID, Drain-to-Source Current (A)

100
T J = 175°C 1.5
(Normalized)

T J = 25°C
10

1.0
1

VDS = 15V
≤60µs PULSE WIDTH
0.1 0.5
2 3 4 5 6 7 8 9 -60 -40 -20 0 20 40 60 80 100120140160180

VGS, Gate-to-Source Voltage (V) T J , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

100000 14.0
VGS = 0V, f = 1 MHZ
ID= 195A
C iss = C gs + C gd, C ds SHORTED
C rss = C gd 12.0 VDS= 19V
VGS, Gate-to-Source Voltage (V)

C oss = C ds + C gd VDS= 12V

10.0
C, Capacitance (pF)

8.0
10000 Ciss
Coss 6.0

Crss 4.0

2.0

1000 0.0
1 10 100 0 50 100 150 200
VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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 IRF1324PbF
1000 10000
OPERATION IN THIS AREA
LIMITED BY R DS(on)

ID, Drain-to-Source Current (A)

ISD, Reverse Drain Current (A)

TJ = 175°C 1000
100µsec
100
1msec

100

T J = 25°C Limited by
package
10
10msec
10
Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse DC
1.0 1
0.0 0.5 1.0 1.5 1 10 100
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area
Forward Voltage

V(BR)DSS , Drain-to-Source Breakdown Voltage (V)

400 32
Id = 5mA
350
Limited By Package

300 30
ID, Drain Current (A)

250

200 28

150

100 26

50

0 24
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180

T C , Case Temperature (°C) T J , Temperature ( °C )

Fig 9. Maximum Drain Current vs. Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
2.0 1200
EAS , Single Pulse Avalanche Energy (mJ)

ID
1.8
TOP 44A
1000
1.6 83A
BOTTOM 195A
1.4
800
1.2
Energy (µJ)

1.0 600
0.8
400
0.6

0.4
200
0.2

0.0 0
-5 0 5 10 15 20 25 30 25 50 75 100 125 150 175

VDS, Drain-to-Source Voltage (V) Starting T J , Junction Temperature (°C)

Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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 IRF1324PbF

1
Thermal Response ( Z thJC ) °C/W

D = 0.50

0.1 0.20

0.10
R1
R1
R2
R2
R3
R3
R4
R4
Ri (°C/W) τi (sec)
0.05 0.0125 0.000008
τJ τC
τJ τ
τ1 0.0822 0.000078
0.02 τ1
τ2 τ3 τ4
0.01 τ2 τ3 τ4 0.2019 0.001110
0.01
Ci= τi/Ri 0.2036 0.007197
Ci i/Ri
Notes:
SINGLE PULSE 1. Duty Factor D = t1/t2
( THERMAL RESPONSE ) 2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000

Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
Avalanche Current (A)

100
0.05

0.10

10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth

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IRF1324PbF
300
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
250 ID = 195A Notes on Repetitive Avalanche Curves , Figures 14, 15:
EAR , Avalanche Energy (mJ)

(For further info, see AN-1005 at www.irf.com)

200 1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
150 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
100 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
50 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
0
D = Duty cycle in avalanche = tav ·f
25 50 75 100 125 150 175 ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav

Fig 15. Maximum Avalanche Energy vs. Temperature

4.5
VGS(th) , Gate threshold Voltage (V)

4.0

3.5

3.0
ID = 250µA
2.5 ID = 1.0mA
ID = 1.0A
2.0

1.5

1.0
-75 -50 -25 0 25 50 75 100 125 150 175 200
T J , Temperature ( °C )

Fig 16. Threshold Voltage vs. Temperature

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 IRF1324PbF
Driver Gate Drive
P.W.
D.U.T P.W.
Period D=
Period
+

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Current
Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS

Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms
RD
VDS VDS

VGS
90%
D.U.T.
RG
+
- VDD

V10V
GS 10%
Pulse Width ≤ 1 µs VGS
Duty Factor ≤ 0.1 %
td(on) tr t d(off) tf

Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Current Regulator Id
Same Type as D.U.T. Vds

Vgs
50KΩ

12V .2µF
.3µF

+
V
D.U.T. - DS
Vgs(th)
VGS

3mA

IG ID
Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr

Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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IRF1324PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

(;$03/( 7+,6,6$1,5)

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TO-220AB packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/2009
8 www.irf.com
IMPORTANT NOTICE
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