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PS4DCS

The document is a problem sheet for a course on Digital Circuits and Systems, focusing on sequential circuits including latches, flip-flops, counters, and finite state machines. It contains various design problems and tasks related to flip-flops, counters, state diagrams, and timing analysis. The problems require circuit diagrams, truth tables, and output waveform analysis for different configurations and sequences.

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6 views

PS4DCS

The document is a problem sheet for a course on Digital Circuits and Systems, focusing on sequential circuits including latches, flip-flops, counters, and finite state machines. It contains various design problems and tasks related to flip-flops, counters, state diagrams, and timing analysis. The problems require circuit diagrams, truth tables, and output waveform analysis for different configurations and sequences.

Uploaded by

aiswaryab240404ec
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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NATIONAL INSTITUTE OF TECHNOLOGY CALICUT

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING


EC1004E-Digital Circuits and Systems
Problem sheet-4

Topics included: Sequential Circuits - Latches, Flip flops, Counters, Registers, Design
considerations,Timing Diagrams, Hazards, Finite state machines

1. Using T-flip flop design SR flip flop with proper circuit diagram and truth table.
2. Using D-flip flop design a synchronous counter with repeating sequence 000, 010, 101 and 110
3. In a 4-bit right shift register, how many clock pulses are required to change the content of register
to all 1’s?

4. Design a synchronous counter for sequence 0,1,3,4,5,7,0,1,3,4,5,7,0. . . . . . . . . using T flip flops.


5. The waveforms shown in below given figure are applied to (a) a positive edgetriggered S-R flip-flop
and (b) a negative edge-triggered S-R flip-flop. Draw the output waveform in each case.

6. The following serial data are applied to the flip-flop shown in figure. J1 = 10110110, J2 = 11011001, K1 =
10010110, K2 = 11011011. Determine the resulting serial data that appears on the Q output. There
is one clock pulse for each bit time. Assume that, Q is initially 0. The rightmost bits are applied
first.

7. Design the following counters:


(a) A mod-7 asynchronous counter using J-K FFs.
(b) A mod-7 synchronous counter using S-R FFs.
(c) A 3-bit Gray code synchronous counter using D FFs.

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8. The state diagram of a FSM designed to detect an overlapping sequence of 3 bits is shown in the
figure. The FSM has an input In and output Out. The initial state of the FSM is S0. If the input
sequence is 101101101, starting with the leftmost bit, determine the output sequence.

9. Design a Moore machine that can detect the presence of a non overlapping sequence 1101 in a given
bit stream.
10. Design a circuit to generate the signal Y from the signal X

11. In the circuit gate A, gate B, gate C and gate D have delays of 10ns, 20ns, 10ns, 10ns and 20ns
respectively. If the initial values of the inputs w, x, y and z are 0,0,0 and 1 respectively, and if x
changes to 1 at time t = 10ns, plot the timing waveform of F1 , F2 , F3 and F . Check whether F
suffers from a hazard. If so, what type of hazard?

12. Analyze the given sequential circuit and find the corresponding state diagram

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