SE Sem-IV

Microprocessor
CSC405
Module - 2
Instruction Set and Programming
By Prof. Sunil Katkar
Department of Computer Engineering, VCET
 Module - 2
Instruction Set and Programming
Objective
To emphasize on instruction set and logic to build assembly
language programs.
Outcome
At the end of the course student will be able to:
Write assembly, mixed language programs using instruction
set of 8086 and analyze updated values of control flag after
execution of assembly language program.
 Module -2
Instruction Set and Programming

2.1 - Addressing Modes

2.2 - Instruction set-Data Transfer Instructions, String
Instructions, Logical Instructions, Arithmetic Instructions,
Transfer of Control Instructions, Processor Control
Instructions
2.3 - Assembler Directives and Assembly Language
Programming, Macros, Procedures
ADDRESSING MODES
 8086 Microprocessor
Addressing Modes

Every instruction of a program has to operate on a data.

The different ways in which a source operand is denoted
in an instruction are known as addressing modes.

1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes for
10. Indirect I/O port Addressing I/O ports

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing mode

5
 8086 Microprocessor Group I : Addressing modes for
Addressing Modes register and immediate data

1. Register Addressing The instruction will specify the name of the

register which holds the data to be operated by
2. Immediate Addressing the instruction.
3. Direct Addressing Example:
4. Register Indirect Addressing
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL

7. Based Index Addressing (CL)  (DH)

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

6
 8086 Microprocessor Group I : Addressing modes for
Addressing Modes register and immediate data

1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL

7. Based Index Addressing (DL)  08H

8. String Addressing
MOV AX, 0A9FH
9. Direct I/O port Addressing
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing
moved to AX register
11. Relative Addressing
(AX)  0A9FH
12. Implied Addressing

7
8086 Microprocessor
Addressing Modes : Memory Access

20 Address lines  8086 can address up to

220 = 1M bytes of memory

However, the largest register is only 16 bits

Physical Address will have to be calculated

Physical Address : Actual address of a byte in
memory. i.e. the value which goes out onto the
address bus.

Memory Address represented in the form –

Seg : Offset (Eg - 89AB:F012)

Each time the processor wants to access

memory, it takes the contents of a segment
register, shifts it one hexadecimal place to the
16 bytes of
left (same as multiplying by 1610), then add the contiguous memory
required offset to form the 20- bit address

89AB : F012 → 89AB → 89AB0 (Paragraph to byte → 89AB x 10 = 89AB0)

F012 → 0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
9
 8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing

2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.

5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing
Example:
7. Based Index Addressing
MOV AL, [1000H] Assume DS=2000H
8. String Addressing MOV BX, [1354H]
9. Direct I/O port Addressing
The square brackets around the 1354H denotes
the contents of the memory location. When
10. Indirect I/O port Addressing
executed, this instruction will copy the contents of
11. Relative Addressing the memory location into BX register.

12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.

11
 8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing In Register indirect addressing, name of the

register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.

3. Direct Addressing Registers used to hold EA are any of the following

registers:
4. Register Indirect Addressing
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
6. Indexed Addressing
address calculation.
7. Based Index Addressing
Example:
Note : Register/ memory
8. String Addressing enclosed in brackets refer
MOV CX, [BX]
to content of register/
9. Direct I/O port Addressing memory
Operations:
10. Indirect I/O port Addressing
EA = (BX) BX = 1250H
11. Relative Addressing BA = (DS) x 10 DS = 4000H
MA = BA + EA MA = 41250
12. Implied Addressing (CX)  (MA) or,

(CL)  (MA) 41250H → CL

(CH)  (MA +1) 41251H → CH

12
 8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing In Based Addressing, BX or BP is used to hold the

base value for effective address and a signed 8-bit
2. Immediate Addressing or unsigned 16-bit displacement will be specified
in the instruction.
3. Direct Addressing
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.

5. Based Addressing When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.
6. Indexed Addressing
When BP holds the base value of EA, BP and SS is
7. Based Index Addressing
used.
8. String Addressing
Example:
9. Direct I/O port Addressing
MOV AX, [BX +0008H]
10. Indirect I/O port Addressing
Operations:
11. Relative Addressing EA = (BX) + 0008H
BA = (DS) x 10
12. Implied Addressing MA = BA + EA

(AX)  (MA) or,

(AL)  (MA)
(AH)  (MA + 1) 13
 8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing SI or DI register is used to hold an index value for

memory data and a signed 8-bit or unsigned 16-
2. Immediate Addressing bit displacement will be specified in the
instruction.
3. Direct Addressing
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.

5. Based Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.
6. Indexed Addressing

7. Based Index Addressing

Example:
8. String Addressing
MOV CX, [SI + FF0A2H]
9. Direct I/O port Addressing
Operations:
10. Indirect I/O port Addressing
EA = (SI) + FFA2H
11. Relative Addressing BA = (DS) x 10
MA = BA + EA
12. Implied Addressing
(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)
14
 8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing In Based Index Addressing, the effective address

is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
3. Direct Addressing

4. Register Indirect Addressing

Example:
5. Based Addressing
MOV DX, [BX + SI + 000AH]
6. Indexed Addressing

7. Based Index Addressing

Operations:
8. String Addressing

9. Direct I/O port Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 10
10. Indirect I/O port Addressing MA = BA + EA
11. Relative Addressing
(DX)  (MA) or,
12. Implied Addressing
(DL)  (MA)
(DH)  (MA + 1)

15
 8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing Employed in string operations to operate on string

data.
2. Immediate Addressing
The effective address (EA) of source data is stored
3. Direct Addressing in SI register and the EA of destination is stored in
DI register.
4. Register Indirect Addressing
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES
6. Indexed Addressing

7. Based Index Addressing

Example: MOVS BYTE
8. String Addressing
Operations:
9. Direct I/O port Addressing
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 10 MA = BA + EA

11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 10 MAE = BAE + EAE
12. Implied Addressing

Note : Effective address of (MAE)  (MA)

the Extra segment register
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI)  (SI) +1 and (DI) = (DI)16+ 1
 8086 Microprocessor Group III : Addressing
Addressing Modes modes for I/O ports

1. Register Addressing These addressing modes are used to access data

from standard I/O mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.

4. Register Indirect Addressing Example: IN AL, [09H]

5. Based Addressing Operations: PORTaddr = 09H

(AL)  (PORT)
6. Indexed Addressing
Content of port with address 09H is
7. Based Index Addressing
moved to AL register
8. String Addressing
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing will specify the name of the register which holds
the port address. In 8086, the 16-bit port address
10. Indirect I/O port Addressing is stored in the DX register.

11. Relative Addressing Example: OUT [DX], AX

12. Implied Addressing Operations: PORTaddr = (DX)

(PORT)  (AX)

Content of AX is moved to port

whose address is specified by DX
register. 17
 8086 Microprocessor Group IV : Relative
Addressing Modes Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing In this addressing mode, the effective address of

a program instruction is specified relative to
4. Register Indirect Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
5. Based Addressing
Example: JZ 0AH
6. Indexed Addressing
Operations:
7. Based Index Addressing

8. String Addressing 000AH  0AH (sign extend)

9. Direct I/O port Addressing If ZF = 1, then

10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 10
11. Relative Addressing MA = BA + EA

12. Implied Addressing If ZF = 1, then the program control jumps to

new address calculated above.

If ZF = 0, then next instruction of the

program is executed.
18
 8086 Microprocessor Group IV : Implied
Addressing Modes Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

19
INSTRUCTION SET
Rules while executing the Instruction

21
8086 Microprocessor
Instruction Set

8086 supports 6 types of instructions.

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. String manipulation Instructions

5. Process Control Instructions

6. Control Transfer Instructions

22
8086 Microprocessor
Instruction Set

1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to

registers, memory locations and I/O ports.

Generally involve two operands: Source operand and

Destination operand of the same size.

Source: Register or a memory location or an immediate data

Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory

and a 16-bit data can be moved to 16-bit register/ memory.

23
Data Transfer Instructions

24
 MOV destination register, source register

MOV AX, BX

25
 MOV memory. accumulator

MOV [SI], AL

Let, CS → 2105 H
IP → 187A H, DS → 2314 H,
AL → 20H, SI → 1023

26
 MOV accumulator, memory

MOV AX, Temp_Result

Let, CS → 2105 H
IP → 187A H, DS → 2314 H,
Temp_Result → FF H,
AH → 00 H and AL → 0A H

27
 MOV register, memory
# MOV CX, COUNT [DI]

Let, CS → 2105 H
IP → 187A H, DS → 2314 H,
DI → 1100 H,
AH → AA H and AL → 2B H
COUNT offset → 1000 H

28
# MOV memory, register # MOV register, immediate

MOV COUNT[DI], CX MOV CL, 02 H

# MOV memory, immediate

MOV COUNT[DI], 2DH

Let, CS → 2105H, IP → 2105H, DI → 1100H,

COUNT → 1000H, DS → 2314H

EA = COUNT + DI

PA = DS + EA

29
# MOV seg-reg, reg-16 # MOV seg-reg, mem-16

MOV DS, AX MOV DS, [SI]

# MOV reg-16, seg-reg # MOV memory, seg-reg

MOV AX, DS MOV COUNT, DS

30
 PUSH – Push word onto stack

# PUSH Source

SP = SP – 2

SS : [SP]

PUSH AX

Let, SS → 4523H, SP → 2586H,

CS → 2105H, IP → 187AH,

AH → FFH & AL → AAH

PA = 45230H+ 2586H = 477B6 H

31
 POP – Pop word off stack

# POP Destination POP AX

# POP Operand Let, SS → 4523H, SP → 2586H,

SP = SP + 2 CS → 2105H, IP → 187AH,
SS : [SP]
PA = 45230H+ 2586H = 477B6 H

Contents of 477B6H → 3BH & 477B7H → 2AH

32
 XCHG – Exchange byte or word

# XCHG destination, source

XCHG AX, BX

33
XLAT/XLATB : Translate or Replace Byte

34
35
36
Addition

37
 ADD register, register

Register Addressing Mode

# ADD BL, CL All Flags are affected

38
 ADD register, memory

ADD AX, [2048]

Let,
DS → 2314 H

Offset → 2048

Physical Address

23140 + 2048
=25188

2005 + 1024 =
3029

39
 ADD memory, register

ADD [2048], AX

Let,
DS → 2314 H

Offset → 2048

Physical Address

23140 + 2048
=25188

2005 + 1024 =
3029

40
 ADD register, immediate
ADD accumulator, immediate

ADD AL, 74 H

74 + 24 = 98

41
 ADD memory, immediate data

ADD [5214], 75

Let,
DS → 2314 H

Offset → 5214

Physical Address

23140 + 5214
=28354

75 H + 14 H = 89 H

42
 ADC – Add with carry
ADC AL, BL
20 H + 34 H + 01 = 55 H

43
 INC – Increment byte or word by 1

INC Destination

INC AL

INC CX

44
 DAA – Decimal adjust for addition

DAA AL  Sum in AL adjusted to

If lower nibble of AL > 9 or AF = 1, packed BCD format
then
AL = AL + 06H AL = 0101 1001 = 59 BCD
AF = 1 BL = 0011 0100 = 34 BCD
If upper nibble of AL > 9 or CF = 1,
then ADD AL, BL
AL = AL + 60H DAA
CF = 1

01011001+ 00110100
= 1000 1101
= 8D BCD
Lower nibble = 1101 = F > 9
therefore,
10001101 + 00000110
= 1001 0011
= 93 BCD 45
Address Object Instructions

46
 LEA – Load Effective Address
# LEA register, source

Reg. = Address of
memory (offset)

LEA AX, COUNT

47
 LDS – Load pointer with DS

# LDS register, source

REG = First word

DS = Second word

REG  Source, DS  (Source + 2)

# LDS BX, Count

Let, Offset of Count = 2045, DS → 2314H, CS → 2105H,

IP → 187AH, ES → 2010H

PA = 23140H + 2045H = 25185H

48
LDS – Load pointer with DS

LDS BX, Count

49
50
 SUB Register, Register

SUB BL, CL H 07 - 04 = 03

SUB CH, BL

Let, CH → 28H (i.e. 0010 1000)

BL → 46H ( i.e. 0100 0110)

CH → - 30H (i.e. 1110 0010)

CF = 1, OF = 0, SF = 1

SUB CH, BL

Let, CH → 6AH (i.e. 0110 1010)

BL → 7AH ( i.e. 0111 1010)

CH → 78H (i.e. 1111 000)

ZF=AF=0, PF = 1, OF = 1, SF = 1, CF = 1
51
52
 Flag Register

0 1 1 0 1 0 1 0
0 1 1 1 1 0 1 0
1 1 1 1
1 1 1 1 1 0 0 0 0
ZF=AF=0, PF = 1, OF = 1, SF = 1, CF = 1

53
 SUB memory, register

SUB [2048], AX

Let,
CS → 2105 H,
IP → 187A H
DS → 2314 H
Offset → 2048H

Physical Address

23140 + 2048
=25188

2024 - 1005 =
101FH

54
 SUB Register, memory

Register  register – contents of memory location

SUB AX, [2048]

55
 SUB Register, immediate
SUB accumulator, immediate
Register  register – immediate data

SUB AL, 24H

56
 SUB memory, immediate data

memory  memory – immediate data

SUB COST, 14H

Let, CS→ 2105H, IP = 187AH, DS = 2314H, offset (ie COST) = 5214

Immediate number = 75H

PA = 23140H + 5214H = 28354H

57
 SBB Subtract byte or word with borrow

SBB destination, source

destination  destination – source – CY Flag (i.e. Borrow)
SBB AL, BL
AL  AL – BL – CY
Let, AL = 34H, BL = 24H, CY = 1

58
 DEC - Decrement byte or word by 1
DEC destination
destination  destination – 1
DEC AL
AL  AL – 1
Let, AL = 09H

59
 AAS – ASCII adjust for subtraction
AAS
If lower nibble of AL > 9 or AF = 1, then Let AL = 0011 1001
AL = AL – 06H = 39H = ASCII 9
AH = AH – 1 Let BL = 0011 0101
AF = 1 = 35H = ASCII 5
CF = 1 SUB AL, BL
AAS
else
= 0011 1001 – 0011 0101
AF = 0 = 0 0000 0100
CF = 0 = 04 BCD
In both cases clear the high nibble of AL

60
 DAS – Decimal adjust for subtraction

DAS AL  Difference in AL adjusted

If lower nibble of AL > 9 or AF = 1, to packed BCD format
then
AL = AL – 06H AL = 1000 0110 = 86 BCD
AF = 1 BL = 0101 0111 = 57 BCD
If upper nibble of AL > 9 or CF = 1,
then SUB AL, BL
AL = AL -60H DAS
CF = 1

1000 0110 – 0101 0111

= 0010 1111
= 2F BCD
Lower nibble = 1111 = F > 9
therefore,
0010 1111 – 0110
= 0010 1001
= 29 BCD 61
 NEG – Negative byte or word
NEG destination
Invert all bits of operand and add 1 to inverted operand
NEG AX
AX  2’s complement of number in AX
Let, AX = 00A3H = 0000 0000 1010 0011
then 2’s complement will be 1111 1111 0101 1101

62
 CMP – Compare byte or word
CMP destination, source
destination – source
If source > destination, then
CF = 1, ZF = 0, SF = 1
If source < destination, then
CF = 0, ZF = 0, SF = 0
If source = destination, then
CF = 0, ZF = 1, SF = 0

63
Multiplication

64
 MUL - Multiply byte or word (unsigned)

MUL CX
MUL source
(DX:AX) = AX * CX
When operand is a byte:
MSB will be stored in DX
AX = AL * operand
LSB will be stored in AX
When operand is a word
Let, AX = 0009H, CX = 0054H,
(DX:AX) = AX * operand
DX = FFFFH (initial data),
CS = 2105H, IP = 187AH
0009H * 0054H = 02F4H

65
 IMUL - Multiply byte or word (signed)

IMUL source IMUL BL

When operand is a byte: AX = AL * BL
AX = AL * operand Let, AL = 45 H, BL = 0E H
When operand is a word 45 H * 0E H = 03CEH
(DX:AX) = AX * operand MSB = 0, positive result

66
Division Instruction

67
 DIV – Divide byte or word unsigned
DIV source
DIV BH
When operand is a byte:
Let, AX = 37D7 H = 14295 decimal
AL = AX / operand (Quotient)
BH = 97H = 151 decimal
AH = remainder (Modulus)
AL = AX / BH = 5E H = 94 decimal
When operand is a word
AH = 65H = 101 decimal
AX = (DS:AX) / operand (Quotient)
DX = remainder (Modulus)

68
 IDIV – Integer divide byte or word
IDIV source
IDIV BL
When operand is a byte:
Let, AX =03AB H, BL= 00D3 H
AL = AX / operand (Quotient)
AL = AX /BL = EC H
AH = remainder (Modulus)
AH = Remainder = 27 H
When operand is a word
AX = (DS:AX) / operand (Quotient)
DX = remainder (Modulus)

69
 CBW – Convert byte or word

CBW AX = 00AC H = -163 decimal

If MSB bit of AL = 1 then CBW
AH = 255 (FFH) Convert signed byte in AL to sign word
Else in AX
AH = 0 Result : 1111 1111 1010 0011 = -163
decimal

70
 CWD – Convert word to double word
CWD
If MSB bit of AX = 1 then
DX = 65535 (FFFF H)
If DX = 4AA3 H and AX = 00A3 H
Else
DX = 0

71
Logical Group

72
 NOT – NOT byte or word
NOT destination
If bit is 1 turn it to 0
If bit is 0 turn it to 1
NOT AX

73
 AND – And byte or word
AND destination, source
Destination = destination AND source
AND AL, BL

74
 OR –Inclusive OR byte or word
OR destination, source
Destination = destination OR source
OR AL, BL

75
 XOR – Exclusive OR byte or word
XOR destination, source
Destination = destination XOR source
XOR AL, BL

76
 TEST – Test byte or word

TEST destination, source

Destination = destination AND source
TEST AL, 75H

77
Shifts

78
 SHL/SAL – Shift logical/arithmetic left byte
or word

SAL/SHL destination, count

CF  MSB  LSB  0 SHL AX, 01

79
 SHR – Shift logical right byte or word

SHR destination, count

SHR AX, CL
0 → MSB → LSB → CF
Let Ax = 1234 H, CL = 02 H

80
 SAR – Shift arithmetic byte or word

SAR destination, count

MSB → MSB → LSB → CF SAR AX, 1

81
Rotates

82
 ROL – Rotate left byte or word

ROL destination, source ROL AX, 01 H

Let,
AX = 0001 0010 0110 0100
CF = 0

83
 RCR – rotate through carry right byte or
word

RCR destination, count RCR AX, CL

84
 Mixed Language Programming
using Assembly and C

Mixed-language programming is the process of building

programs in which the source code is written in two or more
languages.
It allows you to:

• Call existing code that is written in another language

• Use procedures that may be difficult to implement in a

particular language

• Gain advantages in processing speeds

85
Combining Assembly and C

86
Combining Assembly and C

87
AAA – ASCII adjust for addition

88
DAA – Decimal Adjust Accumulator

89
AAS – ASCII adjust for Subtraction

90
DAS – Decimal Adjust for Subtraction

91
8086 Microprocessor
Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

MOV reg2/ mem, reg1/ mem

MOV reg2, reg1 (reg2)  (reg1)

MOV mem, reg1 (mem)  (reg1)
MOV reg2, mem (reg2)  (mem)

MOV reg/ mem, data

MOV reg, data (reg)  data

MOV mem, data (mem)  data

XCHG reg2/ mem, reg1

XCHG reg2, reg1 (reg2)  (reg1)

XCHG mem, reg1 (mem)  (reg1)

92
8086 Microprocessor
Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

PUSH reg16/ mem

PUSH reg16 (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (reg16)

PUSH mem (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (mem)

POP reg16/ mem

POP reg16 MA S = (SS) x 1610 + SP

(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2

POP mem MA S = (SS) x 1610 + SP

(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2
93
8086 Microprocessor
Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

IN A, [DX] OUT [DX], A

IN AL, [DX] PORTaddr = (DX) OUT [DX], AL PORTaddr = (DX)

(AL)  (PORT) (PORT)  (AL)

IN AX, [DX] PORTaddr = (DX) OUT [DX], AX PORTaddr = (DX)

(AX)  (PORT) (PORT)  (AX)

IN A, addr8 OUT addr8, A

IN AL, addr8 (AL)  (addr8) OUT addr8, AL (addr8)  (AL)

IN AX, addr8 (AX)  (addr8) OUT addr8, AX (addr8)  (AX)

94
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADD reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)

ADC reg2, mem (reg2)  (reg2) + (mem)
ADC mem, reg1 (mem)  (mem)+(reg1)

ADD reg/mem, data

ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data

ADD A, data

ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16

95
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADC reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)+CF

ADC reg2, mem (reg2)  (reg2) + (mem)+CF
ADC mem, reg1 (mem)  (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF

ADDC A, data

ADD AL, data8 (AL)  (AL) + data8+CF

ADD AX, data16 (AX)  (AX) +data16+CF

96
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SUB reg2/ mem, reg1/mem

SUB reg2, reg1 (reg2)  (reg1) - (reg2)

SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)

SUB reg/mem, data

SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data

SUB A, data

SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16

97
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SBB reg2/ mem, reg1/mem

SBB reg2, reg1 (reg2)  (reg1) - (reg2) - CF

SBB reg2, mem (reg2)  (reg2) - (mem)- CF
SBB mem, reg1 (mem)  (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF

SBB A, data

SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF

98
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

INC reg/ mem

INC reg8 (reg8)  (reg8) + 1

INC reg16 (reg16)  (reg16) + 1

INC mem (mem)  (mem) + 1

DEC reg/ mem

DEC reg8 (reg8)  (reg8) - 1

DEC reg16 (reg16)  (reg16) - 1

DEC mem (mem)  (mem) - 1

99
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

MUL reg/ mem

MUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

MUL mem For byte : (AX)  (AL) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

IMUL reg/ mem

IMUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

IMUL mem For byte : (AX)  (AX) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

100
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

DIV reg/ mem

DIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder

DIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

101
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

IDIV reg/ mem

IDIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder

IDIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

102
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags  (reg2) – (reg1)

If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags  (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags  (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0

103
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg/mem, data

CMP reg, data Modify flags  (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0

CMP mem, data Modify flags  (mem) – (mem)

If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0

104
8086 Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP A, data

CMP AL, data8 Modify flags  (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags  (AX) – data16

If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0

105
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

106
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

107
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

108
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

109
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

110
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

111
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

112
8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

113
8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

❑ String : Sequence of bytes or words

❑ 8086 instruction set includes instruction for string movement, comparison,

scan, load and store.

❑ REP instruction prefix : used to repeat execution of string instructions

❑ String instructions end with S or SB or SW.

S represents string, SB string byte and SW string word.

❑ Offset or effective address of the source operand is stored in SI register and

that of the destination operand is stored in DI register.

❑ Depending on the status of DF, SI and DI registers are automatically

updated.

❑ DF = 0  SI and DI are incremented by 1 for byte and 2 for word.

❑ DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

114
8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

REP

REPZ/ REPE While CX  0 and ZF = 1, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) – 1
ZF = 0)

REPNZ/ REPNE While CX  0 and ZF = 0, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) - 1
ZF = 1)

115
8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

MOVS

MOVSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE)  (MA)

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1

If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

MOVSW MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1)  (MA; MA + 1)

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2

If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2

116
8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Compare two string byte or string word

CMPS

CMPSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

Modify flags  (MA) - (MAE)

If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0

If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
CMPSW If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0

For byte operation

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1
If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

For word operation

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2
If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2

117
8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
Scan (compare) a string byte or word with accumulator
SCAS

SCASB MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)

If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0

If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

SCASW MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)

If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 2

118
If DF = 1, then (DI)  (DI) – 2
8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Load string byte in to AL or string word in to AX

LODS

LODSB MA = (DS) x 1610 + (SI)

(AL)  (MA)

If DF = 0, then (SI)  (SI) + 1

If DF = 1, then (SI)  (SI) – 1

LODSW MA = (DS) x 1610 + (SI)

(AX)  (MA ; MA + 1)

If DF = 0, then (SI)  (SI) + 2

If DF = 1, then (SI)  (SI) – 2

119
8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Store byte from AL or word from AX in to string

STOS

STOSB MAE = (ES) x 1610 + (DI)

(MAE)  (AL)

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

STOSW MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1 )  (AX)

If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2

120
8086 Microprocessor
Instruction Set

5. Processor Control Instructions

Mnemonics Explanation
STC Set CF  1

CLC Clear CF  0

CMC Complement carry CF  CF/

STD Set direction flag DF  1

CLD Clear direction flag DF  0

STI Set interrupt enable flag IF  1

CLI Clear interrupt enable flag IF  0

NOP No operation

HLT Halt after interrupt is set

WAIT Wait for TEST pin active

ESC opcode mem/ reg Used to pass instruction to a coprocessor

which shares the address and data bus
with the 8086

LOCK Lock bus during next instruction 121

8086 Microprocessor
Instruction Set

6. Control Transfer Instructions

Transfer the control to a specific destination or target instruction

Do not affect flags

❑ 8086 Unconditional transfers

Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine

RET Return from subroutine

JMP reg/ mem/ disp8/ disp16 Unconditional jump

122
 8086 Microprocessor
Instruction Set

6. Control Transfer Instructions

❑ 8086 signed conditional ❑ 8086 unsigned conditional

branch instructions branch instructions

Checks flags

If conditions are true, the program control is

transferred to the new memory location in the same
segment by modifying the content of IP

123
 8086 Microprocessor
Instruction Set

6. Control Transfer Instructions

❑ 8086 signed conditional ❑ 8086 unsigned conditional

branch instructions branch instructions

Name Alternate name Name Alternate name

JE disp8 JZ disp8 JE disp8 JZ disp8
Jump if equal Jump if result is 0 Jump if equal Jump if result is 0

JNE disp8 JNZ disp8 JNE disp8 JNZ disp8

Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 JNBE disp8
Jump if greater Jump if not less or Jump if above Jump if not below
equal or equal
JGE disp8 JNL disp8 JAE disp8 JNB disp8
Jump if greater Jump if not less Jump if above or Jump if not below
than or equal equal
JL disp8 JNGE disp8 JB disp8 JNAE disp8
Jump if less than Jump if not Jump if below Jump if not above
greater than or or equal
equal
JLE disp8 JNG disp8 JBE disp8 JNA disp8
Jump if less than Jump if not Jump if below or Jump if not above
or equal greater equal 124
8086 Microprocessor
Instruction Set

6. Control Transfer Instructions

❑ 8086 conditional branch instructions affecting individual flags

Mnemonics Explanation

JC disp8 Jump if CF = 1

JNC disp8 Jump if CF = 0

JP disp8 Jump if PF = 1

JNP disp8 Jump if PF = 0

JO disp8 Jump if OF = 1

JNO disp8 Jump if OF = 0

JS disp8 Jump if SF = 1

JNS disp8 Jump if SF = 0

JZ disp8 Jump if result is zero, i.e, Z = 1

JNZ disp8 Jump if result is not zero, i.e, Z = 1

125
Assembler directives
8086 Microprocessor
Assemble Directives

Instructions to the Assembler regarding the program being

executed.

Control the generation of machine codes and organization of

the program; but no machine codes are generated for
assembler directives.

Also called ‘pseudo instructions’

Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..

127
8086 Microprocessor
Assemble Directives

DB Define Byte

DW Define a byte type (8-bit) variable

SEGMENT Reserves specific amount of memory

ENDS locations to each variable

ASSUME Range : 00H – FFH for unsigned value;

00H – 7FH for positive value and
ORG 80H – FFH for negative value
END
EVEN General form : variable DB value/ values
EQU

PROC
FAR Example:
NEAR LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for
SHORT the variable LIST and each data specified in the
instruction are stored as initial value in the reserved
MACRO memory location
ENDM 128
8086 Microprocessor
Assemble Directives

DB Define Word

DW Define a word type (16-bit) variable

SEGMENT Reserves two consecutive memory locations

ENDS to each variable

ASSUME Range : 0000H – FFFFH for unsigned value;

0000H – 7FFFH for positive value and
ORG 8000H – FFFFH for negative value
END
EVEN General form : variable DW value/ values
EQU

PROC
FAR Example:
NEAR ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for
SHORT the variable ALIST and each 16-bit data specified in
the instruction is stored in two consecutive memory
MACRO location.
ENDM 129
8086 Microprocessor
Assemble Directives

DB SEGMENT : Used to indicate the beginning of

a code/ data/ stack segment
DW
ENDS : Used to indicate the end of a code/
SEGMENT data/ stack segment
ENDS
General form:
ASSUME

ORG
END Segnam SEGMENT
EVEN
…
EQU … Program code
… or
PROC … Data Defining Statements
…
FAR …
NEAR
ENDP Segnam ENDS

SHORT

MACRO User defined name of

the segment
ENDM 130
8086 Microprocessor
Assemble Directives

DB Informs the assembler the name of the

program/ data segment that should be used
DW for a specific segment.

SEGMENT General form:

ENDS
ASSUME segreg : segnam, .. , segreg : segnam
ASSUME

ORG
User defined name of
END Segment Register
the segment
EVEN
EQU

PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the compiler that the
ENDP instructions of the program are
stored in the segment ACODE and
data are stored in the segment
SHORT ADATA

MACRO
ENDM 131
8086 Microprocessor
Assemble Directives

ORG (Origin) is used to assign the starting address

DB
(Effective address) for a program/ data segment

DW END is used to terminate a program; statements

after END will be ignored
SEGMENT
ENDS EVEN : Informs the assembler to store program/
data segment starting from an even address
ASSUME
EQU (Equate) is used to attach a value to a variable

ORG
Examples:
END
EVEN ORG 1000H Informs the assembler that the statements
EQU following ORG 1000H should be stored in
memory starting with effective address
1000H
PROC
FAR
LOOP EQU 10FEH Value of variable LOOP is 10FEH
NEAR
ENDP
_SDATA SEGMENT In this data segment, effective address of
SHORT ORG 1200H memory location assigned to A will be 1200H
A DB 4CH and that of B will be 1202H and 1203H.
EVEN
MACRO B DW 1052H
ENDM _SDATA ENDS 132
8086 Microprocessor
Assemble Directives

PROC Indicates the beginning of a procedure

DB
ENDP End of procedure
DW
FAR Intersegment call
SEGMENT
ENDS NEAR Intrasegment call

General form
ASSUME

ORG
procname PROC[NEAR/ FAR]
END
EVEN …
… Program statements of the
EQU procedure
…

PROC RET Last statement of the

procedure
ENDP
FAR procname ENDP
NEAR

SHORT User defined name of

the procedure
MACRO
ENDM 133
8086 Microprocessor
Assemble Directives

DB
Examples:
DW

SEGMENT ADD64 PROC NEAR The subroutine/ procedure named ADD64 is

ENDS declared as NEAR and so the assembler will
… code the CALL and RET instructions involved
… in this procedure as near call and return
ASSUME …

RET
ORG
ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT
is declared as FAR and so the assembler will
… code the CALL and RET instructions involved
PROC … in this procedure as far call and return
ENDP …
FAR
RET
NEAR CONVERT ENDP

SHORT

MACRO
ENDM 134
8086 Microprocessor
Assemble Directives

DB Reserves one memory location for 8-bit

signed displacement in jump instructions
DW
Example:
SEGMENT
ENDS

ASSUME JMP SHORT The directive will reserve one

AHEAD memory location for 8-bit
ORG displacement named AHEAD
END
EVEN
EQU

PROC
ENDP
FAR
NEAR

SHORT

MACRO
ENDM 135
8086 Microprocessor
Assemble Directives

DB MACRO Indicate the beginning of a macro

DW ENDM End of a macro

SEGMENT General form:

ENDS

ASSUME macroname MACRO[Arg1, Arg2 ...]

Program
… statements in
ORG … the macro
END …
EVEN
EQU macroname ENDM

PROC
ENDP
FAR User defined name of
NEAR the macro

SHORT

MACRO
ENDM 136
Interfacing memory and i/o ports
8086 Microprocessor
Memory

Processor Memory
▪ Registers inside a microcomputer
▪ Store data and results temporarily
▪ No speed disparity
▪ Cost 

Primary or Main Memory

▪ Storage area which can be directly
Memory accessed by microprocessor
▪ Store programs and data prior to
Store
execution
Programs
▪ Should not have speed disparity with
and Data
processor  Semi Conductor
memories using CMOS technology
▪ ROM, EPROM, Static RAM, DRAM

Secondary Memory
▪ Storage media comprising of slow
devices such as magnetic tapes and
disks
▪ Hold large data files and programs:
Operating system, compilers,
databases, permanent programs etc. 138
8086 Microprocessor
Memory organization in 8086

Memory IC’s : Byte oriented

8086 : 16-bit

Word : Stored by two

consecutive memory locations;
for LSB and MSB

Address of word : Address of

LSB

Bank 0 : A0 = 0  Even
addressed memory bank

Bank 1 : 𝑩𝑯𝑬 = 0  Odd

addressed memory bank

139
8086 Microprocessor
Memory organization in 8086

Operation 𝑩𝑯𝑬 A0 Data Lines Used

1 Read/ Write byte at an even address 1 0 D7 – D0

2 Read/ Write byte at an odd address 0 1 D15 – D8

3 Read/ Write word at an even address 0 0 D15 – D0

4 Read/ Write word at an odd address 0 1 D15 – D0 in first operation

byte from odd bank is
transferred
1 0 D7 – D0 in first operation
byte from odd bank is
transferred 140
8086 Microprocessor
Memory organization in 8086

Available memory space = EPROM + RAM

Allot equal address space in odd and even

bank for both EPROM and RAM

Can be implemented in two IC’s (one for

even and other for odd) or in multiple IC’s

141
8086 Microprocessor
Interfacing SRAM and EPROM

Memory interface  Read from and write in

to a set of semiconductor memory IC chip

EPROM  Read operations

RAM  Read and Write

In order to perform read/ write operations,

Memory access time  read / write time of

the processor

Chip Select (CS) signal has to be generated

Control signals for read / write operations

Allot address for each memory location

142
8086 Microprocessor
Interfacing SRAM and EPROM

Typical Semiconductor IC Chip

No of Memory capacity Range of

Address address in
pins hexa
In Decimal In kilo In hexa

20 220= 10,48,576 1024 k = 1M 100000 00000

to
FFFFF

143
8086 Microprocessor
Interfacing SRAM and EPROM

Memory map of 8086

EPROM’s are mapped at FFFFFH

 Facilitate automatic execution of monitor programs
and creation of interrupt vector table

RAM are mapped at the beginning; 00000H is allotted to RAM

144
8086 Microprocessor
Interfacing SRAM and EPROM

Monitor Programs
 Programing 8279 for keyboard scanning and display
refreshing

 Programming peripheral IC’s 8259, 8257, 8255,

8251, 8254 etc

 Initialization of stack

 Display a message on display (output)

 Initializing interrupt vector table

Note : 8279 Programmable keyboard/ display controller

8257 DMA controller

8259 Programmable interrupt controller

8255 Programmable peripheral interface

145
8086 Microprocessor
Interfacing I/O and peripheral devices

I/O devices
 For communication between microprocessor and
outside world

 Keyboards, CRT displays, Printers, Compact Discs

etc.


Ports / Buffer IC’s
Microprocessor I/ O devices
(interface circuitry)

 Data transfer types

Memory mapped
Programmed I/ O
Data transfer is accomplished I/O mapped
through an I/O port
controlled by software

Interrupt driven I/ O
I/O device interrupts the
processor and initiate data
transfer
Direct memory access
Data transfer is achieved by 146
bypassing the microprocessor
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