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Description:- Verilog FSM level 1

Developer :- Shah Henisha
Date:- 23/02/2025
email :- [email protected]
Version :- 1.0
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Question
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Draw the state diagram of the FSM implemented by the following
Verilog code and implement the testbench using Verilog to verify
the identified state diagram.
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Code:
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module fsm(in,rst,out,clk);
input in,clk,rst; // adding reset so it does not go in infinite loop
output out;

reg [1:0] PS,NS;

always@(*) begin
case (PS)
2'b00: NS = (in)? 2'b01 : 2'b00;
2'b01: NS = (in) ? 2'b10 : 2'b00;
2'b10: NS = (!in) ? 2'b11 : 2'b00;
2'b11: NS = 2'b00;
endcase
end
always @(posedge clk) begin
if(!rst)
PS<=00;
else begin
PS <= NS;
end
end
assign out = &PS;
endmodule

Testbench:
`timescale 1ns / 1ps
module fsm_tb;

1
 reg in, clk,rst;
wire out;
fsm uut (
.in(in),
.out(out),
.clk(clk),
.rst(rst)
);
always begin
#5 clk = ~clk;
end
initial begin
clk = 0;
rst =0;
#10;
rst =1;
in = 0;
$monitor("Time: %0d | rst = %0b | clk = %b | in = %b | out = %b",
$time, rst, clk, in, out);
// First test: Input = 0 (Expect state 00, out=0)
in = 0;
#10; // Wait for 1 clock cycle for state transition and output update
// Second test: Input = 1 (Expect state 01, out=0)
in = 1;
#10;
// Third test: Input = 1 (Expect state 10, out=0)
in = 1;
#10;
// Fourth test: Input = 0 (Expect state 11, out=1)
in = 0;
#10;
// Fifth test: Input = 0 (Expect state 00, out=0)
in = 0;
#10;
// Sixth test: Input = 1 (Expect state 01, out=0)
in = 1;
#10;
// Seventh test: Input = 0 (Expect state 00, out=0)
in = 0;
#10;
$stop;
end
initial begin

2
 $dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule
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Output:
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Time: 10 | rst = 1 | clk = 0 | in = 0 | out = 0
Time: 15 | rst = 1 | clk = 1 | in = 0 | out = 0
Time: 20 | rst = 1 | clk = 0 | in = 1 | out = 0
Time: 25 | rst = 1 | clk = 1 | in = 1 | out = 0
Time: 30 | rst = 1 | clk = 0 | in = 1 | out = 0
Time: 35 | rst = 1 | clk = 1 | in = 1 | out = 0
Time: 40 | rst = 1 | clk = 0 | in = 0 | out = 0
Time: 45 | rst = 1 | clk = 1 | in = 0 | out = 1
Time: 50 | rst = 1 | clk = 0 | in = 0 | out = 1
Time: 55 | rst = 1 | clk = 1 | in = 0 | out = 0
Time: 60 | rst = 1 | clk = 0 | in = 1 | out = 0
Time: 65 | rst = 1 | clk = 1 | in = 1 | out = 0
Time: 70 | rst = 1 | clk = 0 | in = 0 | out = 0
Time: 75 | rst = 1 | clk = 1 | in = 0 | out = 0

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Question :2
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Q2) You are an engineer working for NASA. They want you to design
a FSM that will test their newest rover Fido on the MIT campus.
NASA wirelessly transmits the travel plans to Fido, and then
Fido moves according to that information. “FIDO (Fast ID Online)
is a set of technology-agnostic security specifications for
strong authentication”.
To design your FSM, you first select the following locations
around the MIT campus and assign each location with a state in
3-bit binary representation:
Killian[000],
Kresge[001],
ZCenter[010],

3
Syd- Pac[011],
Student Center[100],
Building 34[101],
6.111 Lab[110],
Stata Center[111].
To simplify your test, you inform NASA to send Fido's FSM a
binary sequence for travel plans (e.g.’1-0-0- 0-1’ to cause Fido
to move five times). In other words, Fido receives either “0” or
(1) for each move and travels to the next destination as
specified below. Fido starts off at Killian Court for each test
run, and your FSM should output Fido’s current location.
Killian [000]: If 0, stay at Killian. If 1, go to Kresge.
Kresge [001]: If 0, go to Z-Center. If 1, go to the Student
Center.
Z-Center [010]: If 0, go to Syd-Pac. If 1, go to the Student
Center.
Syd-Pac [011]: If 0, stay at Syd-Pac. If 1, go to Killian.
Student Center [100]: If 0, go to Stata Center. If 1, go to
Building
Building 34 [101]: If 0, go to Syd-Pac. If 1, go to 6.111 Lab.
6.111 Lab [110]: If 0, go to Stata Center. If 1, stay at 6.111
Lab.
Stata Center [111]: If 0, go to Kresge. If 1, go to Building 34.

(a) Draw the state transition diagram for this FSM.

(b) If Fido is forever given a sequence of ones (i.e. 11111…),
where will it eventually end up?
(c) If Fido is forever given a sequence of 01s (i.e. 010101…),
which location(s) will it never visit?
(d) Design a module in Verilog for this FSM – the following
schematic shows the appropriate inputs and outputs.

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4
 Code
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module FidoFSM (
input clk,
input reset,
input move,
output reg [2:0] state
);
// State Encoding
parameter Killian = 3'b000,
Kresge = 3'b001,
ZCenter = 3'b010,
SydPac = 3'b011,
StudentCenter = 3'b100,
Building34 = 3'b101,
Lab6111 = 3'b110,
StataCenter = 3'b111;
always @(posedge clk or posedge reset) begin
if (reset)
state <= Killian; // Reset to Killian
else begin
case (state)
Killian: state <= move ? Kresge : Killian;
Kresge: state <= move ? StudentCenter : ZCenter;
ZCenter: state <= move ? StudentCenter : SydPac;
SydPac: state <= move ? Killian : SydPac;
StudentCenter: state <= move ? Building34 : StataCenter;
Building34: state <= move ? Lab6111 : SydPac;
Lab6111: state <= move ? Lab6111 : StataCenter;
StataCenter: state <= move ? Building34 : Kresge;
default: state <= Killian;
endcase
end
end
endmodule

Testbench:
`timescale 1ns/1ps
module FidoFSM_tb;

5
 reg clk;
reg reset;
reg move;
wire [2:0] state;
FidoFSM uut (
.clk(clk),
.reset(reset),
.move(move),
.state(state)
);
// Clock Generation
always #5 clk = ~clk;
initial begin
$monitor("Time=%0t | Reset=%b | Move=%b | State=%b", $time, reset, move, state);
clk = 0; reset = 1; move = 0; #10; // Reset Fido
reset = 0; #10;
// Move sequence: 1-1-1-1-1 to see if it loops at 6.111 Lab
move = 1; #10;
move = 1; #10;
move = 1; #10;
move = 1; #10;
move = 1; #10;
// Move sequence: 0-1-0-1-0-1 to test the loop condition
move = 0; #10;
move = 1; #10;
move = 0; #10;
move = 1; #10;
move = 0; #10;
move = 1; #10;
$finish;
end
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule
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6
 OUTPUT:
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Time=0 | Reset=1 | Move=0 | State=000
Time=10000 | Reset=0 | Move=0 | State=000
Time=20000 | Reset=0 | Move=1 | State=000
Time=25000 | Reset=0 | Move=1 | State=001
Time=35000 | Reset=0 | Move=1 | State=100
Time=45000 | Reset=0 | Move=1 | State=101
Time=55000 | Reset=0 | Move=1 | State=110
Time=70000 | Reset=0 | Move=0 | State=110
Time=75000 | Reset=0 | Move=0 | State=111
Time=80000 | Reset=0 | Move=1 | State=111
Time=85000 | Reset=0 | Move=1 | State=101
Time=90000 | Reset=0 | Move=0 | State=101
Time=95000 | Reset=0 | Move=0 | State=011
Time=100000 | Reset=0 | Move=1 | State=011
Time=105000 | Reset=0 | Move=1 | State=000
Time=110000 | Reset=0 | Move=0 | State=000
Time=120000 | Reset=0 | Move=1 | State=000
Time=125000 | Reset=0 | Move=1 | State=001

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