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Unit 2

HIERARCHICAL MEMORY TECHNOLOGY

❖ In computer architecture, the memory hierarchy separates computer
storage into a hierarchy based on response time.
❖ Memory hierarchy affects the performance in computer architectural
design, algorithm predictions and lower-level programming constructs
involving locality of reference.
❖ The total memory capacity of a computer can be visualized by
hierarchy of components.
❖ The Memory Hierarchy system consists of all storage devices contained
in a computer system from the slow auxiliary memory to fast main
memory and to smaller cache memory.
❖ The memory in a computer can be divided into five hierarchies based
on the speed as well as use.
❖ The five hierarchies in the memory are registers, cache, main memory,
magnetic disks and magnetic tapes.
❖ The first three hierarchies are volatile memories, which mean when
there is no power, and then automatically they lose their stored data,
whereas the last two hierarchies are not volatile which means they
store the data permanently.

Memory Hierarchy or Hierarchical Pyramid

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❖ The design of the memory hierarchy is divided into two types such as
primary (Internal) memory and secondary (External) memory.
Memory Hierarchy Design
The memory hierarchy in computers mainly include the following:
1)Registers:
• Usually, the register is a static RAM or SRAM in the processor of the
computer which is used for holding the data word which is typically 64
or 128 bits.
• The program counter register is the most important as well as found in
all the processor.
• Most of the processors use a status word register as well as an
accumulator.
• A status word register is used for decision making, and the accumulator
is used to store data like mathematical operation.
2)Cache Memory:
• Cache memory can also be found in the processor, however rarely it
maybe another IC (Integrated Circuit) which is separated into levels.
• The cache holds the chunk of data which are frequently used from main
memory.
• When the processor has a single core then it will have two or more
cache levels rarely. Present multi-core processors will be having three,
2-levels for each one core, and one level is shared.
3)Main Memory:
• The main memory in the computer is nothing but the memory unit in
the CPU that communicates directly. It is the main storage unit of the
computer.
• This memory is fast as well as large memory used for storing the data
throughout the operations of the computer. This memory is made up of
RAM as well as ROM.
• Multi-processing environment is created by main memory (RAM).
4)Magnetic Disks:
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• The magnetic disks in the computer are circular plates fabricated of

plastic otherwise metal by magnetized material.
• Frequently, two faces of the disks are utilized as well as many disks may
be stacked on one spindle by read or write heads obtainable on every
plane.
• All the disks in computer turn jointly at high speed.
• The tracks in the computer are nothing but bits which are stored within
the magnetized plane in spots next to concentric circles. These are
usually separated into sections which are named as sectors.
5)Magnetic Tapes:
• This tape is a normal magnetic recording which is designed with a
slender magnetizable covering on extended, plastic film of the thin
strip. This is mainly used to back up huge data.
• Whenever the computer requires to access a strip, first it will mount to
access the data. Once the data is allowed, then it will be unmounted.
• The access time of memory will be slower within magnetic strip as well
as it will take a few minutes for accessing a strip.

Characteristics of Memory Hierarchy

1)Performance:
▪ Previously, the designing of a computer system was done without
memory hierarchy and the speed gap among the main memory as well
as the CPU registers enhances because of the huge disparity in access
time, which will cause the lower performance.
▪ So, the enhancement was mandatory. The enhancement of this was
designed in the memory hierarchy model due to the system’s
performance increase.
▪ Performance will decrease when we shift from top to bottom.
2) Ability:
▪ The ability of the memory hierarchy is the total amount of data the
memory can store.
▪ Whenever we shift from top to bottom inside the memory hierarchy,
then the capacity will increase.
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3)Access Time:
▪ The access time in the memory hierarchy is the interval of the time
among the data availability as well as request to read or write.
▪ Because whenever we shift from top to bottom inside the memory
hierarchy, then the access time will increase.
4)Cost per bit:
▪ When we shift from top to bottom inside the memory hierarchy, then
the cost for each bit will increase, which means as internal memory is
expensive compared with external memory.

Advantages of Memory Hierarchy

1. Improved Performance: Hierarchical memory reduces the time it takes
to access data by storing frequently accessed data in faster memory.
2. Increased Capacity: Hierarchical memory allows for larger amounts of
data to be stored by using slower, higher-capacity memory for less
frequently accessed data.
3. Reduced Cost: Hierarchical memory reduces the cost of memory by using
slower, less expensive memory for less frequently accessed data.
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Challenges of Hierarchical Memory

1. Complexity: Hierarchical memory can be complex to manage, requiring
sophisticated algorithms and hardware to maintain coherence and optimize
performance.
2. Latency: Hierarchical memory can introduce latency, as data may need to
be retrieved from slower memory levels.
3. Power Consumption: Hierarchical memory can consume more power, as
multiple levels of memory require power to operate.

Inclusion, Coherence & Locality Properties

1)Inclusion Property:
▪ Ensures that data present in a smaller, faster cache level is also present
in larger, slower cache levels.
▪ Example: If data is in L1 cache, it should also be in L2 and main
memory.
▪ This property simplifies cache management by reducing redundancy
and tracking where data resides.

2)Coherence Property:
▪ Maintains consistency of data across multiple cache levels and
processors in a multi-core or distributed system.
▪ Ensures that changes made to a data item in one cache are propagated
to other caches holding the same data.
▪ Commonly managed through protocols like MESI (Modified, Exclusive,
Shared, Invalid) or MOESI (Modified, Owner, Exclusive, Shared, Invalid).

3)Locality Property:
Locality properties refer to the tendency of a processor to access data
repeatedly in the same memory locations over a short period of time. It is
actually a property of cache memory.
There are two types of locality properties:
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i)Temporal Locality:
▪ This property is related to time.
▪ The tendency of a program to access same memory location multiple
times within a short period of time.
▪ If a word is referenced now, then the same word will be referenced
again in future.
▪ LRU is used in temporal locality.

ii) Spatial Locality:

▪ This property is related to space.
▪ The tendency of a program to access data that is near in memory to
data that has been recently accessed.
▪ If a word is accessed now, then the word adjacent to it (close
proximity) will be accessed next.
▪ Keeping more words in block affects spatial locality (block size).

CACHE MEMORY ORGANIZATIONS

Most recently (frequently) used data is stored in cache.
Why Cache Memory is needed?
Data in primary memory can be accessed faster than secondary memory but
still, access times of primary memory are generally in a few microseconds,
whereas the CPU is capable of performing operations in nanoseconds. Due to
the time lag between accessing data and acting on data performance of the
system decreases as the CPU is not utilized properly, it may remain idle for
some time. In order to minimize this time gap new segment of memory is
Introduced known as Cache Memory.
Key Features of Cache Memory
1. Speed: Faster than the main memory (RAM), which helps the CPU
retrieve data more quickly.
2. Proximity: Located very close to the CPU, often on the CPU chip itself,
reducing data access time.
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3. Function: Temporarily holds data and instructions that the CPU is

likely to use again soon, minimizing the need to access the slower main
memory.

Role of Cache Memory

The role of cache memory is explained below,
• Cache memory plays a crucial role in computer systems.
• It provides faster access.
• It acts buffer between CPU and main memory (RAM).
• Primary role of it is to reduce average time taken to access data,
thereby improving overall system performance.

Benefits of Cache Memory

Various benefits of the cache memory are,
1. Faster access: Faster than main memory. It resides closer to CPU,
typically on same chip or in close proximity. Cache stores subset of data
and instruction.
2. Reducing memory latency: Memory access latency refers to time
taken for processes to retrieve data from memory. Caches are designed
to exploit principle of locality.
3. Lowering bus traffic: Accessing data from main memory involves
transferring it over system bus. Bus is shared resource and excessive
traffic can lead to congestion and slower data transfers. By utilizing
cache memory, processor can reduce frequency of accessing main
memory resulting in less bus traffic and improves system efficiency.
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4. Increasing effective CPU utilization: Cache memory allows CPU to

operate at a higher effective speed. CPU can spend more time executing
instruction rather than waiting for memory access. This leads to better
utilization of CPU’s processing capabilities and higher overall system
performance.
5. Enhancing system scalability: Cache memory helps improve system
scalability by reducing impact of memory latency on overall system
performance.

Working of Cache Memory

In order to understand the working of cache we must understand few
points:
• Cache memory is faster, they can be accessed very fast
• Cache memory is smaller, a large amount of data cannot be stored
Whenever CPU needs any data, it searches for corresponding data in the
cache (fast process) if data is found, it processes the data according to
instructions, however, if data is not found in the cache CPU search for that
data in primary memory (slower process) and loads it into the cache. This
ensures frequently accessed data are always found in the cache and hence
minimizes the time required to access the data.

How does Cache Memory Improve CPU Performance?

Cache memory improves CPU performance by reducing the time it takes for
the CPU to access data. By storing frequently accessed data closer to the CPU,
it minimizes the need for the CPU to fetch data from the slower main
memory.

What is a Cache Hit and a Cache Miss?

Cache Hit: When the CPU finds the required data in the cache memory,
allowing for quick access. On searching in the cache if data is found, a cache
hit has occurred.
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Hit Latency: Hit latency is the time it takes to access a memory location in a
cache.
Cache Miss: When the required data is not found in the cache, forcing the
CPU to retrieve it from the slower main memory. On searching in the cache if
data is not found, a cache miss has occurred.

CACHE MAPPING
Primary Terminologies
Some primary terminologies related to cache mapping are listed below:
• Main Memory Blocks: The main memory is divided into equal-sized
partitions called the main memory blocks.
• Cache Line: The cache is divided into equal partitions called the cache
lines.
• Block Size: The number of bytes or words in one block is called the
block size.
• Tag Bits: Tag bits are the identification bits that are used to identify
which block of main memory is present in the cache line.
• Number of Cache Lines: The number of cache lines is determined by
the ratio of cache size divided by the block or line size.
• Number of Cache Set: The number of cache sets is determined by the
ratio of several cache lines divided by the associativity of the cache.

Definition
Cache mapping is a technique that is used to bring the main memory content
to the cache or to identify the cache block in which the required content is
present. Actually needed block (words) of main memory is brought to the
cache lines & how (through address) CPU identifies(calls) that data from
cache.
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Important Points Related to Cache Mapping

Some important points related to cache mappings are listed below.
• The number of bytes in main memory block is equal to the number of
bytes in cache line i.e., the main memory block size is equal to the cache
line size.
• Number of blocks in cache = Cache Size / line or Block Size
• Number of sets in cache = Number of blocks in cache / Associativity
• The main memory address is divided into two parts i.e., main memory
block number and byte number.
There are three types of cache mappings
Direct Mapping

In this way, we can find which block(words) of main memory will be in

which cache line in direct mapping. In direct mapping, in which cache line
which block will come that is fixed.
CPU Reference
In direct mapping (in main memory) physical address is divided into two
parts i.e., Block number and Block (byte) offset. Block offset tells in that
particular block where the word is present (word index).
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Block Number Block Offset

In direct mapping (in cache) physical address is divided into three parts i.e.,
Tag bits, Cache Line Number and Byte offset. The bits in the cache line
number represents the cache line in which the content is present whereas
the bits in tag are the identification bits that represents which block of main
memory is present in cache. The bits in the byte offset decides in which byte
of the identified block the required content is present.

Tag Number of Cache Lines Byte Offset

Cache Line Number = Main Memory block Number % Number of Blocks in

Cache

Advantages
▪ Fast: Direct mapping is fast because it only requires checking the line
where the block is being searched for, rather than the entire cache.
▪ Simple: Direct mapping is simple to implement and check for cache hits
or misses.
Disadvantages
▪ Conflict misses: Direct mapping can lead to conflict misses, where a
cache block is replaced even if other blocks are empty.
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▪ Performance degradation: Direct mapping can degrade performance if

multiple blocks map to the same line.

Fully Associative Mapping

In fully associative mapping, in any cache line any block (words) can be put.
CPU Reference
In fully associative mapping (in main memory) physical address is divided
into two parts i.e., Block number and Block (byte) offset. Block offset tells in
that particular block where the word is present (word index).
Block Number Block Offset

In fully associative mapping (in cache) address is divided into two parts i.e.,
Tag bits and Byte offset. The tag bits identify that which memory block is
present and bits in the byte offset field decides in which byte of the block the
required content is present.

Tag Byte Offset

Advantages
▪ No Conflict Misses: Since a block can be placed anywhere in the cache,
there is no risk of a conflict miss occurring where multiple blocks map
to the same cache location.
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▪ High hit rate: Due to the ability to place any block anywhere, the cache
is more likely to find the requested data, leading to a higher hit rate.
Disadvantages
▪ Increased comparison time: To find a specific block, the cache needs to
compare the tag of the searched block with every single cache line,
which can significantly increase search time.
▪ High implementation complexity: Implementing a fully associative
cache requires more complex hardware design compared to other
mapping techniques.
▪ Larger circuit area: Due to the need for more extensive comparison
logic, a fully associative cache may require a larger circuit area
compared to other options.

Set Associative Mapping

Set Associative mapping is the combination of direct mapping and
associative mapping.
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That mean in this mapping, firstly the

formula of direct mapping (k mod n)is
used, where n will be set no. And then
the funda of fully associative mapping
will be applicable. That mean in any
line of that set, the block can be placed.

In set associative mapping (in main memory) physical address is divided

into two parts i.e., Block number and Block (byte) offset. Block offset tells in
that particular block where the word is present (word index).
Block Number Block Offset

In set associative mapping the cache blocks are divided in sets. It divides
address into three parts i.e., Tag bits, set number and byte offset. The bits in
set number decides that in which set of the cache the required block is
present and tag bits identify which block of the main memory is present. The
bits in the byte offset field gives us the byte of the block in which the content
is present.

Tag Set Number Byte Offset

Cache Set Number = Main Memory block number % Number of sets in

cache
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Advantages
▪ Higher hit rate: Set associative mapping can have a higher hit rate for
the same cache size.
▪ Fewer conflict misses: Set associative mapping can have fewer conflict
misses.
▪ Reduced comparison time: Set associative mapping can have a reduced
comparison time compared to fully associative mapping.
▪ More flexible than direct mapping: Set associative mapping is more
flexible than direct mapping, but less complex than fully associative
mapping.
Disadvantages
▪ Expensive: Set associative mapping can be expensive due to the cost of
associative-comparison hardware.
▪ Conflict misses: Set associative mapping can still have conflict misses.

CACHE MISSES
Cache miss occurs when data is not available in the Cache Memory. When
CPU detects a miss, it processes the miss by fetching requested data from
main memory.
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Various types of cache misses are:

1)Compulsory Miss: It is also known as cold start misses. These misses
occur when the first access to a block happens. Blocks must be brought into
the cache.
2)Capacity Miss: These misses occur when the program working set is
much larger than the cache capacity. Since cache can not contain all blocks
needed for program execution, so cache discards these blocks.
3)Conflict Miss: It is also known as collision misses or interference
misses. These misses occur when several blocks are mapped to the same set
or block frame. These misses occur in the set associative or direct mapped
block placement strategies. In Fully Associative mapping, there is no conflict
miss.

TECHNIQUES FOR REDUCING CACHE MISSES

➢ Increase cache size: Increase the size of the cache or the amount
of RAM to vertically scale the system.
➢ Use different cache policies: Try out different cache policies,
such as LRU (least recently used), LFU (least frequently used), MRU
(most recently used), FIFO (first in, first out), and LIFO (last in, first
out).
➢ Optimize code: Improve the locality of reference by optimizing the
program's code.
➢ Use prefetching: Use prefetching techniques to anticipate data
requests.
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➢ Use cache blocking: Divide data into smaller blocks to fit more
efficiently into the cache.
➢ Optimize data structures: Optimize data structures to improve
spatial and temporal locality.
➢ Use different cache levels: Use different cache levels or
partitions to reduce cache contention.
➢ Adjust replacement policy: Adjust the cache replacement
policy to suit your workload.

VIRTUAL MEMORY ORGANISATION

Virtual memory is a memory management technique used by operating
systems to give the appearance of a large, continuous block of memory to
applications, even if the physical memory (RAM) is limited. It allows larger
applications to run on systems with less RAM.
• The main objective of virtual memory is to support multiprogramming.
That mean more and more number of processes can come in the main
memory.
• Programs can be larger than the available physical memory. Virtual
Memory provides an abstraction of main memory, eliminating concerns
about storage limitations.
OR
It provides the illusion to the programmer that a processor whose size
is larger than the main memory can also be executed.
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A virtual memory is what its name indicates- it is an illusion of a memory

that is larger than the real memory. The basis of virtual memory is the non-
contiguous memory allocation model. The virtual memory manager removes
some components from memory to make room for other components.

How Virtual Memory Works?

Virtual Memory is a technique that is implemented using both hardware and
software. It maps memory addresses used by a program, called virtual
addresses, into physical addresses in computer memory.
• All memory references within a process are logical addresses that are
dynamically translated into physical addresses at run time. This means
that a process can be swapped in and out of the main memory such that
it occupies different places in the main memory at different times
during the course of execution.
• A process may be broken into a number of pieces (pages) and these
pieces need not to be continuously located in the main memory during
execution. The combination of dynamic run-time address translation
and the use of a page or segment table permits this.
If these characteristics are present then, it is not necessary that all the pages
or segments are present in the main memory during execution. This means
that the required pages need to be loaded into memory whenever required.
Virtual memory is implemented using Demand Paging or Demand
Segmentation.
Types of Virtual Memory
In a computer, virtual memory is managed by the Memory Management Unit
(MMU), which is often built into the CPU. The CPU generates virtual
addresses that the MMU translates into physical addresses.
There are two main types of virtual memory:

• Paging
• Segmentation
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Paging
Paging divides memory into small fixed-size blocks called pages. When the
computer runs out of RAM, pages that aren’t currently in use are moved to
the hard drive, into an area called a swap file. The swap file acts as an
extension of RAM. When a page is needed again, it is swapped back into
RAM, a process known as page swapping. This ensures that the operating
system (OS) and applications have enough memory to run.
Demand Paging: The process of loading the page into memory on demand
(whenever a page fault occurs) is known as demand paging. The process
includes the following steps are as follows:

• If the CPU tries to refer to a page that is currently not available in the
main memory, it generates an interrupt indicating a memory access
fault.
• The OS puts the interrupted process in a blocking state. The OS
generates trap.
• The OS will search for the required page in the logical address space
(LAS).
• The required page will be brought from logical address space to
physical address space. The page replacement algorithms are used for
the decision-making of replacing the page in physical address space.
• The page table will be updated accordingly.
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• The signal will be sent to the CPU to continue the program execution
and it will place the process back into the ready state.
Hence whenever a page fault occurs these steps are followed by the
operating system and the required page is brought into memory.
Page Fault Service Time: The time taken to service the page fault is called
page fault service time. The page fault service time includes the time taken
to perform all the above six steps.
Let, Main memory access time is: m (in nanoseconds)
Page fault service time is: s (in milliseconds)
Page fault rate is: p
Then, Effective memory access time = (p*s) + (1-p) *m
Segmentation
Segmentation divides virtual memory into segments of different sizes.
Segments that aren’t currently needed can be moved to the hard drive. The
system uses a segment table to keep track of each segment’s status,
including whether it’s in memory, if it’s been modified, and its physical
address. Segments are mapped into a process’s address space only when
needed.
Virtual Memory vs Physical Memory

Feature Virtual Memory Physical Memory (RAM)

An abstraction that
The actual hardware (RAM) that
extends the available
Definition stores data and instructions
memory by using disk
currently being used by the CPU
storage

Location On the hard drive or SSD On the computer’s motherboard

Slower (due to disk I/O Faster (accessed directly by the

Speed
operations) CPU)
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Feature Virtual Memory Physical Memory (RAM)

Larger, limited by disk Smaller, limited by the amount

Capacity
space of RAM installed

Lower (cost of additional

Cost Higher (cost of RAM modules)
disk storage)

Data Indirect (via paging and Direct (CPU can access data
Access swapping) directly)

Non-volatile (data Volatile (data is lost when

Volatility
persists on disk) power is off)

What is Swapping?
Swapping is a process out means removing all of its pages from memory, or
marking them so that they will be removed by the normal page replacement
process. Suspending a process ensures that it is not runnable while it is
swapped out. At some later time, the system swaps back the process from
the secondary storage to the main memory. When a process is
busy swapping pages in and out then this situation is called thrashing.
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What is Thrashing?
At any given time, only a few pages of any process are in the main memory,
and therefore more processes can be maintained in memory. Furthermore,
time is saved because unused pages are not swapped in and out of memory.
In the steady state practically, all of the main memory will be occupied with
process pages, so that the processor and OS have direct access to as many
processes as possible. Thus, when the OS brings one page in, it must throw
another out. If it throws out a page just before it is used, then it will just have
to get that page again almost immediately. Too much of this leads to a
condition called Thrashing. The system spends most of its time swapping
pages rather than executing instructions.

In the given diagram, the initial degree of multiprogramming up to some

extent of point(lambda), the CPU utilization is very high and the system
resources are utilized 100%. But if we further increase the degree of
multiprogramming the CPU utilization will drastically fall down and the
system will spend more time only on the page replacement and the time
taken to complete the execution of the process will increase. This situation in
the system is called thrashing.
Benefits of Using Virtual Memory:
• Many processes maintained in the main memory.
• A process larger than the main memory can be executed because of
demand paging. The OS itself loads pages of a process in the main
memory as required.
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• It allows greater multiprogramming levels by using less of the available

(primary) memory for each process.
• It has twice the capacity for addresses as main memory.
• It makes it possible to run more applications at once.
• Users are spared from having to add memory modules when RAM
space runs out, and applications are liberated from shared memory
management.
• When only a portion of a program is required for execution, speed has
increased.
• Memory isolation has increased security.
• It makes it possible for several larger applications to run at once.
• Memory allocation is comparatively cheap.
• It doesn’t require outside fragmentation.
• It is efficient to manage logical partition workloads using the CPU.
• Automatic data movement is possible.
Limitation of Virtual Memory
• It can slow down the system performance, as data needs to be
constantly transferred between the physical memory and the hard disk.
• It can increase the risk of data loss or corruption, as data can be lost if
the hard disk fails or if there is a power outage while data is being
transferred to or from the hard disk.
• It can increase the complexity of the memory management system, as
the operating system needs to manage both physical and virtual
memory.

MAPPING AND MANAGEMENT TECHNIQUES

Mapping techniques are actually same as cache mapping. So lets focus
on management techniques.
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Memory Management Techniques

▪ Operating system use multiple memory management techniques to
manage the primary memory that is RAM.
▪ Degree of multi-programming says to keep more and more number of
processes in main memory so that whenever CPU needs for a process
to execute, there will be plenty number of processes in RAM.
▪ Memory is a large array of bytes and every byte is having some address.
Now memory is divided.
▪ The motive is to keep more and more processes in RAM i.e., to keep
greater number of processes in ready state.

Contiguous Memory Allocation

Contiguous memory allocation is a memory allocation technique where
a process is allocated in a contiguous block of memory. The memory block
is allocated from a larger free memory block, and the process is allocated
the entire block.
Types of Contiguous Memory Allocation
1)Fixed Partitioning: In fixed partitioning, the memory is divided into a
fixed number of partitions of equal or unequal size. Each partition is
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allocated to a process, and the process is restricted to the allocated

partition.
2)Variable Partitioning: In variable partitioning, the memory is divided
into partitions of varying sizes. Each partition is allocated to a process,
and the process can request a specific amount of memory.

Advantages of Contiguous Memory Allocation

1. Efficient Use of Memory: Contiguous memory allocation makes efficient
use of memory, as the entire block is allocated to a single process.
2. Fast Allocation and Deallocation: Contiguous memory allocation allows
for fast allocation and deallocation of memory, as the memory block is
allocated and deallocated as a single unit.
3. Simplified Memory Management: Contiguous memory allocation
simplifies memory management, as the memory block is managed as a
single unit.
Disadvantages of Contiguous Memory Allocation
1. External Fragmentation: Contiguous memory allocation can lead to
external fragmentation, where free memory blocks are broken into
smaller fragments, making it difficult to allocate large blocks of memory.
2. Internal Fragmentation: Contiguous memory allocation can also lead to
internal fragmentation, where a process is allocated more memory than it
needs, resulting in wasted memory.
3. Limited Flexibility: Contiguous memory allocation has limited
flexibility, as it is difficult to allocate memory to multiple processes from a
single free memory block.

Non-Contiguous Memory Allocation

Non-contiguous memory allocation is a memory management
technique that allocates a process's parts to different locations in the main
memory. In which place a process will be stored that is not fixed. This
technique is used in operating systems.
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How it works:
1)A process can request multiple memory blocks from different locations
in the memory.
2)The available free memory space is scattered across the memory.
3)This technique reduces memory wastage caused by internal and
external fragmentation.
Types of Contiguous Memory Allocation
1)Paging: Divides memory into fixed-sized blocks called "pages" and
allocates memory to processes by assigning them different combinations
of these pages, allowing for non-contiguous allocation.
2)Segmentation: Splits memory into variable-sized logical units called
"segments" where each segment can represent a different part of a
program (like code, data, stack).
3)Multilevel paging: A hierarchical approach to paging where the page
table is organized into multiple levels, reducing the memory required to
store the table itself.
4)Inverted paging: Instead of each process having its own page table, a
single page table is maintained for the entire system, where entries point
to the processes that are using that page.
5)Segmented Paging: Segmented paging essentially refers to a
combination of segmentation and paging, where memory is divided into
segments which are further divided into pages.

Advantages of Non-Contiguous Memory Allocation:

1. Reduced External Fragmentation: Non-contiguous memory allocation
reduces external fragmentation, as memory blocks can be allocated from
anywhere in memory.
2. Reduced Internal Fragmentation: Non-contiguous memory allocation
reduces internal fragmentation, as each process is allocated the exact
amount of memory it needs.
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3. Improved Memory Utilization: Non-contiguous memory allocation

improves memory utilization, as memory is allocated according to the
needs of the process.
Disadvantages of Non-Contiguous Memory Allocation:
1. Increased Complexity: Non-contiguous memory allocation is more
complex to implement, as the operating system needs to manage non-
contiguous memory blocks.
2. Increased Overhead: Non-contiguous memory allocation increases
overhead, as the operating system needs to search for free memory
blocks.
3. Page Faults: Non-contiguous memory allocation can lead to page faults,
which occur when a process accesses a page that is not in memory.

MEMORY REPLACEMENT POLICIES

Memory replacement is actually cache replacement. Cache replacement
policies are algorithms that determine which data to remove from a cache
when it's full. It is used to decide which cache line to replace when a new
cache line needs to be allocated and the cache is full.
Importance of cache replacement policies
i)They increases hit rate and reduces page fault.
ii)They're important for efficient memory hierarchy design.

FIFO
FIFO in memory replacement policy stands for "First In, First Out,"
meaning that when a page needs to be replaced in memory, the system will
always choose the page that has been in memory the longest (the oldest
page), essentially treating the memory like a queue where the first item
added is the first to be removed; this is considered a simple and
straightforward page replacement algorithm.
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Working: When a new page needs to be loaded into memory and there is no
space, the page that has been in memory the longest (the one at the front of
the queue) is removed to make room for the new page.
Advantages of FIFO:
Easy to implement: Due to its simple queue-based structure, FIFO is
relatively easy to implement in software.
Disadvantages of FIFO:
i)Can be inefficient: In many scenarios, FIFO might not be the optimal choice
as it doesn't consider how recently a page was accessed, leading to
potentially replacing frequently used pages.
ii)Belady's Anomaly: In some cases, increasing the number of available
memory frames can paradoxically lead to more page faults with FIFO.
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MRU
MRU stands for "Most Recently Used" and refers to a memory replacement
policy where the item that was accessed most recently is the one chosen to
be removed from the cache when space is needed for a new item; essentially,
the opposite of the "Least Recently Used" (LRU) policy.
Functionality: When a cache becomes full and needs to make space for a
new item, the MRU policy identifies the data that was accessed most recently
and removes it from the cache.
Assumption: The MRU policy assumes that items recently accessed are
more likely to be accessed again soon, making it a suitable strategy when
there is strong temporal locality in data access patterns.
When might MRU be useful?
Short-term access patterns: When data is accessed frequently within a short
time frame, MRU can be effective as the most recent access is likely to be the
next access as well.
Limitations of MRU: Not suitable for all scenarios; If access patterns exhibit
poor temporal locality, where recently accessed items are unlikely to be
accessed again soon, MRU may not perform well.
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LRU
LRU" in memory management stands for "Least Recently Used," which is a
cache replacement policy in computer science where the block that has been
least recently accessed is replaced when the cache is full. This policy is based
on the principle of temporal locality, aiming to optimize cache performance
by keeping frequently used data in the cache.

Working:
1)LRU maintains a list of items in the cache, with the most recently used
items at the front.
2)When the cache is full, LRU removes the least recently used item to make
room for a new item.
3)The new item is added to the front of the list.
Advantages:
▪ Improved performance: LRU keeps frequently used data in fast
memory, which improves system performance
▪ Optimized memory usage: LRU keeps frequently used data in memory
and discards less frequently used data, which helps optimize memory
usage
▪ Simple implementation: LRU is easy to understand and implement, and
doesn't require complex data structures or algorithms
▪ Predictable eviction decisions: LRU focuses on recency of access,
making eviction decisions consistent
▪ Works well in many applications: LRU is used in many systems,
including web browsers and databases
Disadvantages
▪ It requires additional Data Structure to be implemented.
▪ Hardware assistance is high.
▪ In LRU error detection is difficult as compared to other algorithms.
▪ It has limited acceptability.
▪ LRU are very costly to operate.
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Optimal
The "optimal memory replacement policy," also called the "Optimal Page
Replacement Algorithm" or "MIN algorithm," is a theoretical strategy in
memory management that aims to replace the page which will not be
accessed for the longest time in the future, essentially selecting the page
with the furthest next use based on perfect knowledge of future memory
access patterns; however, this policy is not practical because it requires
knowing the future access sequence, making it a benchmark for evaluating
other replacement algorithms.
Functionality:
When a page needs to be replaced, the optimal policy selects the page that
will be accessed the furthest into the future, minimizing page faults.
Theoretical nature:
This policy is considered theoretical because it requires knowledge of future
memory access which is not possible in real-time operating systems.
Advantages:
▪ Minimizes page faults: Due to its ability to identify the page that will be
accessed furthest in the future, the optimal policy generates the least
number of page faults, leading to optimal performance in theory.
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▪ Simple concept: The algorithm itself is conceptually simple to

understand, as it only requires identifying the page with the longest
future unused period.
Disadvantages:
▪ Not practical: Since it requires knowledge of future memory access
patterns, which is impossible to obtain in real-time, the optimal policy
cannot be implemented in practice.
▪ Implementation complexity: Although the concept is simple,
implementing an algorithm that accurately predicts future memory
access would be highly complex and resource-intensive.