Silicon (2022) 14:3185–3197

https://doi.org/10.1007/s12633-021-01148-7

REVIEW PAPER

A Detailed Roadmap from Single Gate to Heterojunction TFET

for Next Generation Devices
J. E. Jeyanthi 1 & T. S. Arun Samuel 1 & A. Sharon Geege 1 & P. Vimala 2

Received: 18 January 2021 / Accepted: 5 May 2021 / Published online: 15 May 2021
# Springer Nature B.V. 2021

Abstract
Through the age of nanoelectronics, device dimensions are curbed, and the size of transistors is rapidly reduced. Scaling down
transistors results in high-speed switching, higher density, reduced power consumption, lower transistor costs. Some of the critical
issues facing scaling down transistor sizes such as punch-through effect, drain-induced barrier lowering (DIBL), gate leakage current,
threshold voltage roll-off, leakage current effects various proposed structure. The evolution of the semiconductor industry from the
appropriate methods CMOS into a proposed structure called TFET. The TFET is a suitable method as a critical part of the power usage
in circuit boards that achieves its target to meet reverse sub-threshold slope (SS) below the temperature limit (60 mV/dec in room
temperature) with often a lower drive current implicitly than a MOSFET. In this study, an effort has been made to bring the roadmap of
various TFET structures like Single gated TFET, Double gated TFET, Tri gated TFET, and, finally, Heterojunction TFET.

Keywords Scaling . Scaling challenges . CMOS . TFET . HTFET . Band to band tunneling (BTBT) . ON current . OFF current .
Subthreshold swing (SS)

1 Introduction on system efficiency by reducing its effectiveness in low-

power applications and RF applications [2]. However, the
Every microprocessor is built entirely on MOS transistors. process of scaling the MOSFETs and maintaining the predic-
MOSFET design has influenced the microelectronics sector tion of Moore’s law has risen to certain limits called short
in recent decades due to its key merits - dissipation of low channel results [3, 4]. Additionally, the power management
power, extreme noise tolerance, high packaging capacity, a has become an essential concern for further scaling technolo-
wide variety of supplies voltages, and simple to measure mea- gy, causing immense short-channel effects (SCE). Some of
surements of the unit for better efficiency [1]. The semicon- the SCE, such as DIBL, increases IOFF, threshold voltage
ductor industry focuses on reducing the device, achieving ex- roll-off, degrades the ION/IOFF switching ratio, and gate leak-
cellent size, die area reduction, and functionality. On the other age current (Ig) [1–4]. Therefore, the need emerges from
hand, intense scaling above the threshold has adverse effects experiencing alternative technology that can overcome the
limitations of CMOS technology and is seen as a future pos-
sibility and successor to conventional MOSFET [5].
* J. E. Jeyanthi
[email protected]
TFET was proposed as a higher performance option to
MOSFET, benefiting from quantum tunneling. Due to its
T. S. Arun Samuel Band-to-band (BTBT) current conduction principle, TFET is
[email protected] one of the predicted devices that show SS under 60 mV/de-
A. Sharon Geege cade. TFET’s significant characteristics are used to reduce the
[email protected] SCEs and low OFF-state current (IOFF), which allows the de-
P. Vimala
vice to use as an energy-efficient transition in low power ap-
[email protected] plications [1–5]. Nevertheless, TFET’s drain current remains a
burden, though providing a high ION/IOFF ratio in favor of a
1
Department of ECE, National Engineering College, Kovilpatti, India technology to replace conventional MOSFETs. Specific struc-
2
Department of ECE, Dayananda Sagar College of Engineering, tural and material engineering systems have been accom-
Bangalore, India plished [6–8] to achieve a simultaneous increase of ON
3186 Silicon (2022) 14:3185–3197

current, lower leakage current, and steeper SS. However, research value than vertical TFETs because of their compatibility
when the same material is used in the source, channel, and with the manufacturing processes. [13, 14]. The conventional
drain areas, the drain current is lower in TFET than in flow of the CMOS process of manufacturing may be used to
MOSFET. Because the tunneling of electrons from source to fabricate the TFET device. Wang et al. [15] were first developed
channel depends on the energy gap between the source va- on the silicon suspension with a complementary N-type and P-
lance band and the channel conduction band. Hence the ener- type TFET. Figure 1 showing the schematic diagram of N TFET
gy gap is significant for the homojunction TFET devices. and P-type TFETs; it works in reverse biased condition, offering
Consequently, different materials (heterojunction) used to a large tunneling barrier width and thermal emissions of this
source and a channel region of TFET would reduce the energy barrier width, allowing for a much lower leakage current than
gap between the source and the channel region. Double gate MOSFET. Lee & Choi [16] proposed a model for Single Gate
Heterojunction TFET (H-TFET) showed significant improve- Silicon on Insulator TFET, which provides the ION current of
ment over the Heterojunction TFET [6–9]. H-TFET structures 10−9A and IOFF current of 10−17A when the channel length is
like Si/GaAs HTFET, III-V/Si H-V-TFET, III-V/InGaAs H- used as 20 nm. While increasing the channel length to 100 nm,
TFET structures like Heterojunction Surrounding Gate (HSG) the ON current remains the same, and the OFF current is nearly
TFET, DG-HTFET, DG-HTFET-GD(Gaussian Doping), 10−18A. However, while reducing the channel length, there is a
InGaAs/GaAsSb -H-GAA-TFET, H-SOI-TFET [2–12], need to improve the ION current of the single gate TFET, which is
SiGe based HTFET [34, 35], InGaAs based HTFET [36, 37, the design challenge of TFET. Figure 2 shows the drain current
42], III-V HTFET [38, 40, 55], p-type HTFETs [39, 56], characteristics of single gate TFET. It is inferred from the figure
Graphene Nanoribbon HTFET[41], examined to obtain im- that the single gate TFET [13] structure provides a better ON
proved efficiency. current than the single gate device configuration.
This review paper focuses on the performance analysis of
Single Gated TFET, Double Gated TFET, Gate Material
Engineering TFET, Gate Oxide Engineering TFET, Tri-Gate
TFET, and Heterojunction TFET. It also provides a roadmap 3 DG TFET and its Challenges
of different gate engineering and channel engineering to re-
duce the current leakage and increase ION performance. The For VLSI circuits, the speed of operation depends on the ION
remaining part is categorized on the following. Section 2 fo- current, and a low leakage current is more crucial for power
cuses on Single Gate TFET review & its challenges; section 3 saving. Unfortunately, in TFET, the ON current needs to be
focuses on the review of Double Gate TFET and gate engi- improved by each new transistor generation, but it would lead
neering characteristics; section 4 deals with Tri-Gate TFET to a lower leakage current, increasing energy consumption.
and its characteristics, and section 5 give the need for hetero Hence, to increase the drive current of TFET, a multiple-
materials used in TFETs. gate TFET structure was introduced [17–25; 44–49, 53].

SSS DG TFET A single-k spacer (SSS) Double Gate N-TFET

(DG TFET) was presented by Mallikarjunarao et al. [17] to im-
2 Single Gate TFET and its Challenges prove the device’s performance using different spacer materials.
A SSS material and Silicon dioxide (SiO2), dielectric ma-
A variety of research works for the study of Single Gate TFET terial, were placed over 2 nm underlap length region and
efficiency have been published. Lateral TFETs have more 0.9 nm channel thickness. The work function of gate metal

Fig. 1 Planar NTFET and PTFET

structures
Silicon (2022) 14:3185–3197 3187

Fig. 2 Drain current

characteristics of single gate
TFET

is 4.1 eV. Figure 3 shows the simulated structure of SSS of the advantages of a low-subthreshold TFET and a high
DGTFET. The oxide thickness (tox) of 0.9 nm, gate length current JLFET. ADG-TFET has a high ION/IOFF and a low
(Lg) of 20 nm, silicon body thickness (tSi) of 10 nm, source SS. The asymmetric dual-gate tunneling FET (ADG-TFET)
underlap length(Luns) of 2 nm, drain underlap length(Lund) of cross-sectional view is depicted in Fig.4. The parameters used
2 nm, source spacer length(L ss) of 2 nm, drain spacer in their simulation are: Top-Gate length LTG, Bottom-Gate
length(Lsd) of 2 nm are the device specifications. The SSS work function ФBG, Top Gate work function ФT are 20 nm,
DGTFET has been developed to evaluate its performance 4.80 eV, and 4.32 eV, respectively.
measures with various spacer materials by considering the The proposed structure has investigated and achieved a
optimized underlap region. It shows better performance for significantly higher ION /I OFF ratio of 3.3 × 1010, I ON =
HfO2 spacer material because of its appropriate SCE control. 302 μA/μm using Silvaco TCAD.

ADG-TFET Ying Wang et al. [18] presented asymmetric dual- DM-DG TFET Dual-Material Double- Gate TFETs with SiO2/
gate tunneling FET (ADG-TFET), in conjunction with the HfO2 stacked gate-oxide structure developed by Sanjay
tunnel intersection, the JLFET barrier-controlled system.
ADG-TFET has demonstrated enormous potential because

Fig. 4 Asymmetric dual-gate tunneling FET (ADG-TFET) cross-

Fig. 3 Simulated structure of SSS DGTFET sectional view
3188 Silicon (2022) 14:3185–3197

Kumar et al. [19]. It indicates that the characteristics of SS and

ION over SMG-TFET models have improved. DM DG TFETs
with a SiO2/HfO2 stacked gate oxide structure investigated
and L, L1, L2, L3, L4 are lengths of the channel, source deple-
tion, tunneling gate, auxiliary gate, drain depletion & tox, tk, tsi
are the thickness of SiO2, high-k dielectric, and channel film
respectively. This system comprises M1 (tunneling gate) and
M2 (auxiliary gate) as two latterly attached gate electrodes.
Figure 5 depicts the schematic representation of DM-DG-
TFET.
The device parameters are doping concentrations of source,
channel, drain - 1020 cm−3, 1016 cm−3, and 5X1018cm−3 ac-
cordingly channel length (L) - 50 nm, tunneling gate length
(L2) - 20 nm, auxiliary gate length (L3) - 30 nm, channel Fig. 6 FDGe-DG-TFET cross-sectional view
thickness (tSi) and oxide thickness (tox) - 12 nm and 1 nm
respectively. The structure has been analyzed with the help concentration ND, and drain region length, LD, was also
of TCAD simulation. examined.
With improved Φm and ND, IOFF decreased approximately
FDGe-DG-TFET A fully-depleted (FD) Ge Double-Gate (DG) the magnitude of two orders to 2.5 ambient 10−13/A μm with
Tunneling Field-Effect Transistors (TFET) structure has in- LD arising in the range of 40 nm - 100 nm, and the ION/IOFF as
vestigated by Xiangyu Liu et al. [20]. Figure 5 depicts the 1.58 × 107.
FDGe-DG-TFET cross-section. The channel width and EOT
of HfO2 were set to 0.9 nm. The source doping concentration GME-SP-Dg-TFET Jaya Madan et al. [21] investigated various
and channel doping concentration, and ND, Φm were chosen DG-TFET structures and stated that the electrical parameters
as 5 × 1019 cm−3, 1 × 1018 cm−3, 4.4 eV. All the simulations of GME-SP-DG-TFET for low power implementations. The
have been analyzed by the Sentaurus TCAD device simulator. system has two different metalwork features, predominantly
The ND is 1 × 1018 cm−3, and the channel has degraded in the involving a low work feature at source (tunneling gate) and a
off-state by Φm. The findings showed that the on-state current high work feature at the drain (auxiliary gate). The doping
ION and ION/IOFF rose from about one order of magnitude concentration and pocket width of the source are 2 × 1019
concerning the Standard Ge-DG-TFET ION = 3.95 / A μm & cm−3 and 4 nm. Besides, the parameter values such as gate
below 60 mV/decade subthreshold drop SS = 26.4 mV/de- function for tunneling and the auxiliary gate are respectively
cade. Figure 6 depicts the FD Ge-DG-TFET cross-sectional 4.1 eV and 4.3 eV. Besides, source (p+) and drain doping (n+)
view. The impact of work function Φm, channel doping have been kept 1 × 1020 cm−3 and 5 × 1018 cm−3, respectively.
TCAD Silvaco Atlas device is the simulator.
Figure 7.illustrates the 2D representation of GME-SP-DG-
TFET. The ION/IOFF ratio increases from an order of 1010–
1012.

Fig. 5 The schematic representation of DM-DG-TFET Fig. 7 2D representation of GME-SP-DGTFET

Silicon (2022) 14:3185–3197 3189

Fig. 9 Drain current characteristics of double gate TFET

Devices. Figure 9 shows the drain current characteristics of

Fig. 8 Si-based DM-DG-TFET cross-sectional view double gate TFET. It is inferred from the figure that the double
gate TFET [17] structure provides a better ON current than the
Si-DM-DG-TFET Reza Meshkin [22] has introduced a simple double gate device configuration.
methodology using computational simulations to refine a
dual-material double-gate TFET’s working function. Si-
based Dual-Material Double-Gate TFET (DM-DG-TFET) 4 Tri Gate TFET and its Challenges
cross-sectional view depicted in Fig.8. The gate consists of
dual materials - φt and φa. DM-DG-TFET efficient optimiza- Triple Material Tri-Gate JL-TFET The Tri-Gate-TFET structure
tion factors used. The channel area has divided into two areas was implemented to raise the drive current of TFETs even
that correspond to the gate’s materials and the channel length, while lowering the leakage current. [26–28] [46, 50–52, 54]
i.e., 50 nm of the sum of the length. It should mention that developed a triple material tri-gate junctionless transistor,
these two regions have an average length ratio of 2:3 (L2: L3). which acts as a TFET. The author designed a device with an
R1 and R4 are respectively the depletion side of the source HfO2 and to enhance gate control, and a low-k air spacer was
and drain extension. Source, drain and channel are high (p- used. Parameters used - Gate length is 50 nm, Channel length
type), moderate and light (n-type) doped areas of 1020 cm−3, (Lch) is 152 nm, Channel thickness (Tch) is 20 nm, Oxide
5X1018cm−3 and 1016 cm−3 respectively. The simulations thickness (Tox) is 3 nm, Spacer gap is 1 nm, Channel/
have done through the 2D Silvaco ATLAS simulator. Source/Drain doping concentration is 1020 cm−3, Work fea-
The author suggested that the optimum method for decid- ture of copper, silver, aluminum is 4.5 eV, 4.26 eV, and
ing the importance of the tunneling gate working function 4.2 eV. Space split into three gates to ensure proper isolation.
depends on the increase of the electrical field’s lateral section Figure 10 depicts the triple material tri-gate JL-TFET sche-
along the source/channel crossing and the same section along matic structure. The results have investigated using the
the channel/drain junction. With these general conditions, the Silvaco TCAD simulator. A meager OFF current of 10−4 A
optimum value is established to suit the valence band and is displayed, while the device’s drain current increases sharply
conductive band in off-state mode. Table 1 shows the different after the threshold voltage crossing suggest a superior ON-
electrical parameters comparison of Double Gate-TFET OFF current ratio (~1010).

Table 1 Different electrical parameters comparison of Double Gate-TFET Devices

References Device architecture ION IOFF ION / IOFF Channel length Vth SS

[17] SSS-DG-TFET 1.35 μA 0.021fA 6.4×1010 0.10 μm 0.5 V 30 mV/dec

[18] A-DG-TFET 302 μA/ μm 1×10−18 μA/ μm 3.3×1010 40 nm – 35 mV/dec
[19] DM-DG-TFET 1×10−4 A/μm 1×10−14 A/μm 1×1010 90 nm – 29 mV/dec
[20] FD-Ge DG-TFET 3.9×10−5 A/μm 2.5×10−13 A/μm 1.58×107 50 nm 0.7 V 26.4 mV/dec
[21] GME-SP-DG-TFET 1×10−5 A/μm 1×10−17 A/μm 1×1012 90 nm 0.62 V 27.96 mV/dec
3190 Silicon (2022) 14:3185–3197

Figure 12 depicts DMTG SON TFET with SiO2/HfO2

stacked gate oxide schematic view. Nd, Na, Nch, M of 1024/
m3, 6 × 1026/m3, 1023/m3, and 4.3 eV, respectively. In this
work, the proposed structure has investigated using a 3D
ATLAS device simulator. Table 2 shows the different electri-
cal parameters comparison of tri-gate TFET Devices.
Figure 13 shows the drain current characteristics of the tri-
gate TFET. It is inferred from the figure that tri gate TFET
[27] structure provides the better ON than the tri-gate device
configuration.

5 Heterojunction TFET and its Roadmap

Fig. 10 Triple material tri-gate JL-TFET schematic structure Hetero-Structure Vertical TFET Vanlalawmpuia et al. [29] pro-
posed the Vertical Tunnel FET hetero-structure, with all geo-
GC-DMTG SON-TFET Has designed with a front gate stack metric dimensions designed for the highest SS and maximum
(HfO2/SiO2) by Dinesh Kumar Dash et al. [27] current ratio. Hafnium dioxide (HfO2) content with a permit-
Figure 11 shows the GC-DMTG SON-TFET schematic tivity of 22 gate oxide. A metal gate work function, ΦM =
representation. The work function comprises M1 and M2 with 4.72 eV, employed for an optimized SS. The VDS value set as
the channel length, L = L1 + L2, Nch1, and Nch2 as doping 0.5 V. The drain current at Vgs = 1.2 V while off current taken
concentrations. Thickness is teff, tair, and tSi - stacked front gate as Vgs = 0 V. The doping concentrations were: source (1 ×
oxide (HfO2/SiO2), air, and channel. The parameters and its 10 20 cm −3 ), channel (1 × 10 16 cm −3 ), and drain (5 ×
values used for calculation and simulation such as tSi, t1, t2, 1018 cm−3) to lessen the device’s ambipolarity. The geometric
L1,L2,L,W of 10 nm,1 nm, 2 nm, 15 nm,25 nm,40 nm,5 nm dimensions are tGe = 12 nm while tSi = 3 nm. The LG = 30 nm,
respectively and the values of Nch1, Nch2, Na, Nd, φM1, φM2 as LS = 26 nm, channel undercut length of LUC = 4 nm, tox =
1011 cm−3,1013 cm−3, 1020 cm−3, 5X1012cm−3, 4.0 eV, 4.4 eV 2 nm and tBox = 10 nm. Figure 14. illustrates Hetero-structure
respectively. The results have investigated using the Silvaco vertical TFET Schematic representation. As the structure pro-
Atlas TCAD simulator. posed was based on a vertical BTBT, which improved the
electrical field, causing a higher rate of electron tunneling
DMTG Son TFET Priyanka Saha et al. [28] presented a dual when the source thickness (tGe) declined.
material tri-gate (DMTG) Silicon On Nothing (SON) TFET The drain current rises, whereas the off-state leakage cur-
with SiO2/HfO2 stacked gate oxide. Here, L nm as x-axis, tsi as rent for differences in source thickness remains stable. tSi re-
the z-axis. W is channel width along the y-axis. The device duction increases the current ratio and removes short channel
parameters and values used for calculation and simulation, effects due to improved electrostatic gate control. The geomet-
such as t1, t2, tb, tsi of 1 nm, 2 nm, 50 nm, 10 nm, respectively, ric dimensions are intended to promote electric performance.
and L, L 1 = L 2 , W, M 1 , and M 2 of 40 nm, 20 nm, A good ION/IOFF ratio of 3.84 × 1010 was obtained, with a
5 nm,4.03eVand 4.6 eV. comparatively low subthreshold swing of 48.26 mV/dec.

Hetero-Dielectric Gate SOI TFET Debika Das et al. [6] pro-

posed an SOI TFET with a dual dielectric pocket. The results
suggest this device not prone to ON current deterioration rel-
ative to ambipolar behavior in the presence of interface traps.
Dielectric gate oxide gives capable ION and prevents reverse
leakage problems. The structure comprises a hetero-dielectric
SOI TFET gate, which uses the p + Si1-xGex layer among
source and channel. The valence band relative to the conduc-
tion band at the tunnel contact the low-bandgap material used
at the interface from the source t channel promotes ION. A
vacuum dielectric pocket in the source channel junction and
SiO2 in the drain channel junction as a dielectric pocket. This
Fig. 11 GC-DMTG SON-TFET schematic representation pocket combination enables consistent output for low-power
Silicon (2022) 14:3185–3197 3191

Table 2 Different electrical parameters comparison of Tri-Gate-TFET Devices

References Device architecture ION IOFF ION / IOFF Channel Vth SS

[26] GC-DM-TG-SON-TFET 4×10−6 A/μm 1×10−13 A/μm 4×107 40 nm 0.5 V –

[27] DM-TG-SON-TFET 1.6×10−4 A/μm 1×10−13 A/μm 1.4×109 0.04 μm 0.3 V –
[28] TM-TG-JLTFET 1×10−3 A/μm 8×10−15 A/μm 12.5×1012 152 nm 0.4 V 47 mV/dec

applications like high ON current (ION), low OFF current InAs in the source field, the tunneling window is better
(IOFF), steeper SS, a lower threshold voltage (Vth). over a source-channel intersection. The author has selected
Figure 15 shows the hetero-dielectric gate SOI TFET 2D parameters for the proposed DG-TFET heterojunction as
structure. The increase in tSiGe contributes to an increase in Gate length 20 nm, toxf- 2 nm, toxb - 2 nm, tGr - 10 nm, and
ON current accordingly. The nominal ON current has a thick- the electrical parameters as source Doping concentration 1 ×
ness of 5 nm, a 5.77 × 10− 5A/μm at the ON / OFF ratio of 1020 cm−3, Channel Doping concentration 1 × 1016 cm−3,
2.43 / 1012. The ION = 1.02 × 10−5 A / μm at the very same Drain Doping concentration 5 × 1018 cm−3, Metal 1 work
time, ON / OFF ratio of 4.53 ~ 1011 at the SS of 14 mV/dec at function (ɸm1) 4.5 eV, Metal 2 work function (ɸm2) 4 eV,
the tSiGe of 2 nm. It suggested that the existing SOI TFET Gate Voltage (VG) 1 V, Supply Voltage (VDD) 0.7 V ~ 1 V.
heterojunction offers optimum efficiency for a 1 nm The device has been designed as the TFET system’s double
underlapping gate-source (Tun) & 5 nm SiGe, if both ON gate (front and rear gate) consists of two metals (M1 and M2)
and OFF current obtained 1.16*10−4 A / μm and 3.32 A/μm with different functions linked around the channel area as
as well as 3.32 TA/ μm. It reflects a high ON / OFF ratio of shown in Fig. 16. The overall length of the channel area (L)
1012. The threshold voltage (Vth) and SS were 0.39 V and has two parts of the region (R1 and R2), which are expected to
2 mV/decade, respectively. The proposed TFET structure of- be (L′ and L′′) along the x-axis, respectively. P+ source doping
fers a high ON / OFF current ratio of 3.49/1012, with a drain (NS) = 1020 cm−3, N+ drain doping (ND) = 5 × 1018 cm−3, in-
current of 1.16/10−4 A / μm and a steeper subthreshold swing trinsic channel doping (Nch) = 1016 cm−3, body thickness
of 2 mV/dec. (tGr) = 10 nm, dielectric (SiO2) thickness (toxf = toxb = 2 nm),
channel length (L = L1 + L2) = 20 nm, L1 = 10 nm and L2 =
InAs/Si -H-DG-DM TFET Carbon material such as graphene has 10 nm. The author developed a heterojunction in the original
mainly been examined as a suitable alternative for low-power Silicon (Si) region by adding Indium Arsenide (InAs). As
carbon nanotubes. Mono-layer, two-layer graphene is often InAs has a lower power band-gap of 0.35 eV, well below
used as a channel material for FET tunnels. Ritam Dutta 1.12 eV Si, direct tunneling increases the current in the drain
et al. [7] proposed the InAs/Si Hetero-Junction DG-DM- stream. InAs also have very high mobility of electrons and
TFET. holes, approximately four by 10 4 cm 2 /V, and five by
102 cm2/V increase the ION/IOFF switching ratio. Also, sub-

Fig. 12 DMTG SON TFET with SiO2/HfO2 stacked gate oxide

schematic view Fig. 13 Drain current characteristics of tri gate TFET
3192 Silicon (2022) 14:3185–3197

Fig. 14 Hetero-structure vertical TFET Schematic representation Fig. 16 Schematic representation of an InAs/Si -H-DG-DM TFET

threshold swing (SS) at 20.76 mV / decade and ION/IOFF at the between SiGe pocket regions and silicon source regions en-
InAs/Si graphene DG-TFET ratio is 108. courages a strong bending of the energy band. The result of
the TCAD simulation shows that the HTG-TFET proposed
H-DGTFET ShylendraAsish et al. [8] suggested InAs/Si Hetero achieves both higher current on-state and lower SS. The
Double Gate FET Tunnel. The authors selected the channel HTG-TFET transforms point tuning parallel to the channel
region for silicon with a concentration of 1 to 1015 cm−3, and it into a channel line tube perpendicular to the channel.
is formed by InAs, with a concentration of 1 to 1020 cm−3; Figure 18 illustrates the schematic representation of HTG-
however, silicone drainage formed with n-type material at a TFET. The lateral direction of the gate overlap also raises
concentration of 1 to 1019 cm−3. the electrical field and the tunnel region at the top of the tunnel
Molybdenum, a midgap gate material with a working feature crossing when the device is activated.
of 4.53 eV, has been considered. Figure 17 depicts H-DGTFET Using the Silvaco ATLAS-Simulation Tool, the proposed
Cross-sectional view. A Schenk trap-assisted tunneling model HTG-TFET structure has analyzed utilizing the non-local
and a trap-assisted model were both used with greater precision. BTBT model, Fermi-Dirac statistics, Shockley- Read-Hall, and
The H-DG-TFET threshold voltage was determined using the Lombardi mobility models. Also, the heterojunctions between
TC method and the constant current method. Furthermore, the the silicone source and the SiGe pocket regions provide the de-
production H-DG-TFET was improved with the SS pitch and vice with improved performance, with the HTG-TFET achieving
the GD profile OFF current. The RF performance with UD and a maximum current in the on-state of 7,02A/μm, an average SS
GD has also been examined for various CLs. of 44.64 mV/dec, and an SS of 36,59 mV/dec with Vg = 0.2 V.

HTG-TFET Wei Li [30] et al. proposed a novel T-shaped TFET Hetero-Gate JLTFET Shiromani BalmukundRahi et al. [31]
(HTG-TFET) heterojunction. The device consists of vertical This suggested that the heterogate structure JL-TFET, without
tunneling and places two areas on either side of the gate to p-n junctions, shows better system efficiency than traditional
stretch the tunneling area further. The T-shaped gate overlaps p-n junction architectures. The author has used a broken
the pocket areas at the top of the tunnel connection on the side AlGaAs/Si semiconductor band-gap source to boost the ION
to increase the electric field. In addition, heterojunction and remove the IOFF and the subthreshold slope (SS). The
device has 5-nm-thick AlGaAs/Si-doped evenly with a 2 nm

Fig. 15 Hetero-dielectric gate SOI TFET 2D structure Fig. 17 H-DGTFET Cross-sectional view
Silicon (2022) 14:3185–3197 3193

Fig. 20 Schematic representation of a 3D- WSe2/SnSe2 heterojunction

TFET

Fig. 18 HTG-TFET Schematic representation

heterojunction with contacts Pd Schottky on either side of
oxide thickness. As shown in Fig. 19, the control gate length the intersection. With 10 nm WSe2 flakes and relatively thick,
(LG) and the auxiliary gate length (LG1) are 20 nm. multilayer SnSe2 flakes, the system has developed, as shown
The ION value for the simulated device was 7.2 × 10–7, in Fig. 20.
1.2 × 10–6, and 2.0 × 10–6 A/μm for high-k gate dielectric For the tunneling system, the WSe2 FET retains a higher
materials HfO2 (k = 25), La2O3 (k = 30), and TiO2 (k = 80), ION current as estimated. The WSe2/SnSe2 TFET offers a
respectively. However, IOFF for TiO2 was ≈10−14 to 10−13 transconductance boost of about 70% over the WSe2 FET in
A/μm. The electrical parameters extracted from the simulated the subthreshold range. The author reported on the same flake
device such as IOFF (A/μm) and ION (A/μm) while varying the realized co-integrated 2D/2D WSe2 / SnSe2 tunnel FET and
doping concentration (cm − 3) as 1 × 1016, 1 × 1017, 1 × 1018, WSe2 MOSFET subthermionic. The device created by a rel-
1 × 1019, 2 × 1019 as 2.3 × 10−14 and 5.5 × 10−7, 2.4 × 10−14 atively low gate stack heterogonal system of tungsten / HfO2
and 4.7 × 10−7, 3.9 × 10−14 and 7.2 × 10−7, 4.8 × 10−14 and of vander Waals A sub-threshold slope of 35 mV per 10 years
6.0 × 10−7 respectively. In heterogeneous JL-TFET, this meth- at vds = 500 mV with a lasting IOFF < 0.1 pAμm−2 and an
od guarantees high-performance and efficient electricity by excellent ON/OFF current ratio of more than 105.
mixing high and low-carbon dielectric materials. Included in
the simulated tests are ION10−6 A/μm and IOFF 10−14A /μm for Ge/GeSn HTFET Christian et al. [33] proposed the Ge/GeSn
La2O3. The ION/IOFF alloy 108 and the subthreshold slope of HTFET, which is mainly a new material of choice for low-
the same dielectric is 47.2 mV/dec. power transistors. This employed Ge/GeSn to approach elec-
tronic band structure with a direct band-gap of growing Sn
WSe2/SnSe2 HETEROJUNCTION TFET NicolòOliva et al. [32] amount fraction. Singular crystalline Ge / GeSn epilayers
suggested the design of back gated WSe 2 / SnSe 2 formed over Ge-buffered Si(001) (Ge-virtual surface —

Fig. 19 Heterogate JL-TFET

Schematic representation
3194 Silicon (2022) 14:3185–3197

Fig. 22 Drain current characteristics of HTFET

Fig. 21 Ge/GeSn vertical pTFET fabrication
It is inferred from the figure that the HTFET [8] structure
GeVS) 200 mm and 300 mm wafers employing shortened provides a better ON current than the HTFET device
chemical vapor accumulation as shown in Fig. 21. configuration.
The device shows shifting over magnitude (104) with
drain-current 2.4 μA/μm at VGov = −2 V, Vds = −0.5 V. At
Vds = VGov = −0.5 V is 0.012 μA/μm, where VGov - gate
overdrive voltage for minimum drain current ION. Hence, a 6 Conclusion
comprehensive report of Ge/GeSn heterostructure pTFETs
presented. Devices have greater performance than those of In the last few decades, the rapid and relentless development
the previous reports GeSn pTFETs. An intensely scalable of the MOS transistor contributed to the exponential growth of
three-layer gate-stack of Cacc = 3 μF/cm2 and EOT = the Semi-conductor industry. The roadmap incorporates dif-
0.84 nm were designed to obtain effective electrostatics. The ferent channel substances to widen the transistor beyond 3 nm
optimized model shows the competitive output with ION = when the rule of Moore is challenged. Hence for ultra-low
0.4 μA/ μm and sub-60 mV/decade upwards of three ranges power implementations, the revolutionary devices could in-
of drain current magnitude for an operating voltage (0.5 V) clude sophisticated TFET structures, spin-wave structures,
with higher Sn material, lower Trap Densities and ultra-thin and 3D-nano materials. In this review article Double Gate,
body geometry (UTB). Table 3 shows the different electrical Tri-Gate, and Heterojunction TFET structures have been com-
parameters comparison of Heterojunction-TFET Devices. pared and suggested a systematic survey and overview of
Figure 22 shows the drain current characteristics of HTFET. various device architectures for Heterojunction TFET. This

Table 3 Different electrical parameters comparison of Heterojunction-TFET Devices

References Device Architecture ION IOFF ION / IOFF Channel Vth SS

[29] HV-TFET 1×10−5 A/μm 1×10−14 A/μm 3.84×109 8 nm 0.76 V 48.26 mV/dec
[6] DM-DG-HTFET 1.16×10−4 A/μm 3.32×10−17 A/μm 3.49×1012 0.08 μm 0.39 V 2 mV/dec
[7] H-SOI-TFET 1×10−4 A/μm 1×10−12 A/μm 1×108 20 nm 0.19 V 20.76 mV/dec
[8] DG-HTFET 166.6×10−6A 7.55×10−9A 22.06×103 0.20 nm 0.6 V 50 mV/dec
[30] T-HTFET 7.02 1×10−12 A/μm 7×1012 40 nm 0.2 V 36.59 mV/dec
μA/μm
[31] H-JL-TFET 1.2×10−6 1×10−14 1×108 0.06 μm 0.6 V 47.2 mV/dec
A/μm A/μm
[32] HTFET 1×10−8 A/μm 1×10−15 A/μm 1×107 – 0.5 V 35 mV/dec
[33] H-pTFET 2.4×10−6 0.012 μA/μm 9.2×103 – 0.5 V –
A/μm
Silicon (2022) 14:3185–3197 3195

paper shows the likelihood of drain current enhancement 6. Das D, Chakraborty U (2020) A study on dual dielectric pocket
Heterojunction SOI tunnel FET performance and flicker noise anal-
through finding suitable device configurations beneath
ysis in presence of Interface traps. Silicon. 13:787–798. https://doi.
Heterojunction TFET & thereby lessens the reverse leakage org/10.1007/s12633-020-00488-0
current. It examines and evaluates parameters such as the ION/ 7. Ritam D, Subash TD, Paitya N (2020) InAs/Si hetero-junction
IOFF ratio, channel length (L), subthreshold swing (SS), and channel to enhance the performance of DG-TFET with
the cut-off frequency of various interface architectures. The GrapheneNanoribbon: an analytical model. Silicon. 13:1453–
1459. https://doi.org/10.1007/s12633-020-00546-7
value of using different designs of systems progresses to a 8. Ahish S, Sharma D, Kumar YBN, Vasantha MH (2016)
successful SS. It has been further concluded that Indium Performance enhancement of novel InAs/Si hetero double-gate
Arsenide and Silicon-based heterojunction double gate dual- tunnel FET using Gaussian doping. IEEE Transactions On
material TFET provides the better ION current and low leakage Electron Devices 63:288–295. https://doi.org/10.1109/TED.2015.
2503141
current. The system-level layout is also discussed an attractive
9. RanjanTripathy M, Singh AK, Chander S, Singh PK, Baral K, Jit S
prospect for ultra-low-power technology. (2020) Device-level performance comparison of some pocket
engineered III-V/Si hetero-junction vertical tunnel field
EffectTransistor. International Conference on Devices, Circuits
Contributions Writing - literature search and analysis, original draft and Systems. https://doi.org/10.1109/ICDCS48716.2020.243576
preparation: [J.E.Jeyanthi] [A.Sharon Geege], Idea of the article, 10. Haris M, Loan SA, Mainuddin (2017) An Ambipolar Immune Si/
Resources, Supervision: [T.S.Arun Samuel], Checked the comparison GaAs Hetero-junction Doping-less TFET. International conference
results and validation: [P.Vimala]. on Microelectronic Devices, Circuits and Systems. https://doi.org/
10.1109/ICMDCS.2017.8211539
Code Availability Not Applicable. 11. Biswal SM, Swain SK, BiswajitBaral DN, Nanda U,
DhananjaTripthy SKD (2019) Performance analysis of staggered
Heterojunction based SRG TFET biosensor for health IoT appli-
Declarations cation. Devices for Integrated Circuit (DevIC). https://doi.org/10.
1109/DEVIC.2019.8783813
Ethics Approval and Consent to Participate All authors freely agreed 12. Dewey G, Chu-Kung B, Boardman J, Fastenau JM, Kavalieros J,
and gave their consent for the publication of this paper. Kotlyar R, Liu WK, Lubyshev D, Metz M, Mukherjee N, Oakey P,
Pillarisetty R, Radosavljevic M, Then HW, Chau R (2011)
Consent for Publication All authors freely agreed and gave their consent Fabrication, characterization, and physics of III-V Heterojunction
for the publication of this paper. tunneling field effect transistors (H-TFET) for steep sub-threshold
swing. International Electron Devices Meeting. https://doi.org/10.
Conflicts of Interest/Competing Interests The authors have no relevant 1109/IEDM.2011.6131666
financial or non-financial interests to disclose. 13. Chien ND, Shih C-H (2016) Oxide thickness-dependent effects of
source doping profile on the performance of single- and double-gate
tunnel field-effect transistors. Superlattice Microst 102:284–299.
https://doi.org/10.1016/j.spmi.2016.12.048
14. Lee MJ, Choi WY (2011) Analytical model of single-gate silicon-
References on-insulator (SOI) tunneling field-effect transistors (TFETs). Solid
State Electron 63:110–114. https://doi.org/10.1016/j.sse.2011.05.
1. Navya Shree G, Priyadarshini U, Keerthana M, Vimala P (2020) 008
Design of gate engineered heterojunction surrounding gate tunnel 15. Wang PF, Hilsenbeck K, Nirschl TH, Oswald M, Stepper CH,
field effect transistor (HSG TFET). International Conference on Weiss M, Landsiedel DS, Hansch W (2004) Complementary
Emerging Trends in Information Technology and Engineering tunneling transistor for low power applications. Solid State
https://doi.org/10.1109/icETITE47903.2020.230 Electron 48(12):2281–2286
2. Sahoo S, Dash S, Mishra GP (2018) An extensive simulation study 16. Lee MJ, Choi WY (2011) Analytical model of a single-gate silicon-
of Gaussian drain doped Heterojunction Double Gate TFET. IEEE on-insulator (SOI) tunneling field-effect transistors (TFETs). Solid
Electron Device KolkataConference.https://doi.org/10.1109/ State Electron 63(1):110–114
EDKCON.2018.8770387 17. Mallikarjunarao RR, Pradhan KP, Sahu PK (2016) Dielectric
3. Madan J, SkandaShekhar RC (2017) Gate metal engineered engineered symmetric underlap double gate tunnel FET
Heterojunction DGTFETs for superior analog performance and en- (DGTFET): an investigation towards variation of dielectric mate-
hanced device reliability. Conference on Information and rials. Superlattice Microst 96:226–233. https://doi.org/10.1016/j.
Communication Technology. https://doi.org/10.1109/ spmi.2016.05.035
INFOCOMTECH.2017.8340634 18. Wang Y, Wang Y-f, Xue W, Cao F (2016) Asymmetric dual-gate
4. Madan J, Karwal K, Chaujar R (2018) Performance analysis of tunneling FET with improved performance. Superlattice Microst
Heterojunction DMDGTFET with different source materials for 91:216–224. https://doi.org/10.1016/j.spmi.2016.01.017
analog application. Proceedings of the 2nd International 19. Kumar S, EktaGoel KS, Singh B, Singh PK, Baral K, Jit S (2017) 2-
Conference on Trends in Electronics and Informatics. https://doi. D analytical modeling of the electrical characteristics of dual-
org/10.1109/ICOEI.2018.8553716 material double- gate TFETs with a SiO2/HfO2 stacked gate-
5. Pindoo IA, Sinha SK, Tripathi SL (2019) Performance analysis of oxide structure. IEEE Transactions On Electron Devices 64:960–
double gate Heterojunction tunnel field effect transistor. 968. https://doi.org/10.1109/TED.2017.2656630
International Conference on Cutting-edge Technologies in 20. Liu X, Hu H, Wang M, Zhang H, Cui S, Shu B, Wang B (2017)
Engineering. https://doi.org/10.1109/ICon-CuTE47290.2019. Study of novel fully-depleted Ge double-gate tunneling field-effect
8991467 transistors for improvement in on-state current and sub-threshold
3196 Silicon (2022) 14:3185–3197

swing. Physica E: Low-dimensional Systems and Nanostructures 35. HwaSeo J, Yoon YJ, Kwon RH, In Jang Y, Kang IM (2016) Design
95:51–58. https://doi.org/10.1016/j.physe.2017.08.014 optimization of Si/Ge-based Heterojunction arch-shaped gate-all-
21. Madan J, Kaur R, Sharma R, Pandey R, RishuChaujar (2018) around (GAA) tunneling field-effect transistor (TFET) which appli-
Electrical characteristics assessment of gate metal and source pock- cable for future Mobile communication systems. International
et engineered DG-TFET for low power analog applications. IEEE Conference on Information Networking. https://doi.org/10.1109/
Electron Device Kolkata Conference. https://doi.org/10.1109/ ICOIN.2016.7427155
EDKCON.2018.8770462 36. Jae HwaSeo, Young Jun Yoon, Hwan Gi Lee, In Man Kang (2018)
22. Meshkin R, SedighZiabari SA, RezaeeJordehi A (2018) A novel Design optimization InGaAs/GaAsSb-based Heterojunction Gate-
analytical approach to optimize the work functions of dual-material All-Around (GAA) arch-shaped tunneling field-effect transistor (A-
double-gate tunneling-FETs. Superlattice Microst 126:63–71. TFET). International Conference on Electronics, Information, and
https://doi.org/10.1016/j.spmi.2018.12.016 Communication. https://doi.org/10.23919/ELINFOCOM.2018.
23. Priya GL, Venkatesh M, Balamurugan NB (2021) Triple metal 8330638
surrounding gate junctionless tunnel FET based 6T SRAM design 37. Afzalian A, Doornbos G, Shen T-M, Passlack M (2018) A high-
for low leakage memory system. Silicon. https://doi.org/10.1007/ performance InAs/GaSb core-shell nanowire line-tunneling TFET:
s12633-021-01075-7 An atomistic mode-space NEGF study. IEEE J Electron Devices
24. Venkatesh M, Balamurugan NB (2020) Influence of threshold volt- Soc. https://doi.org/10.1109/JEDS.2018.2881335
age performance analysis on dual halo gate stacked triple material 38. G. Dewey, B. Chu-Kung, J. Boardman, J. M. Fastenau, J.
dual gate TFET for ultra low power applications. Silicon http://link. Kavalieros, R. Kotlyar, W. K. Liu, D. Lubyshev, M. Metz, N.
springer.com/article/10.1007/s12633-020-00422-4 13:275–287 Mukherjee, P. Oakey, R. Pillarisetty, M. Radosavljevic, H. W.
25. Venkatesh M, Suguna M, Balamurugan NB (2020) Influence of and R. Chau (2011) Fabrication, characterization, and physics of
germanium source dual halo dual dielectric triple material surround- III-V Heterojunction tunneling field effect transistors (H-TFET) for
ing gate tunnel FET for improved analog/RF performance. Silicon. steep sub-threshold swing. International Electron Devices Meeting
http://link.springer.com/article/10.1007/s12633-020-00385-6 12: https://doi.org/10.1109/IEDM.2011.6131666
2869–2877 39. Ke S, Hu J, Xu X (2019) Independent-gate P-type TFETs using
26. Dewan MI, Kashem MTB, Subrina S (2016) Characteristic analysis double Heterojunction structures. IEEE International Symposium
of triple material tri-gate Junctionless tunnel field effect transistor. on Circuits and Systems. https://doi.org/10.1109/ISCAS.2019.
International Conference on Electrical and Computer Engineering. 8702154
https://doi.org/10.1109/ICECE.2016.7853924 40. Han-Lin H, Hu VP-H (2018) Device design of vertical nanowire
27. Dash DK, PriyankaSaha AM, Sarkar SK (2017) 3-D analytical III-V heterojunction TFETs for performance enhancement.
modeling of dual-metal front-gate stack tri-gate SON-TFET with International Symposium on Next Generation Electronics. https://
Graded Channel engineering. IEEE Calcutta Conference. https:// doi.org/10.1109/ISNE.2018.8394742
doi.org/10.1109/CALCON.2017.8280724 41. Lv Y, Huang Q, HaoWang SC, He J (2016) A numerical study on
28. Saha P, Sarkhel S (2018) 3D modeling based performance analysis Graphene Nanoribbon Heterojunction dual-material gate tunnel
of gate engineered trigate SON TFET with SiO2/HfO2 stacked gate FET. IEEE Electron Device Letters 37:1354–1357. https://doi.org/
oxide. IEEE International Conference on Electronics, Computing 10.1109/LED.2016.2597155
and Communication Technologies. https://doi.org/10.1109/ 42. Shih P-C, Hou W-C, Li J-Y (2017) A U-gate InGaAs/GaAsSb
CONECCT.2018.8482379 Heterojunction TFET of tunneling normal to the gate with separate
29. Vanlalawmpuia K, Bhowmick B (2020) Optimization of a Hetero- control over ON- and OFF-state current. IEEE Electron Device
structure vertical tunnel FET for enhanced electrical performance Letters 38:1751–1754. https://doi.org/10.1109/LED.2017.2759303
and effects of temperature variation on RF/linearityparameters. 43. Yang S, HongliangLv BL, Yan S, Zhang Y (2020) A novel planar
Silicon. https://doi.org/10.1007/s12633-020-00411-7 architecture for Heterojunction TFETs with improved performance
30. Li W, Liu H, Wang S, Chen S, Yang Z (2017) Design of High and its digital application as an inverter. IEEE Access 8:23559–
Performance Si/SiGe Heterojunction tunneling FETs with a T- 23567. https://doi.org/10.1109/ACCESS.2020.2970502
shaped gate. Nanoscale Res Lett. https://doi.org/10.1186/s11671- 44. YaweiLv QH, Wang H, Chang S, Member, He J (2016) A numer-
017-19583 ical study on GrapheneNanoribbon Heterojunction dual-material
31. ShiromaniBalmukundRahi PA, Gupta S (2017) gate tunnel FET. IEEE Electron Device Letters 37:1354–1357.
Heterogatejunctionless tunnel field-effect transistor: future of https://doi.org/10.1109/LED.2016.2597155
low-power devices. J Comput Electron 16:30–38. https://doi.org/ 45. Hraziia AV, Amara A, CostinAnghel (2012) An analysis on the
10.1007/s10825-016-0936-9 ambipolar current in Si double-gate tunnelFETs. Solid State
32. Oliva N, Capua L, Cavalieri M, Luisier M, Ionescu AM (2020) Electron 70:67–72. https://doi.org/10.1016/j.sse.2011.11.009
WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic 46. Vanitha P, Arun Samuel TS, Nirmal D (2018) A new 2- D mathe-
characteristic and MOSFET co-integrated on same WSe2 flake. npj matical modeling of surrounding gate triple material tunnel FET
2D Materials and Applications. https://doi.org/10.1038/s41699- using halo engineering for enhanced drain current. Int J Electron
020-0142-2 Commun 99:34–39. https://doi.org/10.1016/j.aeue.2018.11.013
33. Schulte-Braucks C, Pandey R, Sajjad RN, Barth M, Ghosh RK, 47. Tamersit K (2020) Performance enhancement of an ultra-scaled
Grisafe B, Sharma P, von den Driesch N, Vohra A, Rayner Jr double-gate graphene-nanoribbon tunnel field-effect transistor
GB, Loo R, Mantl S, Buca D, Chih-ChiehYeh C-HW, Tsai W, using channel doping engineering: quantum simulation study. Int
Antoniadis DA, Datta S (2017) Fabrication, characterization, and J Electron Commun 122:153287. https://doi.org/10.1016/j.aeue.
analysis of Ge/GeSn Heterojunction p-type tunnel transistors. IEEE 2020.153287
Transactions on Electron Devices 64:4354–4362. https://doi.org/ 48. Bagga N, Sarkar SK (2015) An analytical model for tunnel barrier
10.1109/TED.2017.2742957 modulation in triple metal double gate TFET. IEEE Transactions on
34. Sangeetha G S, T. E Ayoob Khan, Dr.Shahul Hameed T A (2016) Electron Devices 62:2136–2142. https://doi.org/10.1109/TED.
SiGe/Si Heterojunction TFET for analog signal applications. 2015.2434276
International Conference on Next Generation 49. Bagga N, Sarkhel S, Sarkar SK (2016) Analytical model for ID-VD
IntelligentSystems.https://doi.org/10.1109/ICNGIS.2016.7854035 characteristics of a triple metal double gate TFET. International
Silicon (2022) 14:3185–3197 3197

Conference on Computing, Communication and Automation. aligned triple gate SOI p-type Tunnel FET output characteristic.
https://doi.org/10.1109/CCAA.2016.7813939 Symposium on Microelectronics Technology and Devices. https://
50. Ko E, Lee H, Park J-D, Shin C (2016) Vertical tunnel FET: design doi.org/10.1109/SBMicro.2017.8112973
optimization with triple metal-gate layers. IEEE Transactions On 55. Dewey G, Chu-Kung B, Boardman J, Fastenau JM, Kavalieros J,
Electron Devices 63:5030–5035. https://doi.org/10.1109/TED. Kotlyar R, Liu WK, Lubyshev D, Metz M, Mukherjee N, Oakey P,
2016.2619372 Pillarisetty R, Radosavljevic M, Then HW, Chau R (2011)
51. Komalavalli S, Arun Samuel TS, Vimala P (2019) Performance Fabrication, characterization, and physics of III-V Heterojunction
analysis of triple material tri gate TFET using 3D analytical model- tunneling field effect transistors (H-TFET) for steep sub-threshold
ling and TCAD simulation. Int J Electron Commun 110:152842. swing. International Electron Devices Meeting. https://doi.org/10.
https://doi.org/10.1016/j.aeue.2019.152842 1109/IEDM.2011.6131666
52. Rao M, Ranjan R, Pradhan KP, Sahu PK (2016) Performance anal- 56. Ke S, Hu J, Xu X (2019) Independent-gate p-type TFETs using
ysis of symmetric High-k Spacer (SHS) trigate SOI TFET. double heterojunction structures. IEEE International Symposium
International Conference on Devices, Circuits and Systems. on Circuits and Systems. https://doi.org/10.1109/ISCAS.2019.
https://doi.org/10.1109/ICDCSyst.2016.7570642 8702154
53. Safa S, Noor SL, Khan MZR (2016) Triple material double gate
TFET with optimized Si film thickness. International Conference
Publisher’s Note Springer Nature remains neutral with regard to jurisdic-
on Electrical Engineering and Information Communication
tional claims in published maps and institutional affiliations.
Technology. https://doi.org/10.1109/CEEICT.2016.7873039
54. Torres HLF, Martino JA, Rooyackers R, Vandooren A, Simoen E,
Claeys C, Agopian PGD (2017) Proton radiation effects on the self-