Roll No.: 23294917080 | B. Tech.

ECE B--B2 Experiment 5

Experiment 5
Ring Oscillator

5.1 Aim
• Design and simulate a three-stage and five-stage CMOS ring oscillator

• Measure the oscillation frequency and period

• Study the effect of supply voltage variation on oscillation frequency

• Study the effect of transistor W/L ratio variation on oscillation frequency

• Study the effect of load capacitance variation on oscillation frequency

5.2 Theory
• A ring oscillator is a device composed of an odd number of NOT gates (inverters)
in a ring, whose output oscillates between two voltage levels.

• The main principle of operation is based on the signal propagation delay through
each inverter stage. With an odd number of inverters connected in a closed loop,
the circuit becomes unstable and oscillates.

• Due to the odd number of inversions around the loop, the circuit has no stable
operating point and continuously switches between logic states.

• The oscillation frequency is determined by the propagation delay of each inverter

and the number of stages. The period of oscillation is approximately 2 × n × td,
where n is the number of inverter stages and td is the propagation delay of each
inverter.

• Ring oscillators are widely used in VLSI systems for clock generation, phase-locked
loops (PLLs), and as a benchmark circuit for characterizing process variations in
integrated circuit manufacturing.

• They provide a simple way to generate clock signals without using external
components like crystals or inductors, making them suitable for on-chip
applications where area and cost are important factors.

5.3 LTspice Code

5.3.1 Three-Stage Ring Oscillator

26
 Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 5

Listing 5.1: Task-1: Three-Stage Ring Oscillator

1

2
3

5 VDD Vdd 0 DC 5
6

8 M1 out1 out3 Vdd Vdd PMOS_MOD =10 u L=1 u

9 M2 out1 out3 0 0 NMOS_MOD =10 u L=1 u
10 C1 out1 0 1 p
11

12

13 M3 out2 out1 Vdd Vdd PMOS_MOD =10 u L=1 u

14 M4 out2 out1 0 0 NMOS_MOD =10 u L=1 u
15 C2 out2 0 1 p
16

17

18 M5 out3 out2 Vdd Vdd PMOS_MOD =10 u L=1 u

19 M6 out3 out2 0 0 NMOS_MOD =10 u L=1 u
20 C3 out3 0 1 p
21

22

23

24
25

26

27

28

5.3.2 Five-Stage Ring Oscillator

Listing 5.2: Task-2: Five-Stage Ring Oscillator

1

2
3

5 VDD Vdd 0 DC 5
6

8 M1 out1 out5 Vdd Vdd PMOS_MOD =10 u L=1 u

9 M2 out1 out5 0 0 NMOS_MOD =10 u L=1 u
10 C1 out1 0 1 p
11

12
13 M3 out2 out1 Vdd Vdd PMOS_MOD =10 u L=1 u
14 M4 out2 out1 0 0 NMOS_MOD =10 u L=1 u
15 C2 out2 0 1 p
16

17

18 M5 out3 out2 Vdd Vdd PMOS_MOD =10 u L=1 u

19 M6 out3 out2 0 0 NMOS_MOD =10 u L=1 u
20 C3 out3 0 1 p
21

22

27
 Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 5

23 M7 out4 out3 Vdd Vdd PMOS_MOD =10 u L=1 u

24 out3 0 0 NMOS_MOD =10 u L=1 u
25 0 1p
26

27

28 M9 out5 out4 Vdd Vdd PMOS_MOD =10 u L=1 u

29 M10 out5 out4 0 0 NMOS_MOD =10 u L=1 u
30
31

32

33

34

35
36

37

38

5.3.3 Effect of Supply Voltage Variation

Listing 5.3: Task-3: Effect of Supply Voltage Variation

1
2

7
8 M1 out1 out3 Vdd Vdd PMOS_MOD =10 u L=1 u
9 M2 out1 out3 0 0 NMOS_MOD =10 u L=1 u
10 C1 out1 0 1 p
11
12

13 M3 out2 out1 Vdd Vdd PMOS_MOD =10 u L=1 u

14 M4 out2 out1 0 0 NMOS_MOD =10 u L=1 u
15 C2 out2 0 1 p
16

17
18 M5 out3 out2 Vdd Vdd PMOS_MOD =10 u L=1 u
19 M6 out3 out2 0 0 NMOS_MOD =10 u L=1 u
20 C3 out3 0 1 p
21

22
23

24

25

26

27

28
29

5.3.4 Effect of W/L Ratio Variation

Listing 5.4: Task-4: Effect of W/L Ratio Variation

28
 Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 5

3
4

5 VDD Vdd 0 DC 5
6

8 M1 out1 out3 Vdd Vdd PMOS_MOD W={ w} L=1 u

9 M2 out1 out3 0 0 NMOS_MOD =10 u L=1 u
10 C1 out1 0 1 p
11

12

13 M3 out2 out1 Vdd Vdd PMOS_MOD W={ w} L=1 u

14 M4 out2 out1 0 0 NMOS_MOD =10 u L=1 u
15 C2 out2 0 1 p
16

17

18 M5 out3 out2 Vdd Vdd PMOS_MOD W={ w} L=1 u

19 M6 out3 out2 0 0 NMOS_MOD =10 u L=1 u
20 C3 out3 0 1 p
21

22

23

24
25

26

27 param w 10 u 20 u 30 u W/
28

29

5.3.5 Effect of Load Capacitance Variation

Listing 5.5: Task-5: Effect of Load Capacitance Variation

1 * Three - Stage Ring Oscilla tor with Load C a pa cita nce Variation
2 . include " Mode l_ file . txt" ; Incl ude NMOS and PMOS models
3

4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power suppl y
6

7 * First inverter
8 M1 out1 out3 Vdd Vdd PMOS_MOD W =10 u L=1 u
9 M2 out1 out3 0 0 NMOS_MOD W =10 u L=1 u
10 C1 out1 0 { co} ; Va riable load capacitance
11

12 * Second inverter
13 M3 out2 out1 Vdd Vdd PMOS_MOD W =10 u L=1 u
14 M4 out2 out1 0 0 NMOS_MOD W =10 u L=1 u
15 C2 out2 0 { co} ; Va riable load capacitance
16

17 * Third inverter
18 M5 out3 out2 Vdd Vdd PMOS_MOD W =10 u L=1 u
19 M6 out3 out2 0 0 NMOS_MOD W =10 u L=1 u
20 C3 out3 0 { co} ; Va riable load capacitance
21

22 * Initia l conditi on to start oscillati on

23 . ic V( ou t1 ) =0 V( out2 ) =5 V( out3 ) =0

29
 Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 5

24

25

26
27 5 p 10 p
28

29

5.4 Result
5.4.1 Oscillation Frequency Calculation

Listing 5.6: Oscillation Frequency and Period Calculation

1 For the three - stage ring oscillator:
2 Period = Time between conse cutive rising edges of out1
3 Period = 58.3 ns - 21.7 ns = 36.6 ns
4 Frequency = 1/ Period = 1/36.6 ns = 27.32 MHz
5

6 For the five - stage ring os cillator:

7 Period = Time between conse cutive rising edges of out1
8 Period = 96.5 ns - 38.2 ns = 58.3 ns
9 Frequency = 1/ Period = 1/58.3 ns = 17.15 MHz
10

11 The the or e tica l re la tionship is confir me d where :

12 Frequency 1/(2 n td)
13 Where n is the number of stages , and td is the propagat ion delay
per stage

5.4.2 Effect of Supply Voltage on Frequency

Listing 5.7: Supply Voltage Effect Analysis

1 Supply Volta ge ( V) O s cil la ti on Period ( ns) Frequenc MHz)
2 3 52.1 19.19
3 5 36.6 27.32
4 7 29.3 34.13
5

7
8

5.4.3 Effect of W/L Ratio on Frequency

Listing 5.8: W/L Ratio Effect Analysis

1 PMOS W/ L Ratio O s cil la ti on Period ( ns) Frequenc MHz)
2 10 u/1 u 36.6 27.32
3 20 u/1 u 32.8 30.49
4 30 u/1 u 30.2 33.11
5

6 Increas ing the W/ L ratio of the PMOS t ra ns is t ors incr

30
 Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 5

5.4.4 Effect of Load Capacitance on Frequency

Listing 5.9: Load Capacitance Effect Analysis

1 Load C apacitance ( pF) O s cil la ti on Period ( ns) Frequenc MHz)
2 1p 36.6 27.32
3 5p 67.3 14.86
4 10 p 98.5 10.15
5

7
8

5.4.5 Effect of Temperature on Frequency

Listing 5.10: Temperature Effect Analysis

1 Te m pe rat ure ( C ) Os cilla tion Period ( ns) Frequen MHz)
2 0 32.4 30.86
3 27 36.6 27.32
4 100 48.2 20.75
5

5.5 Observation
• The simulations demonstrated that ring oscillators with an odd number of inverter
stages produce stable oscillations with a frequency determined by the propagation
delay of each stage and the total number of stages.

• The five-stage ring oscillator has a lower oscillation frequency than the three-stage
oscillator, confirming the inverse relationship between stage count and frequency.

• Increasing the supply voltage significantly increases the oscillation frequency by

reducing the propagation delay through each inverter.

• Increasing the W/L ratio of the transistors increases the oscillation frequency due
to higher current drive capability.

• Increasing the load capacitance decreases the oscillation frequency due to increased
charging/discharging time.

• Higher temperature operation results in lower oscillation frequency due to decreased

carrier mobility.

31
Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 5

• The ring oscillator circuit provides a simple yet effective way to generate clock
signals in digital systems without external components.

• The simulation results align with the theoretical relationship: frequency 1/(2 × n
× td), where n is the number of stages and td is the propagation delay per stage.

Figure 5.1: Three-Stage Ring Oscillator Output Waveforms

Figure 5.2: Five-Stage Ring Oscillator Output Waveforms

32
Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 5

Figure 5.3: Effect of Supply Voltage Variation on Oscillation Frequency

Figure 5.4: Effect of W/L Ratio Variation on Oscillation Frequency

Figure 5.5: Effect of Load Capacitance Variation on Oscillation Frequency

33
 Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 6

Experiment 6
2:1 Multiplexer Using Transmission Gates

6.1 Aim
• Design and simulate a 2:1 multiplexer using CMOS transmission gates

• Verify the functionality of the multiplexer with different input combinations

• Study the effect of load capacitance variation on output response

6.2 Theory
• A 2:1 multiplexer (MUX) is a digital circuit that selects one of two input signals
and forwards it to the output based on a selection signal.

• A transmission gate is a CMOS switch composed of an NMOS and a PMOS

transistor connected in parallel, controlled by complementary signals.

• Unlike a conventional pass transistor, a transmission gate provides low resistance

signal path for both logic high and low levels, eliminating voltage degradation.

• When the select signal (S) is high, the transmission gate connected to input A
conducts, allowing A to pass to the output. When S is low, the transmission gate
connected to input B conducts.

• The complementary nature of transmission gates ensures that only one input path
is active at a time, preventing signal contention.

• Transmission gate-based multiplexers are widely used in VLSI design due to their
low power consumption, reduced transistor count, and bidirectional signal
capability.

• Applications include data routing in processors, memory systems, and configurable

logic blocks in FPGAs.

6.3 LTspice Code

6.3.1 Basic 2:1 Multiplexer Using Transmission Gates

Listing 6.1: Task-1: Basic 2:1 Multiplexer

1

3
4
5 VDD Vdd 0 DC 5

34
 Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 6

8
VA
9
VB
10

11

12

13

14
Sbar S Vdd Vdd PMOS_MOD =10 u L=1 u
15
Sbar S 0 0 NMOS_MOD W=5 u L=1 u
16

17

18 A S Y 0 NMOS_MOD =10 u L=1 u

19 A Y Vdd PMOS_MOD =20 u u
20
21

22 B Sbar Y 0 NMOS_MOD =10 u L=1 u

23 B S Y Vdd =20 u L=1 u
24

25

26
C1 Y 0 1 p
27

28

29

30

6.3.2 Effect of Supply Voltage Variation

Listing 6.2: Task-2: Effect of Supply Voltage Variation

1

3
4

8
9

10

11

12

13 M1 Sbar S Vdd Vdd PMOS_MOD =10 u L=1 u

14 M2 Sbar S 0 0 NMOS_MOD W=5 u L=1 u
15

16 A when
17 M3 A 0 NMOS_MOD =10 u u NMOS
18 M4 A Sbar Y Vdd PMOS_MOD =20 u L=1 u PMOS
19

20 B when
21 M5 B 0 NMOS_MOD =10 u u NMOS
22 M6 B S Y Vdd PMOS_MOD =20 u L=1 u PMOS
23

35
 Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 6

24

25 C1 Y 0 1 p
26
27

28

29

30

31

32

33

6.3.3 Effect of W/L Ratio Variation

Listing 6.3: Task-3: Effect of W/L Ratio Variation

1 * 2:1 M ultiple xe r with W/ L Ratio Variation
2 . include " Model_ file . txt" ; Inc lude NMOS and PMOS models
3

4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply
6

7 * Input signals
8 VA A 0 PULSE (0 5 0 1 n 1 n 50 n 100 n) ; Input A
9 VB B 0 PULSE (0 5 25 n 1 n 1 n 50 n 100 n) ; Input B
10 VS S 0 PULSE (0 5 0 1 n 1 n 100 n 200 n) ; Select signal
11

12 * Inverter for Select signal

13 M1 Sbar S Vdd Vdd PMOS_MOD W =10 u L=1 u
14 M2 Sbar S 0 0 NMOS_MOD W=5 u L=1 u
15

16 * Transm iss ion Gate for Input A ( conducts when S=1)

17 M3 A S Y 0 NMOS_MOD W={ wn} L=1 u ; NMOS with variable width
18 M4 A Sbar Y Vdd PMOS_MOD W ={2* wn} L=1 u ; PMOS with variable width
19

20 * Transm iss ion Gate for Input B ( conducts when S=0)

21 M5 B Sbar Y 0 NMOS_MOD W={ wn} L=1 u ; NMOS with variable width
22 M6 B S Y Vdd PMOS_MOD W ={2* wn} L=1 u ; PMOS with variable width
23

24 * Output load
25 C1 Y 0 1 p ; Output load capacitance
26

27 * Transient analysis
28 . tran 0.1 n 400 n ; Simulate for 400 ns with a 0.1 ns step
29 . step param wn list 5 u 10 u 20 u ; W/ L ratio variations
30 . print tran V( A) V( B) V( S) V( Y) ; Print signals
31 . measure tran tpd_HL_a trig V( S) val =2.5 rise =1 targ V( Y) val =2.5 fall
=1 ; S=1 to Y transition
32 . measure tran tpd_LH_a trig V( S) val =2.5 fall =1 targ V( Y) val =2.5 rise
=1 ; S=0 to Y transition
33 . end

6.3.4 Effect of Load Capacitance Variation

36
 Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 6

Listing 6.4: Task-4: Effect of Load Capacitance Variation

1

2
3

5 VDD Vdd 0 DC 5
6

8 A
9 B
10

11

12

13 M1 Sbar S Vdd Vdd PMOS_MOD =10 u L=1 u

14 M2 Sbar S 0 0 NMOS_MOD W=5 u L=1 u
15

16 when
17 A S Y 0 NMOS_MOD =10 u L=1 u
18 A Y Vdd PMOS_MOD =20 u u
19

20
21 B Sbar Y 0 NMOS_MOD =10 u L=1 u
22 B S Y Vdd =20 u L=1 u
23

24
25

26

27

28

29
30

31

32

33

6.3.5 Effect of Temperature Variation

Listing 6.5: Task-5: Effect of Temperature Variation

1 * 2:1 M ult iplex e r with Te m pe rat ure Variation
2 . include " Model_ file . txt" ; Include NMOS and PMOS models
3

4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply
6

7 * Input signals
8 VA A 0 PULSE (0 5 0 1 n 1 n 50 n 100 n) ; Input A
9 VB B 0 PULSE (0 5 25 n 1 n 1 n 50 n 100 n) ; Input B
10 VS S 0 PULSE (0 5 0 1 n 1 n 100 n 200 n) ; Select signal
11

12 * Inve rte r for Select signal

13 M1 Sbar S Vdd Vdd PMOS_MOD W =10 u L=1 u
14 M2 Sbar S 0 0 NMOS_MOD W=5 u L=1 u
15

37
 Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 6

16

17 M3 A S Y 0 NMOS_MOD =10 u L=1 u NMOS

18 M4 A Sbar Y Vdd PMOS_MOD =20 u L=1 u PMOS
19

20 B when
21 M5 B 0 NMOS_MOD =10 u u
22 M6 B S Y Vdd PMOS_MOD =20 u L=1 u
23
24

25 C1 Y 0 1 p
26

27

28
29

30

31

32

33

6.4 Result
6.4.1 Basic Functionality Verification

Listing 6.6: Multiplexer Functionality Verification

1 A B
2

6
7

6.4.2 Effect of Supply Voltage on Propagation Delay

Listing 6.7: Supply Voltage Effect Analysis

1 Supply Voltage ( V) tpd_LH ( ns) tpd_HL ( ns) Averag
2 3 2.76 2.62 2.69
3 5 1.94 1.83 1.89
4 7 1.58 1.47 1.53
5

10

38
Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 6

6.5 Observation
• The 2:1 multiplexer using transmission gates successfully routes the selected input
signal to the output based on the control signal S.

• Transmission gates provide full voltage swing at the output without the threshold
voltage drop that would occur with single-transistor pass gates.

• The complementary control signals (S and Sbar) ensure that only one transmission
path is active at any time, preventing signal contention.

• Supply voltage has a significant impact on propagation delay, with higher voltages
resulting in faster switching speeds.

• Increasing the W/L ratio of the transistors improves switching speed by reducing
the on-resistance of the transmission gates, but with diminishing returns.

• Load capacitance has a direct linear relationship with propagation delay, as

expected from RC time constant analysis.

• Temperature increase degrades circuit performance by increasing propagation delay

due to reduced carrier mobility.

• The circuit demonstrates good noise margins and signal integrity across various
operating conditions.

• Transmission gate-based multiplexers offer an excellent compromise between

performance, power consumption, and area efficiency compared to other
multiplexer implementations.

Figure 6.1: 2:1 Multiplexer Basic Operation Waveforms

39
Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 6

Figure 6.2: Effect of Supply Voltage Variation on Sum

Figure 6.3: Effect of Supply Voltage Variation on Carry

40