SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

D Dependable Texas Instruments Quality and SN5404 . . . J PACKAGE

Reliability SN54LS04, SN54S04 . . . J OR W PACKAGE
SN7404, SN74S04 . . . D, N, OR NS PACKAGE
SN74LS04 . . . D, DB, N, OR NS PACKAGE
(TOP VIEW)
description/ordering information
These devices contain six independent inverters. 1A 1 14 VCC
1Y 2 13 6A
2A 3 12 6Y
2Y 4 11 5A
3A 5 10 5Y
3Y 6 9 4A
GND 7 8 4Y

SN5404 . . . W PACKAGE
(TOP VIEW)

1A 1 14 1Y
2Y 2 13 6A
2A 3 12 6Y
VCC 4 11 GND
3A 5 10 5Y
3Y 6 9 5A
4A 7 8 4Y

SN54LS04, SN54S04 . . . FK PACKAGE

(TOP VIEW)

VCC
NC
1Y
1A

6A
3 2 1 20 19
2A 4 18 6Y
NC 5 17 NC
2Y 6 16 5A
NC 7 15 NC
3A 8 14 5Y
9 10 11 12 13
3Y

4Y
4A
GND
NC

NC − No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

     !"   #!$% &"' Copyright  2004, Texas Instruments Incorporated
&!   #" #" (" "  ") !"  #&! #%  - ./.010 %% #"" " ""&
&& *+' &! #", &"  ""%+ %!&" !%" ("*" "&'  %% (" #&! #&!
",  %% #""' #", &"  ""%+ %!&" ",  %% #""'

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1













  

SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
Tube SN7404N SN7404N
PDIP − N Tube SN74LS04N SN74LS04N
Tube SN74S04N SN74S04N
Tube SN7404D
7404
Tape and reel SN7404DR
Tube SN74LS04D
SOIC − D LS04
0°C
0 C to 70
70°C
C Tape and reel SN74LS04DR
Tube SN74S04D
S04
Tape and reel SN74S04DR
Tape and reel SN7404NSR SN7404
SOP − NS Tape and reel SN74LS04NSR 74LS04
Tape and reel SN74S04NSR 74S04
SSOP − DB Tape and reel SN74LS04DBR LS04
Tube SN5404J SN5404J
Tube SNJ5404J SNJ5404J
Tube SN54LS04J SN54LS04J
CDIP − J
Tube SN54S04J SN54S04J
Tube SNJ54LS04J SNJ54LS04J
−55°C
−55 C to 125
125°C
C Tube SNJ54S04J SNJ54S04J
Tube SNJ5404W SNJ5404W
CFP − W Tube SNJ54LS04W SNJ54LS04W
Tube SNJ54S04W SNJ54S04W
Tube SNJ54LS04FK SNJ54LS04FK
LCCC − FK
Tube SNJ54S04FK SNJ54S04FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.

FUNCTION TABLE
(each inverter)
INPUT OUTPUT
A Y
H L
L H

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265













  

SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

logic diagram (positive logic)

1A 1Y

2A 2Y

3A 3Y

4A 4Y

5A 5Y

6A 6Y

Y=A

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3













  

SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

schematics (each gate)

’04
VCC

4 kΩ 1.6 kΩ 130 Ω

Input A

Output Y

1 kΩ

GND

’LS04 ’S04
VCC VCC

20 kΩ 8 kΩ 120 Ω 2.8 kΩ 50 Ω
900 Ω

Input
A 3.5 kΩ Output
Input 4 kΩ Output Y
A Y

12 kΩ
250 Ω
500 Ω
3 kΩ
1.5 kΩ

GND

GND

Resistor values shown are nominal.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265













  

SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI: ’04, ’S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
’LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN5404 SN7404
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current −0.4 −0.4 mA
IOL Low-level output current 16 16 mA
TA Operating free-air temperature −55 125 0 70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN5404 SN7404
PARAMETER TEST CONDITIONS‡ UNIT
MIN TYP§ MAX MIN TYP§ MAX
VIK VCC = MIN, II = − 12 mA −1.5 −1.5 V
VOH VCC = MIN, VIL = 0.8 V, IOH = −0.4 mA 2.4 3.4 2.4 3.4 V
VOL VCC = MIN, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V
II VCC = MAX, VI = 5.5 V 1 1 mA
IIH VCC = MAX, VI = 2.4 V 40 40 µA
IIL VCC = MAX, VI = 0.4 V −1.6 −1.6 mA
IOS¶ VCC = MAX −20 −55 −18 −55 mA
ICCH VCC = MAX, VI = 0 V 6 12 6 12 mA
ICCL VCC = MAX, VI = 4.5 V 18 33 18 33 mA
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ All typical values are at VCC = 5 V, TA = 25°C.
¶ Not more than one output should be shorted at a time.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5













  

SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)

SN5404
FROM TO SN7404
PARAMETER TEST CONDITIONS UNIT
(INPUT) (OUTPUT)
MIN TYP MAX
tPLH 12 22
A Y RL = 400 Ω, CL = 15 pF ns
tPHL 8 15

recommended operating conditions (see Note 3)

SN54LS04 SN74LS04
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current −0.4 −0.4 mA
IOL Low-level output current 4 8 mA
TA Operating free-air temperature −55 125 0 70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN54LS04 SN74LS04
PARAMETER TEST CONDITIONS† UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
VIK VCC = MIN, II = − 18 mA −1.5 −1.5 V
VOH VCC = MIN, VIL = MAX, IOH = −0.4 mA 2.5 3.4 2.7 3.4 V
IOL = 4 mA 0.25 0.4 0.4
VOL VCC = MIN, VIH = 2 V V
IOL = 8 mA 0.25 0.5
II VCC = MAX, VI = 7 V 0.1 0.1 mA
IIH VCC = MAX, VI = 2.7 V 20 20 µA
IIL VCC = MAX, VI = 0.4 V −0.4 −0.4 mA
IOS§ VCC = MAX −20 −100 −20 −100 mA
ICCH VCC = MAX, VI = 0 V 1.2 2.4 1.2 2.4 mA
ICCL VCC = MAX, VI = 4.5 V 3.6 6.6 3.6 6.6 mA
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2)

SN54LS04
FROM TO SN74LS04
PARAMETER TEST CONDITIONS UNIT
(INPUT) (OUTPUT)
MIN TYP MAX
tPLH 9 15
A Y RL = 2 kΩ, CL = 15 pF ns
tPHL 10 15

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265













  

SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

recommended operating conditions (see Note 3)

SN54S04 SN74S04
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current −1 −1 mA
IOL Low-level output current 20 20 mA
TA Operating free-air temperature −55 125 0 70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN54S04 SN74S04
PARAMETER TEST CONDITIONS† UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
VIK VCC = MIN, II = − 18 mA −1.2 −1.2 V
VOH VCC = MIN, VIL = 0.8 V, IOH = −1 mA 2.5 3.4 2.7 3.4 V
VOL VCC = MIN, VIH = 2 V, IOL = 20 mA 0.5 0.5 V
II VCC = MAX, VI = 5.5 V 1 1 mA
IIH VCC = MAX, VI = 2.7 V 50 50 µA
IIL VCC = MAX, VI = 0.5 V −2 −2 mA
IOS§ VCC = MAX −40 −100 −40 −100 mA
ICCH VCC = MAX, VI = 0 V 15 24 15 24 mA
ICCL VCC = MAX, VI = 4.5 V 30 54 30 54 mA
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)

SN54S04
FROM TO SN74S04
PARAMETER TEST CONDITIONS UNIT
(INPUT) (OUTPUT)
MIN TYP MAX
tPLH 3 4.5
A Y RL = 280 Ω, CL = 15 pF ns
tPHL 3 5
tPLH 4.5
A Y RL = 280 Ω, CL = 50 pF ns
tPHL 5

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SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

PARAMETER MEASUREMENT INFORMATION

SERIES 54/74 AND 54S/74S DEVICES
VCC
Test RL
Test Point S1
Point VCC
From Output
VCC Under Test (see Note B)
RL CL
From Output RL (see Note A) 1 kΩ
Under Test (see Note B) From Output Test
CL Under Test Point
(see Note A) CL
(see Note A) S2

LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS

3V
High-Level Timing
Pulse 1.5 V 1.5 V Input 1.5 V
0V
tw th
tsu
3V
Low-Level 1.5 V 1.5 V Data
1.5 V 1.5 V
Pulse Input
0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATIONS SETUP AND HOLD TIMES

Output 3V
Control
(low-level 1.5 V 1.5 V
3V
Input 1.5 V 1.5 V enabling) 0V
0V tPZL tPLZ

tPLH tPHL
Waveform 1 ≈1.5 V
In-Phase VOH (see Notes C 1.5 V
Output 1.5 V 1.5 V and D) VOL + 0.5 V
(see Note D) VOL
VOL
tPZH tPHZ
tPHL tPLH
VOH
Out-of-Phase VOH Waveform 2 VOH − 0.5 V
(see Notes C 1.5 V
Output 1.5 V 1.5 V ≈1.5 V
(see Note D) and D)
VOL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series
54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time, with one input transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265













  

SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

PARAMETER MEASUREMENT INFORMATION

SERIES 54LS/74LS DEVICES
VCC
Test RL
Test Point S1
Point VCC
From Output
VCC Under Test (see Note B)
RL CL
From Output RL (see Note A) 5 kΩ
Under Test (see Note B) From Output Test
CL Under Test Point
(see Note A) CL
(see Note A) S2

LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS

3V
High-Level Timing
Pulse 1.3 V 1.3 V Input 1.3 V
0V
tw th
tsu
3V
Low-Level 1.3 V 1.3 V Data
1.3 V 1.3 V
Pulse Input
0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATIONS SETUP AND HOLD TIMES

Output 3V
Control
(low-level 1.3 V 1.3 V
3V
Input enabling)
1.3 V 1.3 V 0V
0V tPZL tPLZ

tPLH tPHL
Waveform 1 ≈1.5 V
In-Phase VOH 1.3 V
(see Notes C
Output 1.3 V 1.3 V VOL + 0.5 V
and D)
(see Note D) VOL VOL
tPZH tPHZ
tPHL tPLH
VOH
Out-of-Phase Waveform 2 VOH − 0.5 V
VOH
Output (see Notes C 1.3 V
1.3 V 1.3 V
and D) ≈1.5 V
(see Note D) VOL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time, with one input transition per measurement.

Figure 2. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

 PACKAGE OPTION ADDENDUM

www.ti.com 1-May-2025

PACKAGING INFORMATION

Orderable Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
part number (1) (2) (3) Ball material Peak reflow (6)
(4) (5)

JM38510/00105BCA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/
00105BCA
JM38510/00105BDA Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/
00105BDA
JM38510/07003BCA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/
07003BCA
JM38510/07003BDA Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/
07003BDA
JM38510/30003B2A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/
30003B2A
JM38510/30003BCA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/
30003BCA
JM38510/30003BDA Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/
30003BDA
JM38510/30003SCA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/
30003SCA
SN5404J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN5404J
SN54LS04J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54LS04J
SN54S04J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54S04J
SN7404D Obsolete Production SOIC (D) | 14 - - Call TI Call TI 0 to 70 7404
SN7404DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 7404
SN7404N Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 SN7404N
SN74LS04D Active Production SOIC (D) | 14 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LS04
SN74LS04DBR Active Production SSOP (DB) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM - LS04
SN74LS04DG4 Active Production SOIC (D) | 14 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LS04
SN74LS04DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LS04
SN74LS04DRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LS04
SN74LS04N Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 SN74LS04N
SN74LS04NSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 74LS04
SN74S04D Obsolete Production SOIC (D) | 14 - - Call TI Call TI 0 to 70 S04
SN74S04DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 S04

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 1-May-2025

Orderable Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
part number (1) (2) (3) Ball material Peak reflow (6)
(4) (5)

SN74S04N Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 SN74S04N
SN74S04NSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 74S04
SNJ5404J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ5404J
SNJ5404W Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ5404W
SNJ54LS04FK Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ54LS
04FK
SNJ54LS04J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ54LS04J
SNJ54LS04W Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ54LS04W
SNJ54S04FK Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ54S
04FK
SNJ54S04J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ54S04J
SNJ54S04W Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ54S04W

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without
limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available
for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the
finish value exceeds the maximum column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per
JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the
previous line and the two combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 1-May-2025

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN5404, SN54LS04, SN54LS04-SP, SN54S04, SN7404, SN74LS04, SN74S04 :

• Catalog : SN7404, SN74LS04, SN54LS04, SN74S04

• Military : SN5404, SN54LS04, SN54S04
• Space : SN54LS04-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Apr-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN7404DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LS04DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74LS04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LS04NSR SOP NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LS04NSR SOP NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74S04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74S04NSR SOP NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Apr-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN7404DR SOIC D 14 2500 356.0 356.0 35.0
SN74LS04DBR SSOP DB 14 2000 356.0 356.0 35.0
SN74LS04DR SOIC D 14 2500 356.0 356.0 35.0
SN74LS04NSR SOP NS 14 2000 353.0 353.0 32.0
SN74LS04NSR SOP NS 14 2000 356.0 356.0 35.0
SN74S04DR SOIC D 14 2500 356.0 356.0 35.0
SN74S04NSR SOP NS 14 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Apr-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
JM38510/00105BDA W CFP 14 25 506.98 26.16 6220 NA
JM38510/07003BDA W CFP 14 25 506.98 26.16 6220 NA
JM38510/30003B2A FK LCCC 20 55 506.98 12.06 2030 NA
JM38510/30003BDA W CFP 14 25 506.98 26.16 6220 NA
M38510/00105BDA W CFP 14 25 506.98 26.16 6220 NA
M38510/07003BDA W CFP 14 25 506.98 26.16 6220 NA
M38510/30003B2A FK LCCC 20 55 506.98 12.06 2030 NA
M38510/30003BDA W CFP 14 25 506.98 26.16 6220 NA
SN7404N N PDIP 14 25 506 13.97 11230 4.32
SN7404N N PDIP 14 25 506 13.97 11230 4.32
SN7404NE4 N PDIP 14 25 506 13.97 11230 4.32
SN7404NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74LS04D D SOIC 14 50 506.6 8 3940 4.32
SN74LS04DG4 D SOIC 14 50 506.6 8 3940 4.32
SN74LS04N N PDIP 14 25 506 13.97 11230 4.32
SN74LS04N N PDIP 14 25 506 13.97 11230 4.32
SN74LS04NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74LS04NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74S04N N PDIP 14 25 506 13.97 11230 4.32
SN74S04N N PDIP 14 25 506 13.97 11230 4.32
SN74S04NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74S04NE4 N PDIP 14 25 506 13.97 11230 4.32
SNJ5404W W CFP 14 25 506.98 26.16 6220 NA
SNJ54LS04FK FK LCCC 20 55 506.98 12.06 2030 NA
SNJ54LS04W W CFP 14 25 506.98 26.16 6220 NA
SNJ54S04FK FK LCCC 20 55 506.98 12.06 2030 NA

Pack Materials-Page 3
 PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1

8.75 2X
8.55 7.62
NOTE 3

7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE

0.25
0 -8 1.27 0.10
0.40

DETAIL A
TYPICAL

4220718/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(R0.05)
TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220718/A 09/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(5.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4220718/A 09/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DB0014A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
PLANE
12X 0.65
14
1

2X
6.5
3.9
5.9
NOTE 3

7
8 0.38
14X
0.22
0.15 C A B
5.6
B
5.0
NOTE 4

0.25
0.09

SEE DETAIL A
2 MAX
0.25
GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4220762/A 05/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

1 (R0.05) TYP

14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220762/A 05/2024
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220762/A 05/2024
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
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