50 MUST KNOW

STATIC TIMING ANALYSIS

INTERVIEW QUESTIONS
Practical, Theoretical & Tool-Level Questions
For VLSI Engineers to land in their Dreams Companies

Prasanthi Chanda
1.What is Setup Time Violation?
Company: Synopsys, Qualcomm

Setup time is the minimum duration for which data must remain
stable before the active clock edge arrives at a flip-flop.
A setup time violation happens when data reaches the flip-flop too
late, i.e., after the required setup time window.
This can result in incorrect data being captured, leading to
functional errors.
Setup violations typically occur due to high path delay in the
combinational logic between two flip-flops.
Timing tools check the maximum delay along a path to detect setup
violations.
Fixes include:
Reducing logic depth
Adding buffers to balance delay
Cell upsizing or restructuring the logic

2. What is Clock Skew and how does it impact Setup and Hold Timing?
Company: Intel, Texas Instruments

Clock skew is the difference in clock arrival time at the launching

and capturing flip-flops of a data path.
If the clock arrives late at the destination, it's called positive skew; if
it arrives early, it’s called negative skew.
Positive skew can relax setup time requirements but may cause hold
violations.
Negative skew does the opposite: it tightens setup timing but can
help with hold timing.
Excessive skew can create both setup and hold issues on the same
path.
 Skew arises from imbalanced clock routing, varying buffer delays, or
inconsistent load capacitance.
Fix strategies include:
Using Clock Tree Synthesis (CTS) to balance skew
Applying clock buffering
Leveraging useful skew to intentionally adjust timing paths

3. A path is showing a Setup Violation. How will you debug and fix it?
Company: Apple, Broadcom

First, identify the violating path using STA reports (report_timing in

PrimeTime).
Check the startpoint and endpoint flip-flops, and trace the data
path.
Examine the combinational logic delay between the flip-flops.
Analyze the clock arrival times to check for excessive clock skew or
latency.
Check for high fan-out nets, weak drive strengths, or long wire
delays.
Apply fixes such as:
Buffer insertion to reduce net delay
Cell upsizing for faster transitions
Logic restructuring to reduce path depth

4. What is Hold Time Violation? How is it different from Setup

Violation?
Company: Apple, Broadcom

Hold time is the minimum time data must be stable after the clock
edge to be correctly latched.
A hold violation occurs when data changes too soon after the clock
edge, before the latch captures it.
 This is a min delay violation, unlike setup which is a max delay
violation.
Hold violations are mostly due to fast paths, like:
Short logic paths
Strong driving cells
Low-capacitance nets
Fixes include:
Inserting delay buffers in the data path
Cell downsizing to slow down logic transitions

5. How do you fix a Setup Violation?

Company: Nvidia, MediaTek

Identify Violating Timing

Path

Check Path Delay:

Cell Delays + Net

Apply Fixes:
Upsize cell, Add buffers,
Shorten path

Clock Path Tuning:

Skew Optimization

Re-run STA & Verify

Timing Closure

Physical Verification:
Ensure no DRC/EM issues
6.What is Static Timing Analysis (STA), and how is it different from
Dynamic Timing Simulation?
Company: ARM, Texas Instruments

STA (Static Timing Analysis)

Analyzes timing of a digital circuit without applying vectors.
Works on cell delays + interconnect delays using worst/best case
conditions.
Checks for setup, hold, recovery, and removal violations.
Uses constraints like clock definitions, false paths, and multicycle
paths.
Dynamic Simulation
Uses real input vectors to simulate timing behavior.
Captures functionality + timing using RTL or gate-level testbenches.
Time-consuming and vector-dependent — may miss corner cases.
Key Difference:
STA is fast, corner-based and exhaustive for timing; dynamic sim
checks functionality but is limited by vector coverage.

7. What percentage of STA issues arise from each category in a real

design?
Company: Qualcomm, Synopsys

Constraints Errors
10%
Clock Skew/Jitter
10%
Setup Violations
40%

Crosstalk/Noise
15%

Hold Violations
25%
8.What is the Importance of Matching in Analog Layout Design?
Company: Marvell, Texas Instruments

Parameter Setup Violation Hold Violation

Data arrives after Data changes too

Definition
the setup window soon after clock
d
Maximum delay Minimum delay
Type of Check
check check

Occurs When Data path is too slow Data path is too fast

Buffer insertion, path Delay buffers,

Common Fixes
restructuring downsizing cells

Setup uses Hold uses zero-delay

Clock Consideration
propagated clock clock

STA Focus Late data arrival Early data arrival

Can cause incorrect Can overwrite

Impact
latch data previous data

9. What are the main components of a timing path in STA?

Company: Apple, Qualcomm

Components of a Timing Path:

1.Launch Clock Edge
The clock edge that triggers data launch from the source flip-flop.
2.Data Path Delay
Includes cell delays (e.g., combinational logic) + net delays (wire
delays).
3. Capture Clock Edge
The clock edge at the destination flip-flop that captures the data.
10. At what stages of the design flow is STA performed?
Company: Intel, Cadence

RTL Design

Pre-CTS STA
▸ Based on ideal clocks
▸ Helps estimate early timing violations

Post-CTS STA
▸ Real clock tree inserted
▸ Clock skew + propagation delay now
considered

Post-Route STA
▸ Net parasitics extracted
▸ Final delay and setup/hold checks done

Signoff STA
▸ With final parasitics + extracted RC
▸ Checks done across PVT corners + on-chip
variation
▸ Final decision for timing closure

11. You see a negative setup slack in STA. How do you debug it?
Company: Synopsys, Qualcomm

Debug Checklist:
1.Path Type: Is it a real, false, or multicycle path?
→ False/multicycle paths can be ignored or relaxed.
2. High Cell Delay?
→ Replace slow gates or logic cones with faster cells (cell resizing).
3. Long Net Delay?
→ Check for long wires, routing congestion → fix with buffer insertion.
4. Clock Skew?
→ If capture clock arrives earlier than launch clock, try clock tree
balancing.
5. Wrong Constraints?
→ Check if the path is constrained correctly using SDC (setup, hold,
etc.).

12. What is the purpose of false paths and multicycle paths in STA?
Company: Apple, Samsung

False Path Multicycle Path

Path that needs more than 1

Path that does not require
clock cycle to complete data
timing check.
transfer.

Used for test/control logic

Common in slow control logic
paths that don’t switch every
or handshake paths.
cycle.

Set using set_multicycle_path

Tells STA to ignore this path.
command.

13. What’s the meaning of ‘Slack’ in STA? How is it calculated?

Company: AMD, TSMC

Slack = Required Time – Arrival Time

Setup Slack (Worst-case delay):
Ensures data arrives before the capture clock edge.
Formula:
Setup Slack = (T_clock + Setup Time) – (Data Delay + Launch Clock
Delay)

Hold Slack (Best-case delay):

Ensures data doesn’t arrive too early, causing race conditions.
Formula:
Hold Slack = (Data Delay + Launch Clock Delay) – (Hold Time + Capture
Clock Delay)

Positive Slack = Good (no violation)

Negative Slack = Violation (needs fix)

14. Compare Setup vs Hold Timing Checks in STA

Company: Intel, MediaTek

Aspect Setup Timing Hold Timing

Maximum delay Minimum delay

Check Type
check check

Ensures data arrives Ensures data doesn’t

When Checked
before capture clock arrive too early

Required - Arrival Arrival (min) -

Slack Formula
(max) Required

Slow logic, long data Fast logic, short net

Violation Cause
path delay, skew issues

Resize cells, buffer Increase clock path

Fixing Technique
insertion, pipelining delay

High frequency Low skew and

Critical for
designs functional
15. What is Crosstalk in STA and how is it analyzed?
Company: Apple, Qualcomm

Crosstalk is unwanted interference caused by switching activity on

nearby nets (aggressors) impacting a victim net.
It can introduce extra delay (crosstalk delay) or unintended
transitions (crosstalk glitch).
Analyzed using: Noise-aware STA tools like Primetime-SI, Tempus,
which simulate coupling capacitance impact.
Two key effects:
Crosstalk delay → changes timing paths (adds to setup/hold
analysis).
Crosstalk glitch → may cause functional failures if glitches are
captured.

16. What are Clock Gating Checks in STA? Why are they important?
Company: AMD, Broadcom

Clock gating is used to save power by turning off clock to parts of the
circuit when not needed.
In STA, tools perform clock gating checks to ensure:
No glitches pass through gating logic.
Enable signal transitions are timed properly.
It include:
Setup/Hold checks on enable paths.
Glitch detection at AND/OR gates used for gating.
Improper clock gating can cause:
Glitchy clocks → leading to false triggering of flops.
Hold/setup violations due to enable signal misalignment.
17. What is the role of Liberty (.lib) files in STA?
Company: ARM, Synopsys

Liberty files (.lib) define standard cell timing, power, and

functionality.
They are used by STA tools to calculate the delay and transition of
signals in the netlist.
Every standard cell has defined timing arcs (like cell_rise, cell_fall,
rise_transition, etc.) for various input/output conditions.
Delay is a function of:
Input transition (slew rate)
Output load (fanout or capacitance)
These files also include:
Setup/Hold timing
Constraints (max transition, max capacitance)
Power models
Tools like Primetime and Tempus use .lib to simulate delays under
different PVT corners.
Having accurate .lib is critical for reliable STA across multiple
scenarios.

18. Explain Timing Arcs and Types in STA

Company: Samsung, Microchip

Timing arcs represent how signals propagate through cells — from

input pins to output pins.
Each arc defines a delay (or constraint) between an input and output
or between two pins.
Two major types:
Data Arcs: Describe combinational delays (e.g., NAND2: A → Y, B → Y).
Constraint Arcs: Represent setup, hold, recovery, removal
requirements (e.g., D to Q with respect to CLK).
 Timing arcs are library-defined, and used to build the timing graph of
the design.
STA tools use these arcs to perform path-based delay calculation.
For sequential elements (flops, latches), constraint arcs play a vital
role in launch-capture analysis.
Arcs can be conditional (based on functionality) and are non-linear,
requiring interpolation across .lib tables.

19. What is Noise Modeling in STA and why is it important?

Company: Intel, Cadence

In modern STA, Noise Modeling refers to the simulation of unwanted

signal activity (like crosstalk or switching noise) affecting timing
accuracy.
This is especially important in deep submicron nodes where coupling
capacitance and aggressor-victim effects are significant.
Noise can:
Alter signal delay (making paths slower or faster).
Introduce false transitions (glitches).
Cause functional errors if glitches are captured by flip-flops.

20. What is the difference between NLDM and CCS delay models?
Company: MediaTek, Renesas

NLDM (Non-Linear Delay Model):

Traditional model used in .lib files.
Delay and transition are modeled using 2D lookup tables based on
input slew and output load.
Easy to implement, faster in computation.
Not accurate in advanced nodes due to non-linear effects,
especially with coupling.
CCS (Composite Current Source) Model:
Advanced model that captures waveform shape and current flow.
Provides more accurate delay and noise analysis, especially for
crosstalk and multi-input switching.
Requires detailed waveform-aware simulation, leading to higher
runtime but better correlation with SPICE.
CCS is now standard for signoff at 7nm and below, while NLDM is still
used for preliminary timing closure.

21. What is Multi-Voltage Domain Timing Analysis in STA?

Company: Synopsys, Qualcomm

Multi-voltage design uses different voltage levels across blocks to reduce

power.
In STA, this introduces complexity due to:
Timing violations when signals travel between different voltage
domains.
Delay variation caused by voltage differences.
STA tools must ensure:
Correct timing across voltage domains.
Level shifters are inserted and functional.
Power intent files (UPF/CPF) are correctly interpreted.

22. What are Isolation Cells and How Are They Verified in STA?
Company: Intel, Marvell

Isolation cells protect powered-off domains from corrupting the

powered-on logic.
They are inserted at domain boundaries and control what logic is
passed during power-down states.
These cells usually output a fixed logic value (0 or 1) when the
domain is OFF.
 Isolation cells protect powered-off domains from corrupting the
powered-on logic.
They are inserted at domain boundaries and control what logic is
passed during power-down states.
These cells usually output a fixed logic value (0 or 1) when the domain
is OFF.

23. What are the common causes of setup and hold violations in STA?
Company: Synopsys, AMD

Setup violation occurs when data arrives after the setup window
closes.
Hold violation happens when data arrives too early, before the hold
window.
Common causes include:
Unbalanced clock skew
Long combinational logic paths
High fanout or poor placement
Incorrect constraints or missing false/multicycle path definitions
Improper buffer sizing or over-optimization during synthesis
Fixing Setup: Optimize logic, upsize cells, buffer nets, reduce path
delay.
Fixing Hold: Insert buffers to delay data, adjust clock tree, or modify
constraints

24. What is Negative Slack? How do you fix it?

Company: Intel, Marvell

Negative Slack means the timing path is violating its required time.
Setup Slack = Required Time – Arrival Time → if < 0 → Setup violation.
Hold Slack = Arrival Time – Required Time → if < 0 → Hold violation.
 To fix negative setup slack:
Reduce logic depth
Use faster cells
Optimize net delays
To fix negative hold slack:
Add buffers or delay cells
Tweak clock tree to delay data

25. What is the flow to fix a Setup Violation?

Company: Synopsys, Samsung

Setup Slack < 0?

1. Recheck SDC
• Wrong constraints?

2. Logic Optimization
• Reduce logic depth Loop if
not fixed
3. Cell Resizing
• Use higher drive

4. Buffer Insertion
• Cut long nets

5. Floorplan Changes
• Better placement
26. What is the flow to fix a Hold Violation?
Company: Apple, NVIDIA

Hold Slack < 0?

1. Recheck Clock Skew

• Is clock reaching too
early?

2. Add Delay Elements

• Insert delay cells/buffers

3. Use Hold Fixing Cells

• High delay buffers

4. Adjust Clock Routing

• Delay launch clock

27. How does Process-Voltage-Temperature (PVT) variation impact

STA signoff?
Company: Apple, Texas Instruments

PVT corners represent variations in process (fast/slow), voltage levels,

and temperature across silicon.
STA is done across multiple PVT corners to ensure timing holds in
best-case and worst-case environments.
Effects:
Process: Fast corner shortens delays, may cause hold violations;
slow corner stretches delays, may cause setup violations.
Voltage: Lower voltage increases delay; higher voltage reduces
delay but may cause hold issues.
 Voltage: Lower voltage increases delay; higher voltage reduces
delay but may cause hold issues.
Temperature: Higher temperature → slower transistors, worse
setup timing.
Common corners: SS, FF, TT, SF, FS, each with specified voltage and
temperature.
Timing libraries (.lib) are provided for each PVT corner.
STA tools analyze each corner independently and report violations.
Signoff is accepted only when timing is clean across all PVT scenarios.

28. What is Clock Uncertainty in STA and how is it modeled?

Company: MediaTek, Marvell

Clock Uncertainty accounts for inaccuracies in clock edge arrival due to

multiple factors.
Components:
Jitter – Random variation due to PLLs, oscillators
Skew – Design-related delay mismatch between launch and
capture clocks
Margin – Safety buffer added by designers
STA models uncertainty by reducing the effective clock period
available for data to propagate.
Setup Uncertainty is subtracted from the launch-to-capture window.
Hold Uncertainty is added to the hold requirement, making the
timing window tighter.
Clock uncertainty can vary across corners, modes, and domains.
Over-conservative uncertainty can reduce performance, while
underestimation leads to timing failures.
29. How are Integrated Clock Gating (ICG) cells handled in Static
Timing Analysis?
Company: ARM, Synopsys

ICG cells are special clock gating elements used to reduce dynamic
power by disabling the clock to inactive logic blocks.
STA must verify both functional and timing correctness across enable
transitions.
Constraints used:
set_clock_gating_check -setup 0.1 -hold 0.05 [get_clocks clk]
Synthesis tools insert ICG cells with enable logic; STA must trace the
gating enable logic cone to analyze properly.
Clock gating checks are included in timing reports and signoff flows.
Misconfigured ICG paths can result in false negatives or positives in
STA reports.

30. What is the significance of Input/Output (IO) constraints in STA for

top-level timing closure?
Company: Broadcom, Infineon

IO constraints define the timing relationship between internal clocks

and external interfaces, critical for chip-level STA.
Types of IO constraints:
set_input_delay – defines max delay allowed from external driver
to input pin
set_output_delay – defines required delay from internal flop to IO
pin
These are specified relative to an external clock coming from the
testbench or another die.
Example constraints:
set_input_delay 1.2 -clock clk [get_ports in_data]
set_output_delay 1.0 -clock clk [get_ports out_data]
31. How are Timing Exceptions like False Paths and Multicycle Paths
handled in STA?
Company: Cadence, Micron

Timing exceptions inform the STA tool to ignore or alter timing checks
on specific paths.
False Path (FP): A path that never functions in real operation and
should be excluded from analysis.
Example: asynchronous control lines or debug/test signals
Constraint:
set_false_path -from [get_clocks clkA] -to [get_clocks clkB]
Multicycle Path (MCP): A path that logically takes more than one clock
cycle to transfer data.
Used for low-speed logic or slow state machines
Constraint:
set_multicycle_path 2 -setup -from X -to Y
set_multicycle_path 1 -hold -from X -to Y
These exceptions override default 1-cycle setup/hold checks.
Improper use may hide real violations, so must be verified by RTL and
functional context.
Reviewed carefully during timing signoff to avoid silicon bugs.

32. How is STA performed on Asynchronous Clock Domains, and what

are the key challenges?
Company: Intel, STMicroelectronics

In designs with multiple unrelated clocks, asynchronous paths occur

between flip-flops controlled by different clock sources.
STA cannot check setup/hold between asynchronous domains reliably
due to lack of phase relationship.
 challenges:
Metastability – receiver flip-flop may latch invalid data
Unknown data transfer time, so setup/hold checks are
meaningless
Solutions:
Use of synchronizers (2-stage flops) for single-bit control signals
Use of FIFO with gray code pointers for multi-bit data

33. Compare different types of STA corners used during timing closure
Company: Intel, STMicroelectronics

Common Use
Type of Corner Description Impact on STA
Case

Slow process, Max delay → Worst-case setup

SS (Slow-Slow)
low V, high T Setup issues check

Fast process, Min delay → Worst-case hold

FF (Fast-Fast)
high V, low T Hold issues check

TT (Typical- Typical process, Functional

Nominal delays
Typical) voltage, temp validation

Mixed fast/slow Path-specific Extra margin

SF / FS
P corners timing paths

Lower voltage Low-power

Low-Voltage Longer delays
than nominal analysis

High- Slower Automotive/Milit

125°C or more
Temperature transistors ary chips
34. What is CRPR (Clock Reconvergence Pessimism Removal) in STA
and why is it important?
Company: AMD, Synopsys

CRPR removes unnecessary pessimism in timing paths that share the

same clock network.
When clock launch and capture paths reconverge, STA tools may
double-count delay, making slack look worse.
CRPR adjusts for shared clock path delays, improving slack accuracy.
Without CRPR, tools assume independent clock delays, adding
pessimism.
Example: Two flops clocked by the same clock but different path
segments — delay difference overestimated.
Helps reduce false violations, especially in deep pipelines or large
SoCs.

35. How does On-Chip Variation (OCV) affect STA, and what is the
difference between AOCV and POCV?
Company: NVIDIA, Samsung

OCV models timing variation across chip regions due to

manufacturing/process differences.
AOCV (Advanced OCV):
Adds variation based on cell location, path depth, and library-specific
tables
More accurate than classic OCV\
POCV (Parametric OCV):
Uses statistical data (sigma-based modeling)
Captures more realistic variation across timing arcs
Allows path-based analysis with tighter margins
Both reduce over-pessimism, helping meet timing with better QoR.
Tools support commands like:
set_ocv_group -name groupA ...
set_aocvm_table -delay ...
set_pocvm_model ...

36. How is Static Timing Analysis handled in hierarchical or block-

based design flows?
Company: Texas Instruments, Broadcom

Large SoCs are divided into blocks/IPs, each analyzed separately.

STA is done at block-level first, then at top-level (full chip).
At block-level:
Use abstract views (black-box or timing models) of other blocks
Apply interface constraints (IO delays, virtual clocks)
Top-level STA:
All blocks combined with top-level routing and real clocks
Re-validate full paths, including block-to-block timing
Enables parallel development of blocks → faster convergence

37. What is Timing Budgeting in STA and how is it used during

floorplanning?
Company: ARM, MediaTek

Timing budgeting splits total available slack among sub-blocks or

stages.
Ensures each block has a target delay to meet full-chip timing
Done early in floorplanning/placement to guide logic distribution
Example:
Total path delay target = 1ns
Stage 1 budget = 0.4ns, Stage 2 = 0.3ns, Stage 3 = 0.3ns
Helps avoid timing bottlenecks in a single stage
Tools support auto budgeting and manual override based on criticality
Command used (in some tools):
set_max_delay -from A -to B 0.4

38. A path is showing a Hold Violation — How do you debug it?

Company: Intel, Synopsys

Start

Check Path Report

▸ Which FFs are involved?
▸ What’s the hold slack?

Analyze Clock Path Delay

▸ Is capture clock too early?
▸ Check launch/capture clock skew

Review Data Path Delay

▸ Too short data path?
▸ Missing delay elements?

Check Library Timing

▸ Cell delays, interconnect
▸ Are liberty (.lib) models OK?

Review Clock Uncertainty

▸ Too much or too little hold margin?

Apply Fixes
▸ Cell delays, inteAdd delay buffers in data path
▸ Change cell sizing
 Re-run STA
▸ Hold violation resolved?

Done

39. What is Crosstalk Noise in STA and how is it analyzed?

Company: Cadence, Micron

Crosstalk is an unwanted coupling between nearby signal nets (aggressor

→ victim).
In STA, it causes:
Noise-induced delay → impacts setup timing.
False transitions on victim nets → can lead to glitches.
Tools calculate crosstalk delay and noise window based on:
Coupling capacitance
Switching direction (same or opposite)
Signal slew and net spacing
Crosstalk-aware STA includes noise analysis for both:
Functional correctness (noise spikes),
Timing closure (delay shifts).
Fixes include shielding nets, spacing critical signals, or buffer
insertion.

40. What is Crosstalk Noise in STA and how is it analyzed?

Company: Intel, MediaTek

Clock Gating Cells (like ICGs) save power by turning off clocks to idle
modules.
They add extra timing arcs that must be validated during STA.
 Tools perform checks between:
Enable signal to gate control logic
Gate control to clock pin
Timing arcs from clock enable to output are crucial to avoid glitches.
Setup/Hold analysis ensures:
Enable signal is stable before the active clock edge.
No glitch propagates to the gated clock.
Constraints are added for gating checks, and synthesis tools usually
infer these paths.

41. What are PVT Corners in STA and why are multiple corners used
for signoff?
Company: Marvell, GlobalFoundries

PVT = Process, Voltage, Temperature — variations that affect

transistor behavior.
Different PVT corners represent worst/best-case conditions:
Slow-Slow (SS): Worst-case speed (low temp/voltage) → used for
setup analysis
Fast-Fast (FF): Fastest transistors (high temp/voltage) → used for
hold analysis
Typical-Typical (TT): Nominal case for general estimation
STA tools run timing checks across multiple PVT corners to ensure
reliability.
Example: A design must pass setup in [email protected]@125°C and hold in
[email protected]@-40°C.
Using multiple corners ensures:
Functional robustness across manufacturing variations.
Signoff readiness for any process condition.
42. How do you debug a Hold Violation in a timing report?
Company: Broadcom, Qualcomm

Hold violation → data is arriving too early at the capture flip-flop.

Common causes:
Short logic path
Minimal data delay
Skewed clock favoring early capture
Debugging Steps:
Run report_timing -delay_type min in STA tool.
Look for clock path delay vs. data path delay.
Check if clock skew is increasing the violation.
If net is too short → insert buffers or de-optimize fast gates.
Final step: Re-run STA and verify Hold Slack ≥ 0 ps.

43. How do you debug a Hold Violation in a timing report?

Company: Renesas, STMicroelectronics

IO timing defines how signals interact with external components at

chip boundaries.
Important for top-level STA where design connects with board-level
logic.
Input constraints use set_input_delay, output with set_output_delay —
both referenced to IO clock.
IO timing affects:
Data setup/hold to/from external devices
Launch/capture alignment with interface clocks
Signoff STA must:
Apply realistic board delays (trace delays, capacitance)
Account for IO buffer delays and pad timing
Common mistake: Ignoring board skew and delay, leading to failed
signoff.
44. What is MMMC (Multi-Mode Multi-Corner) Analysis and why is it
essential for timing signoff?
Company: Samsung, Synopsys

MMMC is the backbone of STA signoff — validates design across:

Multiple functional modes (e.g., functional, test, scan, low-power)
Multiple PVT corners (process, voltage, temperature)
Each mode-corner combo has a unique set of constraints, timing
libraries, and clocks.
Designers create analysis views for each case:
Example:
view: func_SS_0.9V_125C
view: scan_TT_1.0V_25C
STA is performed simultaneously across all views to detect worst-case
delays.
Helps avoid over-design, ensures robust performance, and speeds up
ECO closure.
MMMC = Mode × Corner × Library

45. How is Clock Jitter modeled in STA and what are its types?
Company: Nvidia, Apple

Clock Jitter = Variability in clock edge arrival time

It affects timing margins and must be modeled carefully in STA.
Types of Jitter:
Cycle-to-Cycle Jitter: Variation between two consecutive edges.
Period Jitter: Change in the duration of clock periods.
Phase Jitter: Short-term deviation from ideal phase.
Random Jitter: Noise-induced and unpredictable.
Modeling in STA:
Modeled using set_clock_uncertainty for both setup and hold.
Higher jitter → lower effective timing window.
STA tools use:
Gaussian models for random jitter
Systematic skew margins for deterministic jitter

46. What are Clock Skew Balancing Techniques in STA and why are
they critical?
Company: Qualcomm, Intel

Clock Skew = Difference in arrival time of the clock signal at launching vs.
capturing flip-flop.
Techniques to Balance Skew:
H-Tree / Balanced Clock Trees: Symmetric distribution to reduce skew.
Clock Buffers Insertion: Strategically placed buffers to match delays.
Useful Skew: Intentionally adjusting skew to fix setup/hold violations.
Clock Gating Aware CTS: Ensures gated elements are synchronized.
CRPR (Clock Reconvergence Pessimism Removal): Removes pessimism
caused by common clock paths.
Significance:
High skew leads to timing violations (esp. hold).
Advanced SoCs use skew-aware place & route tools.
Used in low-power and high-frequency chips.

47. How are ECO Fixes applied during STA timing closure?
Company: GlobalFoundries, Cadence

ECO (Engineering Change Order): Late-stage fixes without full re-synthesis.

Common ECO Fix Methods:
Cell Upsizing/Downsizing: Alters drive strength to reduce delay.
Buffer Insertion/Removal: Adjusts path delay or isolation.
 Net Re-routing: Reduces parasitic delay or congestion.
Gate Swapping: Replace logic cells with faster or better-fitting
versions.
Path Splitting: Parallelizes logic to meet timing.
STA Tools Involved:
Primetime ECO, IC Compiler, Tempus ECO, Innovus ECO
Constraints: set_eco_mode, write_script, etc.
ECOs help finalize designs post signoff check, minimizing re-spin and
time-to-market delays.

48. Key SDC Constraints in STA

Company: Synopsys, Analog Devices

Command Used For Example

create_clock -period
create_clock Define clock
10 [get_ports clk]

set_input_delay 2.5 -
set_input_delay Input arrival time
clock clk [get_ports A]

set_output_delay 1.8 -
set_output_delay Output required time
clock clk [get_ports Z]

set_false_path -from A
set_false_path Ignore unused path
-to B

Add cycles for data set_multicycle_path 2

set_multicycle_path
transfer -setup -from A -to B

Add margin for set_clock_uncertainty

set_clock_uncertainty
skew/jitter 0.2 [get_clocks clk]
49. What are Clock Skew Balancing Techniques in STA and why are
they critical?
Company: Synopsys, Apple

Static Timing Analysis (STA) can be approached using two methodologies:

Path-Based and Graph-Based.
Graph-Based STA is the most commonly used technique. It constructs a
timing graph of the circuit and propagates arrival times, required times,
and slacks through the graph using Breadth-First Search or similar
algorithms. It is efficient and ideal for full-chip analysis and floorplan
evaluation.
Path-Based STA, on the other hand, involves evaluating specific timing
paths end-to-end. This approach computes exact slack values by
performing timing analysis only on critical paths. It’s slower but more
accurate and used during final signoff or for debugging violations.
Summary:
Use Graph-Based STA for speed and coverage.
Use Path-Based STA for precision and final checks.

50. What is the role of Derating Factors in STA?

Company: Apple, Qualcomm, AMD

Derating factors adjust delays to model pessimism from variations in

process, voltage, and temperature (PVT).
They are applied to cell delays and net delays during STA.
Types of Derating:
Global Derating: Uniform scaling across the chip.
Path-Based Derating: Different values for launch and capture paths.
AOCV/POCV: Advanced models for variation-aware timing.
Why it's used:
Prevents over-optimistic timing.
Ensures reliable silicon performance.
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