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 Assignment-5
) The maJr fenctions an T/omodele crnel
> Defecina Errora
T/o modeles hve tee abilit to deteot
errors ond repore tern to teeCPU. ohe wn
the paruty bit nnethod.
-S Prrocesor Communealon
The cruhcol fcencion cn T/o module
involve a keew compOnents
O Comand Decoding)
Rececve nd decode ommandt sent
Rromee preocessor.
pata ExChange
Exchanqe Dota between perepherals,
prroceSors nd the min iermon
(W States Reporbing
Commeei'ole te Stabes oß peripherals
to e proceason.
Adoress Decoding)
rraani2es ech tee pereepheral
Connecteo to te T/o module be mCncyang
hei en'oue osoneAses.

7>Bulsering Daba
Dato bfgerine , To moclulex can mncae
te tranlerr Speed ok dat Sent by the' processor
to perepheral devices. This compernsates fo
Hee latentu of periphenal cdeice
 Date,
Page

) Device comication:
I/o modeles can.laccbitcte commu Coab'o
belueen Connected perepheral.deu'ces.
) ontrol cn Timing
T/o modules ane desioned to mbae
Hhe data troiactions bellween tee interna
Sastem nd perepheraldeces:

2) Three brcod. claScoos of ecternal

or peripherel dexijGes a e inpe deuites,
orepul' deuices ano storage devie.
) Topul deuices
It cllows wer to send.odol or
Commands to tee Complen.
fa keuboards ,mouse,SCcrners

)Oulput devies
It displau ort present tee escales of
Compulen procesSing:
fa' Moritors, frenter, Speakers
) Storreae deuices
JB Sfore dat Cndinotcuctiond etter
temporaruly or pemanenty
.Ea Harnd dreves,Flesh dreves
) The &ASSA Prertammable Periepheral Trteyace
CPPT) host omcen moodes operceion
æBt Set/Reset (BSR) mode

) Bit Set/Reset (BSR) Mode'

d In BSR mode, onuporl C(Pc?-PCO) Cen be
individuille set or nesef .
) The Contrrol woro mB (D?) Sc cwben
BSR mode js selected.
u) The mode cllousc Control overe ndi'viel
bit of pore C fo vanies cpplucafiord.
v) 8SR mode SIodependent o T/o mode cnc
doesnt oyect thecperation of pores tn
T/o mode.

> Inpuloutpul (T/o) Mode

T/oinode is Selecied chen ee cotrol
word' MSB CD7) S L.
) T4 ferter divides into tenee sceb-modes!
(S Mode osimple I/o):
Al frree porls (A, B& ) Can finction
s Simple inpet or tput pores.There is
no. interrupt harding Capabilh in teit mode.
(b) Mode 1(Hard shake 1/o):
Pbrct A corc B Can ct s jnpel n ocopet
porcts and port C bits are cseo fore
handcaking Snala be<ore dat ttensfor.
TH has internup hardleng Coupability ne
Lalche inpee cd ouepu.
 clAssMAte
Date

OModea (B diectional T/oJ

on poRt Acworks , crd porte B Co
work in mode o Cnd l.Porec bits te eses
for handchaena sanald cnd Halso has
inieept handig opabiltey
9) To Confialere the Intel 255A 'Pooriammable
Peipheral Inteface (PPT) is
Port A: Tnpel
Port B) Oelpeee
Pore C' odtoel all bits
To see tBe cortrol word acCordihga tee
8a55A Control reaisterr (n
(h Mode o, ee
basic I/o mooeJ n &bit Contaol wod
tn tee given formal
D7 D6. D5 D4 D3 D DI DO
A B: A

whene;
cOorol Crot a BH See/Reseemode).
D6- Poct Adirectiont forr inpul, ofor ouut
D5 Pont Ccepper CPC7- PGM): 1goriinpl,
O for oepee
D4: Pot B dltrrection:for inpet,oßor
 D3- MOde selection for Grocep B(Porrl Bi aid
PC3- PCo):ofor Mmode o
Da= Porec louser (PC3 - P( oJi1fore inpul, o
for ioulpeel
D- DO Mode se lechon for Grcp A orl A
and PCG-PCH): 0o forMode O!
Bey applegina tee reneired Conialont
Port A: Ippul > D6|.
Port B:Oulpe Dyso
Portc pper : oulpul> D5 20.
Pore C lower :oulpeD2O
Mode o for both tecpi’ DÊ- Do- oo, D20
D7 =1 Cmnust be Tfor contral woro)
By puthing tee bis togefher from tee
11
nequineod congiguraion
D5 D4 D DI o
C

Binary Ilo0oo00
Hena oeunal: Co
The contrrol nejster value is l1oo000o
Cbinctre) and oro (hexa deuma).
. The auestion have been Solved throLqh
Kgcue &l0 by regoreNcing eom te boole.
 clAssMAte
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5) ) Mode a fon i) ano Mode I tor ).

ExplanoPionl
8255, Vareoc modes is bein deCribes
Mode : Tnpeel or oulpef cotte handshale
In tis mode fo llowina achions ane enelebed
Two pore (A &. B) feenchon ad: &bitinpue
Oulpul port.
a. £ach porre ceses tree lenci fromc ada
handshahe sjapal:
3 Tnput &opefdala ne latched.
Frrom iÝ 48e mode s .

Mode a Bi-dinectional daf transßen

The mode is ceseo to transfer daka
belween t o tompfer. In teis ode
port A Con be conkqerres es bilirechional
: pore. fort AiLsesifie Kjantl from port
C as hand Shake sienal.
forr Ci the mode fea.

So, option (d) coill be cornect grom tee gien

talements
6). The SCSGA Preoaremmable tnterut Cortiolle
CPJC) rS desijneo b Intet to munge
hardwane interrpts Cnd redce tee
Ioterrcept loao on e CPU.
A Sinale ga(59A Can handle 8inteneupts
inpcelsIRQO- TR9D.To handle epto 64/o
interrupt requests, meleple 89CEAA Chips Can
be CasCaded toaethert in a master -s(ave
Conßigeation.
)Master 89c59A).
Handles t e mnan Commleucxeion colte
tee CPU.

>slave 82c5A.
Sends its interrcept reqests to tee master,
occcepuing one ee mater's IR inpees.
2)Casciding
pto &slave pICs an be CohneCfed to
one mster, eaCh Slaeqivina
lines, for o total of. &(slave) 8(line)
64 inteuupt inpues.
Acvataaes of 8C59A CPTC):
) Scolenble upto 64 intereepts.
o Recduces CPU ovechees b manaoing meleple
TRQ
cD Preiorete can be proarammed (fenee Or
rrotana
 JASSMAte
Date
Pace

* Bloca diagram f cascadine &acs9A for

kon
64 tnterrapts
CPU(TNT, TNTA)
INT.

Master 8A(59A.
(IRO-IR7 npub)

IR IR3

Slave PTC | ** Slave PIC &

Each has 8inpeks 64 Total TRQS

> worhing rincple of 82C59A (PI)

) I/o Device Interrupt
Any o the 64 Ilo odeices send cn
interipf Signal to one by te.e clave pICs.
) Slave to maten
The Sla Ve PICircoeses an thteroypt on
Its Connecte IR ene to teemAter.
UiD Mater to CPU
The mster PIC Sende 6e INT signal
to the CPU.
i Tnterrept Acknooledge cINTAJ)
The CPo ackhocwledge the tnfereept , The
master idenies whech slave ieeo ee
interept and tells tee CPU.
CPU Ereceeles ISR )
The CPUthen aCesses tAe coreect!
interript Sewtee Roueioe (TSR)Cesing te e
vectore Qd dres prrovided.
)o An operaling sqstem. (o)isa Saltenm
Sgtware hat octs cs un intertace beten,
Heie Conputerr h dare ard cier
), I manages nd controls compcaler resocerces,
Such aa menorri, CPO &peupherals
Cllouing csers to uun ppucolicOrd no
ioteractcoits te compeben!ee
D ESsenialley, tRe' os provides te fendeGion
for ll otker software to fectron on t
Compule
8) The kee Sewices provided bu on os nt)"
Progrceam Sxeceetion.:
The os load or e s proerrema,enseng
bave te rresouces thez need to cpertete.
Memoy mangoement
The & locales cno dellocates memory fo
enninq progroms,prewentina Corgec ts ar
ophming riesorce csage.
 The os prrovides astrecferred wRy to
orcacn2e store nd actess feles oneR Suter
llbcoino uier to creoleymodond
delete les.
æy Preocess manggement
HThe asQs manaei the eoecieion o neltrple
or pocesse
maLsers Conceenentu
allbwing sers to to perporrm mueeple tecks
Simeltoieesly

The as manoqe tee interaChon betoeen

e Conmpuler & peripheral deices (eg)
keyboad mouxe,printer).
(v) Reocurte Monanement.
The os allocales and mangaes vrubUs
nesorce,inelealina CPU time,memokty,
T/o dev'ces nd ofßerc hrcoware Compon,
Ensurceng egpcrend cubilezaion.

The os provides Seruices sr Conne(ting to

and Communiloing cwite ottet conpuled
Curd netonhs enablena dorbe sharing a
Collatoration.

The os implemen k seceeuty méasues d

pruotecttesstem cno cser dala fronm
nehorrezed access, malwe & hreab.
 Erriort Htndna
The as delects aned hcund Les ervcors,
pruovidina mecharisms fon necoverceyc d
prueventing Sustem eroshes.

Use Interfcel
The os prrovides a wser Bruendiintogace
(egqraphca or Commend-e'ne) 4eoA
alloco csers to iteract coitt tee seustem
Cnd contreol ts oparoiors.
q) Masor tapes g Opercating <egstems cre):
wBalch Operaing sgem'
Ereceet es bolches o Jobs othoceb.user
intercaetton.Comnmon in eorly Compeelers
úo. Time Shanina Operaeng Sgctem
Alouos multiple wses to access tee
spgstem Simuleaneusly be pidly
Sotchina belween tRerm.
j)DiStributed Operaing Sastem
MOnages o geoup indeperelent Compulerrs
nd mahes tem cppeour as a single Sqen
j) Nelworh Operotng sgfern
Provide serwice to lompulers connetfeo
Over a neluon ,ihe fele charrena cn
prenter access.
 Real Time Operoctina Seastem..CRTOJ
Preocesses dorta and eents in real-tine
cote strect timina costroint, oten wseo t
embedded Sustems
v) Mobile Cperatina Sastem
Destoned for mobile deuices lihe smant
phone Cno tablets e:a; Andrord, ios.

wiÜ Muleprogramming Operaing gten t

Allouo more than One prrogram to run
Concurrentyy bq manoaina CPU tin e uerta.
vi) Melbtsking Operalin Sestem
Enables eceeeicon multiple tashs
(procease ae tRe sane tine.
dk) MulA reeding peraeng System
Sepportes melbiple threads oittcn a
Single prto(eAs for parallel enecuton.
(N Embedded Operabing sastem
Tollorred for enbedeed SstemA 'eoith
wnted resoXrCes, Such s in appluances
or industreal machenes.

manaaer bg allo coting ,Contro llna aro

optimi2ng the wde f Seaiem nesoLces ehe
CPU time, menory ,storaae rd inpalloutp
deui ces Cmor veuebus progrcams as
processes.
i)T+ ersercescrere cero gcient elilezaeion
resoeces jlleoono meleiple cppla'catond
to reeun ConCeennenty coitoul inte7en
coitt each otAer.

)) Aresident monitor , oßten Aoceno in embedded

Sstem ,res'desin a pererd memo Loceceion,
typically in feesh memor or ROM CUnd
Conatontuy presernt in mêmorgy

inclee'es Code soace,do Dce (for

daba Spce
Vara'akbles ane Constats ) and poten thially
a stach for fen Ction Calls.
lD The speayec agoet is detemineo by t e
torrae& harrdue cro tee monetorls
fen ctionaleky
Intereupt rocesshg
Device Dre'vercs
Resident
Job seqLencing monton

Control anguog e
Jnterprefer
Bocendarcey
cser Prooram
Anea

D0agrtam o% memory laol of nesident niton

 clascte
Date
Page

Uniproaraming malipreogrammna
Oonly one programtme.ae
rnsomultiple progran
in menmory a a locded in memory
nd.enecetedconlurnet.
i cohe'eone proarom
KenDin przoarcam wets forIlo, he CPu
ceetsfor To. Switches to anotser
eady program.
henTlo: rSoCCeering: cetilezalion d
inprove trcoughput.
i) Eay Eale Compcelers hal iDEa Moden openaßna
ran ione Job at atime Sastem like wndous
krom &tanf to fiish.on linun
) Simple Complety and wmone complercky ano
Lowtrounhptl: High hroughpb.
I3) Operand ! oooo00 lo
operand a'-oo0000)
Flan valee

Zero
Ncaaie
1) Ra@e of microprroceisor clocied S0 5GtH2

5X1

Ta 1

F.00 PS
o& nano Seconds

b)Tinsteuctton 238T
- tinstreuction Bx a00PS.
.O6 nanoseCond

15) Operatina modes oy ARIM. prrocessor nebi

> Ucer Model
O Noremal proorram enecution
(io Limted &cannot acces proteced sisten
recorces on Chnge modes as it S
non- prvileaed.
 Dote
Pege

PIQ Modes
O Fast interrupt handlig
0) Privileqed Access Level (R8-RI9 to
W) T has additional banked rneaisters
Speed cp internpt rresponse
d) T+
T} cese forr Hjqh- Priot, timer erihial
d
interipts
2) IR modes
dtandard interrudlevee
handlrg:
dö frevileqed Acces RI3SP) and RNLR)
n) It hCs own banheo reaistens
V) It csed for General perpose interupts
Sepervisor Mode (s c J
qstnm or sogtane interpt hanlirg
). peraing ACCess
) Premleqed tevel
io Entened hrounb swr ( teware Tnterript)
instreechon.
d) Tt h own ban hes reasters SP and LR.
=) Abort mode (abt)l"
æHndles memory aclels violatbrs (ea, invald
Ldorres acces).
) Prrevileaed ACCess level

Undekneed Mode Cund):

0 Handes undekened indteectiors
) Preileoed AC (ess level
(i) TA has own banked renisters SP n LR.
 æ. Previle eo Mode Simila to use mode, wed
by as kor SaSter tas e.
U) Praevileced Mccess level bcel ceses tEe sane
reoi.ter sel cs ceserc mode.
16) OThe Cercnent Prciercem Sfatees ReoiStér (CPSR)
in ARM processorcd iS a 32-bit rreaister te.ae
holds in formation abocef e pro celsor's
Ceerrtent &tate curd Cortol.

i) It Contoins condition fls, Stales bits a

Contrcol bits cohch ingeeience Re preo&LSOr'
behau'oer.

>) Strectre o CPSR (39 bib)).

BiBs Desorepton
31-a8 N,2,C,v Conditon flags
N Negaive resule plan
2 Zerco neseele Biae
C'- Carra/ borrcowentend glae
V

Conditon flans (N,z,C,v)!.

These geags are cepooatecs cter crihmatre
on loaitorl operattors Cnd re ceseo korr
Condihonal exeleetion of instee cfiond.
NCNea aGive )) Sel 6e releell is henalive
 cClaraset ik n arith matre Canny or
borvo OC leed
vCoverklow) sel i there is an overglow in
Sianed operaton.
> Control Bit CI6T)
T). I; see, disables IRQ intereupts
F Sel, disab les fTQ intereepti
T' Inhotes teprrocessor is fn
Thtunb Stale (l6-bit instrestior) or
ARm Sfale (32- bit irsteusti'on)
Mode Bik
These bits determine ee ceent:
operabng mooe tee processor .
Some Common.modes anei
Joo00- e s e

100|O- IRQ
100)| ServiSor
|o]1 ) - Abort
1101) - hdeined
1|1|)

Usaoe CPSR)
D Monatorana proces sor ictefe
i) Controllina intersupt behaui'bur
ri) Soitching enecuPion mode
dv petermining ceurnent &tale
1 Thenearsterc orraenization o n ARM processor
S Steec fered to Seppore Rpeca ent dala
prrocesSina und Control.
) General- Purpose Renistera CRo- RIRD!
These e cused kore Crretmabic, loo'Cal
opereeions nd.cdafo Sforonee deeurond
proaam eNeceion.

Stacu Pointer (RI8 or SP)).

Ponts to tee top he Stact ,cuse in
feenChion Calls ond tnteepks.
) Link neaister (RI4 or LRD)
Stones ee nelern cddresc dereng fencton
calls orr eoceptiord.
Proarcan Conter (RI5 or PC))
Holds teAe aoores the neot instruetion to
be eae cuted.

> Progrrm stafu Reaisters CCPSR 3& SPSRÜ!

" CPSR Cunent Prngrcam stabees Reaisten )
Holds flags (eigj 2ero,corryiNçaahe,
Overfeocw),mode bits ano interrept enable bis.
"SPSR (Saued Proaram Staes Reaisier)).
eseo to Sawe tee CeSR dtee'ng eeephors
tnterrupts (avarlable tn pru'tleneo mode).
ARM proeAsors lso Supporl ban ked reg lcters
in certoen modes (eoy fQ, TRO, Supsvion),
 allecoin kast contet soitchrg ders
tee intviepts
13 ARM proceasors ueiuze var'OLl aodheseina

Renister - Indirect Addnessing

The address o t e data ts Sfored in a
eoster, Cnd he irstreeechion impliecty cses
ths rep isterc tó acceit menoty.
Eg LDR Ro,[RIT
Base -pus-o% see tddressing
The eeective cdoress cnlceelo@ed hu
Cooing an fee toa base negiafels
Content
Eg LDR Ro,[RI, Rl
LDR RO, ER);#4]

scaled -Index Addressing)

Sinilar to base-pluis-oßsel, beel tee
OßAee S Shgtee tSCaled) before beeng
CUolded to the ba e rieacter
Eg LDR Ro, [RI, Ra, TCL #2]
) Immediae AddressiFa
The operand (data or' adoiess iS
drnectu ncleede in the inatreecton ise
Egr Mo Ro,#lD
|4) LDR RO, = Ox 4532 A8cD
mov R, #ox4o
ADD Ro,R!,Ro
STR Ro, [RI
My ExIT BMYEXIT

Ainal Reaster values

Reaster Vale
Ro Ox 4532BCO
RI

Memor Content
Addrnes value
OX453ACDD

ao AREA 2eroçoenl, CODE , READONLY

ENTRY
MOV R0, #Ox fo
Mov RI, #o ;R) oill cocent o 2err0s
MOV R, #32 ) 3R bik to Check
Coceneloop
TST Rb, #I STest leat slaCat b/t
BEQ iS- Zero )I4 Zero,banth to intremeat locnte
Ship
LSR Ro, Ro, #| 3Loqilal chizt aht Ro y !
SODS RR, R8,# I ; pecremert bit Conten
BNE Coeunt loop ; I not o,loop agn
end
iS-2ero
A
DD RI,R|#| ;Inerenent zero Core
B Saip ; Countnue loop
end
B end ; Tngfi'nite loop aften fehishng