Experiment no.

04
Experiment Name: Design and simulation of 3-bit & 4-bit asynchronous up counter and 3-bit
& 4-bit asynchronous down counter.
Objectives:
1. To understand the design and working principles of asynchronous (ripple) counters.
2. To design 3-bit and 4-bit asynchronous up counters using basic digital components such
as flip-flops, and analyze their counting sequences.
3. To design 3-bit and 4-bit asynchronous down counters, exploring the reverse counting
operation and understanding the logic involved in the down-counting process.
4. To simulate the operation of asynchronous up and down counters in a virtual
environment, such as Logisim.
Theory: In digital logic and computing, a Counter is a device which stores (and sometimes
displays) the number of times a particular event or process has occurred, often in relationship
to a clock signal. Counters are used in digital electronics for counting purpose, they can count
specific event happening in the circuit. For example, in UP counter a counter increases count
for every rising edge of clock. Not only counting, a counter can follow the certain sequence
based on our design like any random sequence 0,1,3,2...and so on. They can also be designed
with the help of flip flops. It is a group of flip-flops with a clock signal applied.
Asynchronous or Ripple Counters - In asynchronous counter, universal clock is not used, as
is the case in synchronous counters, only first flip flop is driven by main clock and the clock
input of rest of the following counters is driven by output of previous flip flops [1].
Asynchronous counters are also known as ripple counters and are formed by the successive
combination of trailing edge-triggered flip-flops. It is called so because the data ripples
between the output of one flip-flop to the input of the next [2].
To be precise, in an asynchronous counter, each flip-flop's output serves as the clock input for
the next flip-flop. This causes a delay because each flip-flop has its own switching delay,
known as propagation delay. The delay accumulates as the output of each flip-flop triggers
the next one in the chain, leading to a ripple effect across the flip-flops.
Asynchronous Up Counter: It is a type of digital counter where the output of one flip-flop
triggers the next flip-flop in the sequence. Each flip-flop represents a bit, and the count
increments (or "counts up") with each clock pulse. As the clock pulse is applied to the first flip-
flop only, and each subsequent flip-flop is triggered by the output of the previous one, this
causes a ripple effect, resulting in a delay between the flip-flop outputs. The counter increases
its binary value with each clock cycle (e.g., 000 → 001 → 010 → etc.).
Asynchronous Down Counter: An asynchronous down counter is similar in design to an up
counter, but it counts in the reverse direction. Instead of incrementing, the counter decrements
with each clock pulse (e.g., 111 → 110 → 101 → etc.). Like the up counter, it uses a series of
flip-flops connected in sequence, but the connections are configured so that the binary count
decreases with each clock pulse.
Required Software:
 Logisim
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Working Principle: Number of flip-flops required is equal to the number of bits. The clock
signal is applied to the first flip-flop, i.e., the least significant bit, or LSB. Each time the clock
pulses, the LSB flip-flop toggles its state (from 0 to 1 or from 1 to 0). When the LSB flip-flop
(QA) transitions from 1 to 0 (i.e., after a full cycle of toggling from 0 to 1 and back to 0), it
triggers the second flip-flop (QB) to toggle. Similarly, when QB transitions from 1 to 0, it
triggers the next flip-flop (QC) to toggle, and so on for higher-order flip-flops. This sequential
triggering is called the ripple effect because the changes "ripple" through the flip-flops, with
each flip-flop triggering the next one after it completes a full cycle (from 0 → 1 → 0).
The asynchronous up counter increments in a binary sequence. For an n-bit counter, the binary
count starts at 0 and increments to 2ⁿ - 1. On the contrary, the asynchronous down counter
counts backward in binary. And for an n-bit counter, it starts at the highest binary value (2ⁿ - 1)
and decrements to 0.
The output of the LSB flip-flop (QA) changes at the fastest rate with every clock pulse. The
next flip-flop (QB) toggles at half the frequency of QA, and QC toggles at half the frequency of
QB. This creates a binary counting sequence as the flip-flops toggle.

Design & Simulation:

 3-bit Asynchronous Up Counter:
Truth Table:
Output
Clock Pulse Decimal Value
QA (LSB) QB QC (MSB)
Initially 0 0 0 0
1st () 0 0 1 1
2nd () 0 1 0 2
3rd () 0 1 1 3
4th () 1 0 0 4
5th () 1 0 1 5
6th () 1 1 0 6
7th () 1 1 1 7
8th () 0 0 0 0

Figure 4.1: Circuit Diagram of 3-bit Asynchronous Up Counter Using J-K

Flip-Flops

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 Figure 4.2: Simulation of 3-bit Asynchronous Up Counter in Logisim
Where It Counts 2 in Decimal Value

Figure 4.3: Simulation of 3-bit Asynchronous Up Counter in Logisim Where

It Counts 7 in Decimal Value

 3-bit Asynchronous Down Counter:

Truth Table:
Output
Clock Pulse Decimal Value
QA (LSB) QB QC (MSB)
Initially 1 1 1 7
1st () 1 1 0 6
2nd () 1 0 1 5
3rd () 1 0 0 4
4th () 0 1 1 3
5th () 0 1 0 2
6th () 0 0 1 1
7th () 0 0 0 0
8th () 1 1 1 7

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 Figure 4.4: Circuit Diagram of 3-bit Asynchronous Down Counter Using J-
K Flip-Flops

Figure 4.5: Simulation of 3-bit Asynchronous Down Counter in Logisim Where

It Counts 5 in Decimal Value

Figure 4.6: Simulation of 3-bit Asynchronous Down Counter in Logisim

Where It Counts 1 in Decimal Value

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  4-bit Asynchronous UP Counter:
Truth Table:

Output
Clock Pulse Decimal Value
QA (LSB) QB QC QD
Initially 0 0 0 0 0
1st () 0 0 0 1 1
2nd () 0 0 1 0 2
3rd () 0 0 1 1 3
4th () 0 1 0 0 4
5th () 0 1 0 1 5
6th () 0 1 1 0 6
7th () 0 1 1 1 7
8th () 1 0 0 0 8
9th () 1 0 0 1 9
10th () 1 0 1 0 10
11th () 1 0 1 1 11
12th () 1 1 0 0 12
13th () 1 1 0 1 13
14th () 1 1 1 0 14
15th () 1 1 1 1 15
16th () 0 0 0 0 0

Figure 4.7: Circuit Diagram of 4-bit Asynchronous Up Counter Using J-K Flip-
Flops

Figure 4.8: Simulation of 4-bit Asynchronous Up Counter in Logisim Where It

Counts 3 in Decimal Value

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 Figure 4.9: Simulation of 4-bit Asynchronous Up Counter in Logisim Where It
Counts 10 in Decimal Value
 4-bit Asynchronous UP Counter:
Truth Table:

Output
Clock Pulse Decimal Value
QA (LSB) QB QC QD
Initially 0 0 0 0 0
1st () 0 0 0 1 1
2nd () 0 0 1 0 2
3rd () 0 0 1 1 3
4th () 0 1 0 0 4
5th () 0 1 0 1 5
6th () 0 1 1 0 6
7th () 0 1 1 1 7
8th () 1 0 0 0 8
9th () 1 0 0 1 9
10th () 1 0 1 0 10
11th () 1 0 1 1 11
12th () 1 1 0 0 12
13th () 1 1 0 1 13
14th () 1 1 1 0 14
15th () 1 1 1 1 15
16th () 0 0 0 0 0

Figure 4.10: Circuit Diagram of 4-bit Asynchronous Down Counter Using J-K
Flip-Flops

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 Figure 4.11: Simulation of 4-bit Asynchronous Down Counter in Logisim
Where It Counts 7 in Decimal Value

Figure 4.11: Simulation of 4-bit Asynchronous Down Counter in Logisim

Where It Counts 4 in Decimal Value

Disadvantage of Asynchronous/ Ripple Counter: Propagation delay refers to the small

delay between the time when the clock (or output of a previous flip-flop) changes and when
the subsequent flip-flop changes state. In an asynchronous (ripple) counter, the flip-flops do
not change state simultaneously because the output of one flip-flop serves as the clock for the
next flip-flop. This causes a delay between the state changes of QA, QB and QC.

Figure 4.13: Timing Diagram of Asynchronous/

Ripple Counter Showing Propagation Delay

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When counting a large number of bit, due to the chain system, propagation delay by successive
stages became too large which is very difficult to get rid of. In such a situation, Synchronous
counters are faster and reliable. There are also counting errors in Asynchronous Counter when
high clock frequencies are applied across it.
Discussion: In this experiment, we successfully designed and simulated both 3-bit and 4-bit
asynchronous (ripple) up and down counters using flip-flops in Logisim. The counters
demonstrated the expected functionality: the up counter increased its binary output with each
clock pulse, while the down counter decreased its binary output.
For the up counters, the output bits toggled in a sequence that represented increasing binary
numbers, starting from 000 and counting up. In contrast, the down counters started at the
highest binary value for the given number of bits and decremented with each clock pulse. The
results confirmed the working principle of asynchronous counters, where the clock input is
applied only to the first flip-flop, and the outputs of the subsequent flip-flops serve as the clock
for the next flip-flop in the chain. This creates a ripple effect, leading to a small propagation
delay.
The propagation delay became evident during the simulation as the output changes rippled
through the chain of flip-flops. The delay in state changes between flip-flops increases with the
number of bits, which can lead to issues when working with high-frequency clocks or counters
with many bits. This makes asynchronous counters slower compared to synchronous counters,
which change state simultaneously. The timing diagrams and truth tables generated during the
simulation align with the theoretical concepts discussed.

Conclusion: The experiment successfully demonstrated the working principles of both 3-bit
and 4-bit asynchronous up and down counters. The counters were designed and simulated using
J-K flip-flops, and the results confirmed that the counters function correctly. The key takeaway
is that while asynchronous counters are simple to design, they suffer from propagation delays
due to the ripple effect between flip-flops. This makes them less suitable for high-frequency
applications where timing precision is critical.
To overcome the limitation of propagation delay, synchronous counters are preferred for
applications that require faster and more reliable counting. However, asynchronous counters
remain valuable for simpler and low-frequency digital systems due to their straightforward
design.

References:
[1] 3-Bit Up Counter [Online]. Available:
https://www.deldsim.com/study/material/44/3-bit-up-counter/ (2017-2024)

[2] Asynchronous Counter [Online]. Available:

https://electronicscoach.com/asynchronous-counter.html (2024)

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