International Journal of Mechatronics, Electrical and Computer Technology (IJMEC)

ISSN: 2305-0543 (Online), ISSN: 2411-6173 (Print)

Vol. 10(38), Oct. 2020, PP. 4773-4778

FinFET-based Full Adder using SDTSPC Logic

with High Performance
1st* Amir Baghi Rahin 2nd Vahid Baghi Rahin
Department of Electrical Engineering, Department of Electrical Engineering,
Sardroud Branch, Sardroud Branch,
Islamic Azad University Islamic Azad University
Sardroud, Iran Sardroud, Iran
[email protected] [email protected]

Abstract—This paper presents an optimized design of Effect Transistor (CNTFET) [10] are possible surrogates for
SDTSPC logic (stacked diode transistor based TSPC) using conventional silicon-based MOSFET technology.
FinFET transistors for 1-bit full adder. The analysis was
performed for average power consumption, leakage power, Addition is very important in computational operations
propagation delay and power delay product (PDP) for different and has been widely used in many VLSI designs, in most
supply voltages, loads and temperatures. Comparing the general-purpose systems operations, and in specific
proposed FinFET-based full adder design with MOSFET-based processors. Improving the performance of the full adder
SDTSPC full adder, we achieved a 95.75% improvement in improves the overall performance of the system. Full adder
leakage power consumption. The proposed scheme is also design methods can be generally classified as static and
compared with several previous designs and based on different dynamic logic. Static logic is robust and easy to design.
simulations, the proposed FinFET-based full adder exhibits Dynamic logic has attractive features despite its high
excellent performance. The proposed high-efficiency full adder switching activity. They are usually faster than their static
cell operates at low voltages (0.4 V) even with large capacitors. counterparts. They need fewer transistors, which results in less
area. In addition, voltage levels generally have full swing, and
Keywords—SDTSPC (stacked diode transistor based TSPC) have no static power loss due to the elimination of short-
logic, FinFET transistor, power delay product (PDP), TSPC logic circuit currents, which flow in static circuits when creating a
I. INTRODUCTION direct path from the power line to the ground [11, 12].
However, in dynamic circuits, clock distribution connections
Transistors are essential components in electronic lead to increased power consumption [13]. Also, dynamic
equipment such as radios, calculators, personal computers, logic is more sensitive to noise. However, this noise can be
notebooks, tablets and other electronic equipment. The reduced by several methods. Most plans are offered with one
demand for these electronic equipment is increasing or more compromises. Conventional standard CMOS designs
day-to-day. Therefore, it is important for manufacturers to cannot deliver high-speed digital design, so dynamic logic
produce high quality electronic equipment and various circuits are used to achieve fast digital designs.
functions. Scaling down the MOSFET process in CMOS
technology has become increasingly important in order to Since the full adder cell is the core and the building block
meet customer demands. Reducing the channel length, gate of most computing circuits, it has always been important to
oxide thickness, and supply voltage over the past three design high-performance full adder cells and complex
decades has increased transistor performance in terms of computing circuits with low PDP [6, 10]. This paper presents
speed and power consumption [1]. Fabrication costs have also a high-speed, low-power, low-PDP FinFET-based full adder
decreased sharply. Reducing the size of transistors by scaling for low voltages. The performance of the proposed design will
of technology has led to increased number of devices and the be evaluated in different situations and compared to other
density of integrated circuits [2-4] and an increase in conventional and up-to-date full adder cells in different styles.
capacitive coupling due to the high clock frequency [5]. In This article is organized as follows. In the Section II, we will
addition, by scaling the supply voltage, the threshold voltage have an overview of the FinFET transistor. In Section III, we
is also lowered to maintain circuit performance, which present the proposed FinFET-based full adder circuit. The
increases the leakage current of the device. results of the simulation and performance analysis of several
circuits along with the proposed circuit are discussed in
If the channel length drops below 20 nm, transistors will Section IV. The conclusions will be summarized in Section V.
lose performance. This means that conventional silicon
MOSFETs will no longer be able to maintain Moore's Law. II. OVERVIEW OF THE FINFET TRANSISTOR
However, improved performance of electronic devices is very FinFET is categorized as a multi-gate device whose
desirable in today's semiconductor industry. Therefore, performance is often similar to traditional MOSFET.
engineers and scientists are trying to find a solution to Typically, it has a source, a drain and a gate to control the
overcome this challenge. Multi-Gate MOSFETs (i.e. FinFET) current. The channel is made between the source and the drain
[6, 7], Quantum-Dot Cellular Automata (QCA) [8], Single of FinFET, which is a 3D strip at the top of the silicon
Electron Transistor (SET) [9] and Carbon Nanotube Field- substrate (so called Fin). In order to form several gate

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Article History:
Received Date: Apr. 14, 2020, Accepted Date: Jul. 16, 2020, Available Online: Sep. 01, 2020
Amir Baghi Rahin et al. / FinFET-based Full Adder using SDTSPC Logic with High Performance

electrodes on each side, which may reduce the effects of in silicon, and to enhance device performance and energy
leakage and increase the excitation current, the gate is covered efficiency of full adders.
around the channel (as Fig. 1). FinFET devices are
manufactured in many different ways. In shorted-gate In [14], the designing problem of energy efficient and low
FinFETs (SG-FinFETs), two gates are connected to each noise dynamic TSPC logic for digital CMOS circuits is
other, resulting in a three-terminal device. This can be used as addressed. The proposed scheme in [14] is named as SDTSPC
a direct alternative to traditional bulk-CMOS devices. In logic (stacked diode transistor based TSPC). To reduce power
independent-gate FinFETs (IG-FinFETs), the upper part of the consumption, the effect of stacking on the power supply path
gate is etched and it provides two independent gates. Since, to the ground has been used and to reduce noise, a self-biased
two independent gates can be controlled individually, NMOS transistor has been used in series with the evaluation
IG-FinFETs provide more design options (see Fig. 1). Front transistor. In self-biased transistors, the gate and the drain are
gate (FG) and back gate (BG) of IG-FinFET can be connected connected together as a single node. The good thing about the
in different configurations. IG-FinFET can be considered as self-biased transistors is that they do not require any external
two parallel transistors, and two gates can be stimulated control circuitry and the control signal is generated inside the
independently as shown in Fig. 2. One of the gates, commonly circuit itself. Since gate and drain are interconnected, the
called the back gate, affects the vertical field of the other saturation conditions Vds> Vgs-Vth are always maintained [15].
transistor in the channel region. Thus, it changes the threshold Where Vds is the drain-source voltage, Vgs the gate-source
voltage of device. It also affects the diffusion current in the voltage and Vth is the threshold voltage of the MOS transistor.
sub-threshold regime, thereby controlling the leakage current. In [14], the method of step charging and discharging of the
In addition, two parallel transistors in the IG-FinFET can be node capacitance using self-biased transistors is used. This
interconnected to improve driveability or to form a single reduces the ground and supply bouncing noise. Advantages of
transistor with independent gates. In Fig. 1, the effective the SDTSPC design in [14] over other available designs
channel length and width are equal to 𝐿FIN and ℎFIN, include low power consumption, switching noise reduction,
respectively. The device parameters used in this article are high speed over other dynamic circuit design styles, no charge
listed in Tab. I. sharing problem in dynamic node during pre-charge mode,
reducing the ground and supply bouncing noise, robust against
process corner changes. The proposed circuit in [14]
effectively reduces total power consumption and idle power
consumption. The key idea behind this method is to reduce
power consumption by efficiently stacking the transistors
from the supply voltage path to the ground [16, 17]. Also, a
diode connected transistor is connected in series with the
evaluation transistor to further improve noise and power
consumption [18].
For this purpose, we implement SDTSPC full adder using
FinFET transistors. We replace all MOSFET transistors in the
Fig. 1. IG-FinFET structure [6] structure of this full adder with IG-FinFET transistors. Fig. 3
shows a schematic of the proposed full adder based on the
FinFET transistor. Compared to [14], the number of
transistors in the proposed full adder cell is reduced, because
that two parallel MOSFET transistors are replaced by a two-
gate FinFET transistor [7].
The proposed circuit consists of two P-FinFET pre-charge
transistors (Mpc1 and Mpc2), one N-FinFET evaluation
(a) (b) transistor (ME), and four leakage control transistors (consists
of two N-FinFET (Mn1 and Mn2) and two P-FinFET (Mp1 and
Fig. 2. IG-FinFET symbols; (a) p-type, (b) n-type [6]
MP2)). An N-FinFET transistor called MD is placed as a diode
TABLE I. Device parameters of FinFET [1] connected transistor in series with to the evaluation network
Parameter Value (ME). In this structure, leakage control transistors and diode
Length of the channel (𝐿) 32nm connected transistors creates the stacking effect and thereby
Thickness of front/back gate oxide (𝑡oxfg/𝑡oxbg) 1.6nm reduces power consumption.
Thickness of the fin (𝑡Si) 8nm
Height of the fin (ℎfin) 32nm The advantage of transistor MD is the bouncing noise
Work function (N/P) (𝜑N/𝜑P) 4.5eV/4.9eV reduction during the evaluation phase. As during the transition
Power supply (𝑉dd) 0.9 from the pre-charge to evaluation state the transistor ME is
Channel doping (NBODY) 2×1020 cm-3 switched on first, then MD is switched on when the voltage at
Source/ Drain doping 2×1020 cm-3
node N3 is around the threshold voltage of MD, thereby
III. PROPOSED DESIGN reducing the sudden current impact and noise [14]. Another
advantage is that no additional control circuitry is needed to
Having a full adder with low power, high speed and energy control the performance of the leakage control transistors. In
efficient is very important. Compared to conventional addition, the reduction in power consumption is achieved by
MOSFET technology, the new FinFET technology can be connecting the source terminal of latch N-FinFET to the node
implemented in 1-bit full adders, to continue scale reduction N E.

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EISSN: 2305-0543, PISSN: 2411-6173
International Journal of Mechatronics, Electrical and Computer Technology (IJMEC)
Vol. 10(38), Oct. 2020, PP. 4773-4778

the maximum value is reported as the propagation delay of

each circuit. Average power consumption over a long period
of time is also considered as the average power parameter. In
order to make a compromise between the power consumption
and the delay of the circuits, the performance of these circuits
can be evaluated by calculating the power delay product
(PDP), which is the product of average power consumption
and maximum delay. Consequently, PDP can be an important
parameter for evaluating and comparing the performance of
these circuits.
Simulations in [14] were performed using 180 nm PDK
BSIM3V3 process models in cadence with power supply
voltage of 1.8 V, clock frequency of 500 MHz and load
capacitance of 1 fF at sum and carry outputs. In the first
experiment, we simulated this circuit at 25 °C with 32nm
CMOS technology with power supply voltage of 1V, clock
frequency of 500 MHz and load capacitance of 1 fF at sum
and carry outputs. We also simulated the proposed FinFET-
based circuit with 32 nm FinFET technology with the above
conditions.
Fig. 4(a) and Fig. 4(b) show the input and output
waveforms of the SDTSPC full adder with 32 nm CMOS
Fig. 3. Proposed FinFET-based full adder technology, and the proposed SDTSPC full adder based on
32 nm FinFET technology in the first experiment. In both
During the pre-charge mode, the pre-charge transistors forms, the first waveform is clock signal (Phi), the second and
(MPC1 and MPC2) are switched on, so the voltage at nodes P1 third waveforms are data inputs (A and B), the fourth
and P2 are increased, Mn1 and Mn2 (leakage control transistors) waveform is carry input (C), the fifth and sixth waveforms are
are switched on and the output node is pre-charged. During sum and carry output, respectively.
this phase, Mp1 and Mp2 (leakage control transistors) are
switched off. Since the evaluation transistor is switched off, Tab. II presents the simulation results with the above
the voltage at nodes N1 and N2 increases as a result of the conditions and the best results are bolded. These results show
increased stack of transistors. that the SDTSPC full adder at low voltage and 32nm CMOS
technology perform poorly in terms of delay, power
During evaluation mode, pre-charged transistor is off. As
consumption, leakage power and PDP. While the proposed
a result, leakage control transistors are also turned off.
FinFET-based SDTSPC full adder perform well. In further
Therefore, an stack of transistors is generated from the power
experiments we will show the better performance of the
supply to ground path. Depending on the input values, voltage
proposed full adder.
levels at nodes N1 and N2 are lowered or remained high. If it
drops, Mp1 and Mp2 will get turned on and provide the TABLE II. Simulation results of the first experiment
evaluation path for the charge stored in the dynamic node. Full Adder Tech. Vdd Delay Leakage Power PDP
Therefore, during the evaluation phase, if the inputs are such Design (V) (ps) Power (µW) (aJ)
that there is no discharge path to ground, then the leakage (nW)
control transistors increase the stacking effect since they are FinFET 32nm 1 49.44 0.43 0.640 31.6
switched off and thus reduce the power consumption of the SDTSPC FinFET
device. (Proposed)
CMOS 32nm 1 113.77 752.78 0.788 89.7
IV. SIMULATION RESULTS AND ANALYSIS SDTSPC CMOS
The proposed design has been widely evaluated in various [19]
situations and compared with other classical and modern full CMOS 180nm 1.8 53.1 10.12 0.402 21.3
adders. All designs are simulated using the Synopsys HSPICE SDTSPC CMOS
2008 simulator with 32nm CMOS technology for CMOS [19]
circuits, and 32nm FinFET technology [19] for FinFET
circuits.
In the second experiment, the proposed full adder was
Simulations were performed at room temperature and at simulated at the supply voltages of 0.8, 0.65 and 0.5 V, the
different voltages, frequencies, and load capacitances. The clock frequency of 500 MHz, and the inputs with frequency
complete input pattern was applied to circuits with all possible of 100 MHz and with load capacitance (Cload) of 2.1 fF. The
transition states from one input combination to another to exact results of these simulations are listed in Tab. 3 and
measure their propagation delay. The delay measurement of compared with other conventional structures such as Hybrid,
each circuit is performed from the time the input signal CMOS-Bridge, TGA and Design3. The best results are
reaches Vdd/2 until the output signal reaches the same voltage displayed at each voltage with bolded numbers. According to
level. All states of transmission from one input to another are the experimental results, the proposed FinFET-based full
investigated and delay is measured for each transmission and adder has the lowest leakage power compared to other

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Amir Baghi Rahin et al. / FinFET-based Full Adder using SDTSPC Logic with High Performance

structures at the voltages of 0.8, 0.65 and 0.5 V. In terms of TGA [22] 2036.9 57.09 283.39
propagation delay and PDP, it also performs better than other Design3 [23] 2283.8 62.05 364.19
FinFET SDTSPC (Proposed) 196.57 111.46 85.40
structures. Average power (×10−6 w)
Hybrid [20] 0.0603 0.1023 0.1588
CMOS-Bridge [21] 0.0573 0.0981 0.1492
TGA [22] 0.0659 0.1054 0.1617
Design3 [23] 0.0592 0.1048 0.1617
FinFET SDTSPC (Proposed) 0.1506 0.287 0.474
Leakage power (×10−9 w)
Hybrid [20] 386.37 689.64 1500.9
CMOS-Bridge [21] 6.4181 2.0780 4.2522
TGA [22] 8.2755 5.0872 9.2551
Design3 [23] 17.450 5.3407 7.1369
FinFET SDTSPC (Proposed) 0.201 0.27 0.35
PDP (×10−17 j)
Hybrid [20] 6.4235 3.4722 3.0630
CMOS-Bridge [21] 7.2793 3.9401 3.4236
TGA [22] 13.424 5.8770 4.5832
Design3 [23] 13.530 6.9398 5.8890
FinFET SDTSPC (Proposed) 2.96 3.20 4.05

To evaluate the immunity of the proposed full adder to the

ambient temperature variation, the proposed circuit have been
simulated at a wide range of temperatures from 0 °C to 100 °C
at the supply voltage of 0.65 V, the clock frequency of 500
MHz, the input signals of 100 MHz and the load capacitance
of 2.1 fF have been simulated and compared to other full
adders. The results of this experiment are plotted in Fig. 5.
From the experimental results, it can be deduced that the
proposed full adder has acceptable performance at a wide
range of temperatures and its PDP is lower compared to other
(a) designs.
The driveability of the proposed full adder with load
capacitance changes was also investigated. The worst case of
delay occurs when the supply voltage is low and high load
capacitances are used. To investigate this feature, we
simulated the proposed circuit at a clock frequency of
500 MHz, an input signal frequency of 100 MHz, and a supply
voltage of 0.65 V using a large number of load capacitances
in the range of 1.4 fF to 4.9 fF and compared it with other
previous designs. The results of this experiment are shown in
Fig. 6. The results of this diagram can be useful for better
analyzing the driveability of the proposed design. From the
simulation results it can be deduced that the proposed full
adder cell works with high-efficiency at low voltages even
with large capacitors.

(b)
Fig. 4. Transient mode characteristic; (a) SDTSPC full adder with 32 nm
CMOS technology, (b) proposed FinFET-based SDTSPC full adder
TABLE III. Simulation results of the proposed full adder and
comparison with other structures (frequency=100 MHz, Cload=2.1 fF)
VDD (v) 0.5 0.65 0.8 Fig. 5. PDP of circuits versus temperature changes
Delay (×10−12 s)
Hybrid [20] 1064 339.41 192.85
CMOS-Bridge [21] 1269.9 01.44 229.43

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International Journal of Mechatronics, Electrical and Computer Technology (IJMEC)
Vol. 10(38), Oct. 2020, PP. 4773-4778

(b)

Fig. 6. PDP of circuits in terms of load capacitance changes

To investigate the driveability of the proposed full adder

in detail, we simulated the proposed circuit at clock frequency
of 500 MHz, input signal frequency of 100 MHz, and supply
voltages in the range of 0.8 V to 0.4 V using a large number
of load capacitances in the range of 1.4 fF to 4.9 fF. The results
of this experiment are plotted in three-dimensional graphs,
shown in Figures 7(a), 7(b) and 7(c), respectively, for
propagation delay, power consumption, and PDP. The results
of these charts can be useful for better analyzing the
driveability of the proposed scheme. From the simulation
results it can be deduced that the proposed full adder cell
works with high-efficiency at low voltages even with large
capacitors. The proposed full adder at supply voltage of 0.4 V (c)
can still work well. According to the simulation results, at Fig. 7. Variations of power supply voltage and load capacitance of the
supply voltage of 0.4 V and load capacitance of 1.4 fF to proposed full adder and its impact on (a) propagation delay, (b)
4.9 fF, the propagation delay changes in the range of 0.32 ns average power consumption, and (c) PDP
to 1.4 ns, the average power consumption changes in the range
of 73.2 nW to 105.12 nW, and PDP changes in the range of V. CONCLUSION
23.6 aJ to 147.21 aJ. The value of leakage power at this In this paper, a high-speed low-PDP FinFET-based full
operating voltage is 0.14 nW. These values indicate the adder for low voltage applications was proposed. The
excellent performance of the FinFET-based design at very low proposed full adder at supply voltage of 0.4 V can still work
voltage and high load capacitance. well. According to the simulation results, at the supply voltage
of 0.4 V and load capacitance of 1.4 fF to 4.9 fF, the
propagation delay changes in the range of 0.32 ns to 1.4 ns,
the average power consumption changes in the range of 73.2
nW to 105.125 nW, and PDP changes in the range of 23.6 aJ
to 147.21 aJ. The value of leakage power at this operating
voltage is 0.14 nW. These values indicate the excellent
performance of the FinFET-based design at very low voltage
and high capacitance.
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