Hi3516C V500 Professional Smart IP Camera SoC

Brief Data Sheet

Issue 01

Date 2018-06-28
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Address: New R&D Center, Wuhe Road,
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Email: [email protected]
 Hi3516C V500
Hi3516C V500 Professional Smart IP Camera SoC
Audio Encoding and Decoding
Key Specifications
 Multi-protocol audio encoding and decoding (G.711,
Processor Core G.726, and ADPCM) by using software
 Dual-core ARM Cortex-A7@ 900 MHz, 32 KB I-cache,  Audio 3A functions (AEC, ANR, and ALC)
32 KB D-cache, 256 KB L2 cache Security
 Neon acceleration and integrated FPU
 Secure boot
VENC  Hardware-based memory isolation
 H.264 BP/MP/HP  Hardware-based encryption and decryption algorithms
 H.265 MP (including AES, DES, 3DES, and RSA)
 I-/P-frames and SmartP reference.  Hardware-based HASH algorithms
 MJPEG/JPEG baseline (SHA1/SHA256/HMAC_SHA/HMAC_SHA256)
VENC Performance  Hardware random number generator
 8-kbit OTP storage space
 Up to 2304-pixel wide and 2304 x 1296 resolution for
H.264/H.265 encoding Video Interface
 Real-time multi-stream H.264/H.265 encoding:  VI
− 1920 x 1080@30 fps+720 x 480@30 fps+360 x − 1-channel VI
240@30 fps − 8-/10-/12-/14-bit RGB Bayer DC timing VI
− 2304 x 1296@20 fps+720 x 480@20 fps+360 x − BT.601, BT.656, and BT.1120 VI interfaces
240@20 fps − MIPI, LVDS/sub-LVDS, and HiSPi
 JPEG encoding performance: 4608 x 3456 @10 fps − Compatibility with mainstream HD CMOS sensors
 Five bit rate control modes (CBR, VBR, FixQp, AVBR, provided by vendors such as Sony, ON, OmniVision,
and QpMap) and Panasonic
 Up to 50 Mbit/s output bit rate − Compatibility with the electrical specifications of
 Up to 8-ROI encoding parallel and differential interfaces of various sensors
− Programmable sensor clock output
Smart Video Analysis
− Up to 2304-pixel wide and 2304 x 1296 resolution
 Neural network acceleration engine with processing
 VO
performance up to 0.5 TOPS
− One BT.656/BT.1120 VO interface
 Smart computing acceleration engine
− 6-/8-bit RGB serial LCD VO and 16-/18-/24-bit RGB
Video and Graphics Processing parallel LCD VO
 3DNR, image enhancement, and DCI − 4-lane MIPI-DSI VO
 Anti-flicker processing for video and graphics output
Audio Interface
 1/15–16x video and graphics scaling
 Audio codec, supporting 16-bit input and output
 Video graphics overlay
 Mono-channel differential MIC input for background NR
 90°, 180°, and 270° image rotation
 Single-end dual-channel input
 Image mirroring and flipping
 I2S interface for connecting to external audio codec
 Up to 8-region OSD overlay before encoding
Peripheral Interface
ISP
 POR
 3A functions (AE, AF, and AWB), supporting third-party
 High-precision RTC
3A algorithms
 FPN removal and DPC  2-channel LSADC
 LSC, LDC, and purple fringing correction  I2C interfaces, SPIs, and UART interfaces
 Direction-adaptive demosaic  Three PWM interfaces
 Gamma correction, DCI, and color management and  Two SDIO 3.0 interfaces, supporting the 3.3 V/1.8 V level
− SD 3.0 card supported over one SDIO 3.0 interface
enhancement
 Region-adaptive dehaze  One USB 2.0 host/device interface
 Multi-level NR (including BayerNR and 3DNR), detail  RMII mode, TSO network acceleration, 10/100 Mbit/s
enhancement, and sharpening enhancement full-duplex or half-duplex mode, and PHY clock output
 Local tone mapping External Memory Interface
 Sensor built-in WDR and 2F WDR (line-based/frame-  SDRAM interface
based/DCG) − 16-bit DDR3(L)/DDR4 SDRAM, supporting a
 Video-/Gyro-based 6-DoF IS maximum capacity of 8 Gbits
 ISP tuning tools for the PC − Up to 1800 Mbit/s rate
 SPI NOR flash interface

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 Hi3516C V500
Hi3516C V500 Professional Smart IP Camera SoC
− 1-/2-/4-line mode  Power consumption
− Maximum capacity of 256 MB Typical power consumption at 1080p@30 fps: 900 mW
 SPI NAND flash interface (650 mW with the NNIE disabled)
− Up to 24 bit/1 KB ECC performance  Operating voltage
− Maximum capacity of 1 GB − 0.9 V core voltage
 eMMC 4.5 interface − 3.3 V I/O voltage (±10%)
4-bit data width − 1.5 (1.35) V/1.2 V DDR3(L)/4 SDRAM interface
Startup voltage
 Package
Booting from the SPI NOR flash, SPI NAND flash, or eMMC
Body size of 12 mm x 12 mm (0.47 in. x 0.47 in.), 0.65
SDK mm (0.03 in.) ball pitch, TFBGA RoHS package with 280
 Linux-4.9-based SDK pins
 High-performance H.264 PC decoding library
 High-performance H.265 PC, Android, and iOS decoding
libraries
Physical Specifications

Functional Block Diagram

Image subsystem
16-bit CPU subsystem
VPSS+VGS MIPI/LVDS/
DDR3 (L) DDRC
HiSPi/
DDR4
Cortex-A7 MP2 BT.1120
GDC
@900 MHz
BT.1120/
(32K I/32K D/
SD card ISP RGB565/888/
SDIO 3.0 256K L2)
(3A/WDR) MIPI DSI

SPI flash/ SPI flash/ AMBA 3.0 bus

eMMC eMMC
RTC
AI
subsystem I2C x 7
Video subsystem
FE PHY ETH
NNIE SPI x 3
H.264/H.265/
MJPEG encoder
IVE GPIOs
USB USB 2.0
host/device IR
AES/DES
/3DES/HASH UART x 4
Audio
codec
I2S
PWM x 3

RSA/TRNG LSADC x 2
Hi3516C V500

Hi3516C V500 is a new-generation SoC designed for the industry-dedicated smart HD IP camera. It introduces a new-
generation ISP, the latest H.265 video compression encoder, and a high-performance NNIE engine, enabling Hi3516C V500
to lead the industry in terms of low bit rate, high image quality, intelligent processing and analysis, and low power
consumption. Integrated with the POR, RTC, audio codec, and standby wakeup circuit, Hi3516C V500 can greatly reduce the
EBOM costs for customers. Hi3516C V500 also provides similar interface designs to the HiSilicon DVR and NVR SoCs,
facilitating rapid mass production.

HiSilicon Proprietary and Confidential

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Copyright © HiSilicon Technologies Co., Ltd.
 Hi3516C V500
Hi3516C V500 Professional Smart IP Camera SoC
Hi3516C V500 HD IP Camera Solution
SPI flash DDR3

SFC DDRC
MIC Audio
codec
Speaker
RTC Coin battery
VICAP (ISP)
2M (1080p) SDIO
CMOS sensor Wi-Fi module
SPI/I 2C
Hi3516C V500
USB2
PC/USB flash drive
Photosensitive
ADC
component
MAC
FE PHY Ethernet cable
IR light PWM

UART 0 UART 1 GPIO SDXC

PTZ
Debug Alarm SD card
(RS485)

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 Hi3516C V500
Hi3516C V500 Professional Smart IP Camera SoC

Acronyms and Abbreviations

3DNR three-dimensional noise reduction
6DoF six degrees of freedom
AE automatic exposure
AEC acoustic echo cancellation
AF automatic focus
ALC automatic level control
ANR audio noise reduction
AVBR adaptive variable bit rate
AWB automatic white balance
CBR constant bit rate
codec coder/decoder
DC digital camera
DCG Dual Conversion Gain
DCI dynamic contrast improvement
DDRC double data rate controller
DPC defect pixel correction
DVR digital video recorder
EBOM engineering bill of materials
ECC error-correcting code
FPN fixed pattern noise
I 2C inter-integrated circuit
IR infrared
LCD liquid crystal display
LDC lens distortion correction
LSADC low-speed analog-to-digital converter
LSC lens shading correction
NNIE neural network inference engine
NR noise reduction
NVR network video recorder
OSD on-screen display
OTP one-time programming
POR power-on reset
PWM pulse-width modulation
RMII reduced media-independent interface
ROI region of interest
RTC real-time clock
SDIO secure digital input/output
SoC system-on-chip
SPI serial peripheral interface
TFBGA thin & fine ball grid array
TOPS tera operations per second
UART universal asynchronous receiver transmitter
VBR variable bit rate
VENC video encoding
VI video input
VO video output
WDR wide dynamic range

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Copyright © HiSilicon Technologies Co., Ltd.