microprocessor class 14
microprocessor class 14
PART 14
SIBIN K
• Only 4 bits of this register are used for this purpose, while rest of them is used for interrupt
control.
• TCON is an 8-bit register having address 88H
● TF1 bit is automatically set on the Timer 1 overflow.
● TR1 bit enables the Timer 1.
1 - Timer 1 is enabled.
0 - Timer 1 is disabled.
● IT1: External interrupt 1 type control bit. Set to 1 to enable INT1 to be triggered by falling
edge signal
Set to 0 to enable a low-level signal to generate an interrupt
● IT0: External interrupt 0 type control bit. Set to 1 to enable INT0 to be triggered by falling
edge signal. Set to 0 to enable a low-level signal to generate an interrupt
TMOD Register (Timer Mode)
● The TMOD register selects the operational mode of the timers T0 and T1.
● the low 4 bits (bit0 – bit3) refer to the timer 0, while the high 4 bits (bit4 – bit7) refer to the
timer 1.
● There are 4 operational modes
GATE1 enables and disables Timer 1 by means of a signal brought to the INT1 pin (P3.3):
● 1 – Timer 1 operates only if the INT1 bit is set.
● 0 – Timer 1 operates regardless of the logic state of the INT1 bit.
C/T1 selects pulses to be counted up by the timer/counter 1:
● 1 – Timer counts pulses brought to the T1 pin (P3.5). COUNTER
● 0 – Timer counts pulses from internal oscillator. TIMER
T1M1, T1M0 These two bits select the operational mode of the Timer 1