POWER OPTIMIZATION ANALYSIS OF

DIFFERENT SRAM CELLS USING

2021 IEEE 8th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON) | 978-1-6654-0962-9/21/$31.00 ©2021 IEEE | DOI: 10.1109/UPCON52273.2021.9667583

TRANSISTOR STACKING TECHNIQUE

K.L.V Ramana Kumari M. Asha Rani N. Balaji Sneha Kotha Murali Mohan Kota
Dept of ECE Dept of ECE Dept of ECE Dept of ECE Dept of ECE
VNR VJIET JNTU-H JNTU-K VNR VJIET VNR VJIET
Hyderabad, India Hyderabad, India Kakinada, India Hyderabad, India Hyderabad, India
[email protected] [email protected] [email protected] [email protected] [email protected]

Abstract— Nowadays optimization of power is a major

challenge in VLSI industry. As the density of the memory
systems increases, the power consumption also increases. II. OPERATION OF SRAM
SRAM cell is most fundamental component for all the memory The fig.1 shows the basic cell of the SRAM. The SRAM
devices like cache memories and CPU registers etc. The leakage operation is based on the performance of two CMOS
current of a transistor also leads to more power consumption. technologies connected in parallel. The cell of the SRAM has
So there is a need to reduce the power consumption in each cell 6 transistors, 4 transistors are cross coupled and that stores a
of a memory. In this paper, we focus on power optimization 1bit of data and other two transistors are the access
analysis of different SRAM cells using transistor stacking transistors that allows the data through the Bit Line-BL and
technique. Using this stacking technique, instead of using single
complementary Bit Line Bar- BLB[7-8]. When the Word
size transistor, we use two half size transistors. Here we
connect the transistors in series which are turned off. This Line -WL is high the data is read or write from the cross
reduces the leakage current which in turn reduces the power coupled transistors.
consumption of SRAM cell. In this paper power consumption is
analyzed for various SRAM cells with and without stacking
technique using at different voltages are simulated using
Hspice-A 2008.03 tool.

Keywords—Optimization of power, transistor stacking

method, 6T SRAM, 8T SRAM , 10T SRAM, leakage current.

I. INTRODUCTION
The demand for compact low power devices with high speed
such as smart phones, computers, laptops, etc. is steadily
growing. The memory is the main component in the
technologies that stores the data. As there consists of mainly Fig.1. The basic cell SRAM
RAM and ROM. The Random Access Memory (RAM) is a
memory where it can be stored and retrieved in non- III. TRANSISTOR STACKING APPROACH
sequential order. The Read Only Memory (ROM) performs
read function, writing data is slower. RAM is of two types
they are Static random access memory and Dynamic random
access memory[1-2]. The SRAM cell is made up of the two
CMOS transistors connected in parallel that stores the one bit
of data and other two transistors are the access transistors. The
two transistors for access control. SRAM cell data access is
faster and does not need to refresh the memory. DRAM cell
access data is slow and need to refresh the memory cell after
each reading of capacitor. DRAM cell consume less power.
Cell SRAM requires less area compared to cell DRAM. So,
mainly SRAM cell is used in the techniques to decrease the
power consumption. As the technologies are advancing the
power dissipation is also increasing, so it is necessary to
decrease the power consumption. The main theme in this work
is to decrease the power consumption by using transistor
stacking effect. In this transistor stacking method the
width/length ratio of the transistors are decreased as that of Fig.2. The transistor stacking approach
current decreases then dynamic power decreases then power
consumption decreases in SRAM cells[3-6]. The fig.2 shows the transistor stacking approach. In this
transistor stacking technique the original single transistor is
divided into two transistors. The occurring of stacking is
shown by considering the two NMOS transistors.

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 When the input is 0 the two NMOS transistors are off at once, IV. EXISTING SRAM CELLS
between both the transistors there occurs a sub-threshold
leakage current. That leakage occurred through the stacking in A. Conventional 6T SRAM
the two off NMOS transistors connected in series is lower The fig.4 shows the conventional 6T SRAM cell. The
thancompared with the single transistor. M5 and M6 are transistors to access. This transistor
gives the data access which are present in cells. When
Word Line (WL) is high access transistors start to
control. The transistors M2, M4, M1 and M3 forms the
VDD
two CMOS technologies that are connected back to back
and stores the one bit of data. It utilizes a one port for
read operation and write operation. The write operation
is done by previously charging the Bit Lines to there
related values and conforming the Word Line to
high[13].

Write Operation: To write a bit into the cell, the bit

line is low or high and the bit line bar is opposite to that
of the bit bar. Whenever word Line is one, the access
transistors will again changes data inside cell.
Gnd

Read Operation: The 2 bit lines are precharged to

Fig.3. The brief approach of transistor stacking method high. When the word line is set to high, the bit lines will
be moved down or will not change by considering of the
The fig.3 shows the brief approach of transistor stacking values in the both the nodes.
method by using of two NMOS transistors. A leakage current
depends on the voltages at the four terminals are source,
substrate, drain, gate of the NMOS[9-10]. By taking of the two
NMOS transistors at once. When two transistors A and B are
off at once, there forms a voltage node N in the middle of the
off transistors there forms the small drain current. The node N
in the middle of the off transistors has the below effects:

Because of the intermediate node N, the source to gate voltage

of the NMOS A becomes negative. Therefore, the sub-
threshold current decreases accordingly.

Because of the intermediate node N greater than zero, substrate

to source becomes negative, which then increasing in the Fig. 4. The conventional 6T SRAM cell
threshold voltage and decreasing the sub- threshold leakage of
A. B .Conventional 8T SRAM

The NMOS A decreases from drain to source, which results in The fig.5, shows the conventional 8T SRAM cell.
an increasing in the threshold voltage and decreasing the sub- The M7 and M8 are the transistors to access. This
threshold leakage of A. transistors gives the data access which are present in
cells. when Word Line (WL) is high the access
If only one NMOS or one PMOS device is off, all the transistors start to control. The transistors M2, M4,
transistors will be as short circuit but at the node of source M1, M3, M5 and M6 forms the two CMOS
voltage in the transistor which is off will be zero. So, the technologies that are connected back to back and the
leaking across the transistor which is off is large because of data is stored. The conventional 8T SRAM cell uses a
there is no self reverse biasing effect. If more number of only one port for two the read operation and write
transistors are off, the voltage of the source that transistor is operation.
off, when greater than zero the transistor one connected to
ground by transistors and the discharge will be definite by the
more positively opposite back bias in itself transistor. In the off
transistor the leakage of the reverse bias makes the very small
current[11-12].

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 Fig.5. The conventional 8T SRAM cell

C. Conventional 10T SRAM Fig. 7. The 6T SRAM with the stacking effect
The fig.6 shows the conventional 10T SRAM cell. The M5
and M6 are the transistors to access the data. This transistor During the cell not active state, the input point with the
gives the data access which are present in cells. when value zero attached to ground to the both transistors are
Word Line (WL) is high access transistors start to control. connected series that are turned off. Due to the stacking
The transistors M2, M4, M1, M3,M7, M8, M9 and M10 the leakage current decreases. Due to stacking, leakage
forms the two CMOS technologies that are connected back current passing by the way of the turned off transistors
to back and the data is stored. The conventional cell 10T in PMOS pull up path decreased. The node having the
SRAM utilize a single port to read operation and write value high it gets charged by large resistance that
operation. decreases present current and consumption of power.

B. 8T SRAM With Stacking effect

Fig.6. The conventional 10T SRAM cell

V. PROPOSED DESIGN Fig.8. The 8T SRAM cell with stacking effect

A. 6T SRAM with Stacking Effect

The fig.8 shows the 8T SRAM cell with stacking effect
of transistors. The M2, M4, M5, M9, M6, M10, M13,
The fig.7 shows the 6T SRAM with stacking effect of the M14 are the 8T SRAM cell. Stacking to the transistors
transistors. The M3, M4, M5, M6, M9, M10 are the 6T M7, M11, M8 and M12 are applied as NMOS pull down
SRAM cell. Stacking to the transistors M7 and M8 are transistors. Stacking to the transistors M1 and M3 are
applied as NMOS pull down transistors. Stacking to the applied as PMOS pull up transistors. During the cell not
transistors M1 and M2 are applied as PMOS pull up active state, the input point with the value zero attached
transistors.
to ground to the both transistors are connected series that
are turned off. Due to the stacking the leakage current
decreases. As to stacking, leakage current passing by the
way of the turned of fed transistors in PMOS pull up path
decreased. The node having the value high it gets charged
by large resistance, that decreases leakage

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 current and consumption of power.

C. 10T SRAM with Stacking effect

Fig.10. Simulation waveform for Conventional 6T SRAM

Fig. 9. The 10T SRAM with the stacking effect

Fig.9 shows the 10T SRAM with stacking effect of the Fig.11. Simulation waveform for Stacking 6T SRAM
transistors.TheM3,M4,M7,M8,M9,M10,M13,M14,M17,M1
8 are the 10T SRAM cell. Stacking to the transistors M11,
M12, M15 and M16 are applied as NMOS pull down
transistors. Stacking to the transistors M1,M2,M5 and M6
are applied as PMOS pull up transistors. During the cell not
active state, the input point with the value zero attached to
ground to the both transistors are connected series that are
turned off. Due to stacking the leakage current decreases.
Due to stacking, leakage current passing by the way of the
turned of fed transistor in PMOS pull up path decreased.
The node having the value high it gets the charged by large Fig.12. Simulation waveform for Conventional 8T SRAM
resistance that decreases current at present and consumption
of power.

VI. SIMULATION RESULTS AND CONCLUSION

The simulation wave forms for various power supply

voltages 1V,2V,3V,4V and 5V for both conventional
SRAM cells and with stacking effect SRAM cells are
analyzed and shown in the following Figures Fig.10, Fig.11,
Fig.12, Fig.13, Fig.14 and Fig.15 using H-Spice simulator.
Fig.13. Simulation waveform for Stacking 8T SRAM

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 Fig. 14. Simulation waveform for Conventional 10T SRAM
Fig.17. Variation of power with input voltage for conventional and
stacking 8T

Fig.15. Simulation waveform for Stacking 10TSRAM

The graphs below Fig.16, Fig.17, Fig.18 shows the

variations of power with input voltages for conventional
and stacking techniques. The power consumption of SRAM
cells using stacking technique is less comparative to the
conventional SRAM cells can be observed in graphs. Fig.18. Variation of power with input voltage for conventional and
stacking 10T

Table1: Comparison of conventional and stacking 6T, 8T, 10T SRAM cells
with different supply voltages

SRAM 6T 8T 10T
conventional 0.1505 mw 0.1943mw 0.1252mw
1v
Stacking 1v 0.1252mw 0.1022mw 0.0714mw

Conventional 0.1889mw 71.10uw 0.67498mw

2v
Stacking 2v 67.495uw 64.015uw 44.98uw

Conventional 42.99uw 19.625uw 19.48uw

3v
Fig.16. Variation of power with input voltage for conventional and stacking 6T Stacking 3v 1.949uw 19.447uw 19.41uw

Conventional 44.06uw 4.7uw 4.69uw

4v
Stacking 4v 4.69uw 4.65uw 4.60uw

Conventional 0.46uw 0.682uw 0.568uw

5v
Stacking 5v 0.36uw 0.537uw 0.478uw

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 VII. CONCLUSION
The power consumption of conventional SRAM cells
and stacking technique used SRAM cells of 6T , 8T, 10T has
been analyzed. In conventional 6T, 8T, 10T SRAM cells has
high power consumption due to sub-threshold leakage
currents. The effort to reduce the leakage current and power
consumption using stacking technique SRAM cells are
successfully executed by using Hspice-A 2008.03 tool.

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