• MCS-51 Instruction groups：

1. Data Transfer
2. Arithmetic Operation
3. Logic Operation
4. Boolean -Variable or Bit-Variable Operation
5. Program Branching

08-03-2025 Addressing Modes & Instruction Set-1

 Data Transfer

MOV destination, source ( MOV A, R0 )

XCH destination, source ( XCH A, R0 )

08-03-2025 Addressing Modes & Instruction Set-2

 Source and Destinations

Source
Destination
A
A
R0 ~ R7
R0 ~ R7
Data Memory
Data Memory
Program Memory
Stack
Immediate Data
DPTR
Stack

08-03-2025 Addressing Modes & Instruction Set-3

 Instruction Mnemonic ：
MOV : Internal Memory
MOVX : External Data Memory
MOVC : Program Memory
PUSH : Stack
POP : Stack
XCH : Internal Memory
XCHD : Lower 4-bit

08-03-2025 Addressing Modes & Instruction Set-4

 Rn : R0~R7
yyH : 8-bit address value
yyyyH : 16-bit address value
#xxH : 8-bit immediate data
#xxxwH: 16-bit immediate data
@Ri : R0 or R1
bit : bit address
rel : relative address

08-03-2025 Addressing Modes & Instruction Set-5

 Instruction Operation Op Code Format M/c's Example
MOV A, #xxH (A) ← xx 74 xx 2 bytes 12 (1) MOV A,#07H
MOV A, Rn (A) ← (Rn) E8-EF 1 byte 12 (1) MOV A,R0
MOV A, yyH (A) ← (yy) E5 yy 2 bytes 12 (1) MOV A,30H
MOV A, @Ri (A) ← ((Ri)) E6-E7 1 byte 12 (1) MOV A,@R0
MOV Rn, #xxH (Rn) ← xx 78-7F xx 2 bytes 12 (1) MOV R5,#07H
MOV Rn, A (Rn) ← (A) F8-FF 1 byte 12 (1) MOV R7,A
MOV Rn, yyH (Rn) ← (yy) A8-AF yy 2 bytes 24 (2) MOV R6,30H
MOV yyH, #xxH (yy) ← xx 75 yy xx 3 bytes 24 (2) MOV 30H,#10H
MOV yyH, A (yy) ← (A) F5 yy 2 bytes 12 (1) MOV 20H,A
MOV yyH, Rn (yy) ← (Rn) 88-8F yy 2 bytes 24 (2) MOV 20H,R5
MOV yyH, yzH (yy) ← (yz) 85 yz yy 3 bytes 24 (2) MOV 20H,30H
MOV yyH, @Ri (yy) ← ((Ri)) 86-87 yy 2 bytes 24 (2) MOV 20H,@R2
MOV @Ri, #xxH ((Ri)) ← xx 76-77 xx 2 bytes 12 (1) MOV @R2,#20H
MOV @Ri, A ((Ri)) ← (A) F6-F7 1 byte 12 (1) MOV @R2,A
MOV @Ri, yyH ((Ri)) ← (yy) A6-A7 yy 2 bytes 24 (2) MOV @R2,35H
MOV DPTR,#xxxwH (DPTR) ← xxxw 90 xx xw 3 bytes 24 (2) MOV DPTR,#1234H
MOVX A, @Ri (A) ← ((Ri)) E2-E3 1 byte 24 (2) MOVX A,@R1
MOVX @Ri, A ((Ri)) ← (A) F2-F3 1 byte 24 (2) MOVX @R0,A
MOVX A, @DPTR (A) ← ((DPTR)) E0 1 byte 24 (2) MOVX A,@DPTR
MOVX @DPTR, A ((DPTR)) ← (A) F0 1 byte 24 (2) MOVX @DPTR,A
MOVC A, @A+DPTR (A) ← ((A) + (DPTR)) 93 1 byte 24 (2) MOVC A,@A+DPTR
MOVC A, @A+PC (A) ← ((A) + (PC)) 83 1 byte 24 (2) MOVC A,@A+PC
PUSH yyH (SP) ← (SP) + 1 C0 yy 2 bytes 24 (2) PUSH 20H
((SP)) ← (yy)
POP yyH (yy) ← ((SP)) D0 yy 2 bytes 24 (2) POP 20H
(SP) ← (SP) - 1
XCH A, Rn (A) ←→ (Rn) C8-CF 1 byte 12 (1) XCH A,R1
XCH A, yyH (A) ←→ (yy) C5 yy 2 bytes 12 (1) XCH A,10H
XCH A, @Ri (A) ←→ ((Ri)) C6-C7 1 byte 12 (1) XCH A,@R1
XCHD A, @Ri (A) ←→ ((Ri)) D6-D7 1 byte 12 (1) XCHD A,@R1
08-03-2025 lower 4 bitsAddressing
(0-3) Modes & Instruction Set-6
 Arithmetic Operation
Instruction Mnemonic：
INC : 1 (increment)
DEC : 1 (decrement)
ADD : (addition)
ADDC : (add with carry)
SUBB : (subtract with borrow)
MUL : (multiplication)
DIV : (division)
DA : (decimal adjust accumulator)

08-03-2025 Addressing Modes & Instruction Set-7

 DIV AB (Division of unsigned numbers)
MOV A,#55
MOV B,#10
DIV AB
After division A = 5 (quotient) and B = 5 (remainder)

MOV A,#55
MOV B,#00
DIV AB

After division A = B = Undefined (OV flag = 1)

Note: CY = 0 in this instruction

08-03-2025 Addressing Modes & Instruction Set-8
 MUL AB (Multiplication of unsigned numbers)
MOV A,#5
MOV B,#8
MUL AB
After operation A = 28H (L-Byte) and B = 00H (H-Byte)

MOV A,#25
MOV B,#78
MUL AB

After operation A = 58H (L-Byte) and B = 11H (H-Byte)

Note: CY = 0 in this instruction; OV >1 if product > FFH

08-03-2025 Addressing Modes & Instruction Set-9
 Status of flags ：
INC : No flags affected
DEC : No flags affected
ADD : C, OV, AC
ADDC : C, OV, AC
SUBB : C, OV, AC
MUL : C=0, OV
DIV : C=0, OV

08-03-2025 Addressing Modes & Instruction Set-10

ADD A, #xxH (A) ← (A) + xx 24 xx 2 bytes 12 (1) ADD A,#07H
ADDC A, #xxH (A) ← (A) + (C) + xx 34 xx 2 bytes 12 (1) ADDC A,#70H
ADD A, Rn (A) ← (A) + (Rn) 28 - 2F 1 byte 12 (1) ADD A,R5
ADDC A, Rn (A) ← (A) + (C) + (Rn) 38 - 3F 1 byte 12 (1) ADDC A,R5
ADD A, yyH (A) ← (A) + (yy) 25 yy 2 bytes 12 (1) ADD A,07H
ADDC A, yyH (A) ← (A) + (C) + (yy) 35 yy 2 bytes 12 (1) ADDC A,70H
ADD A, @Ri (A) ← (A) + ((Ri)) 26 - 27 1 byte 12 (1) ADD A,@R1
ADDC A, @Ri (A) ← (A) + (C) + ((Ri)) 36 - 37 1 byte 12 (1) ADDC A,@R0
INC A (A) ← (A) + 1 04 1 byte 12 (1) INC A
INC Rn (Rn) ← (Rn) + 1 08 - 0F 1 byte 12 (1) INC R5
INC @Ri ((Ri)) ← ((Ri)) + 1 06-07 1 byte 12 (1) INC @R1
INC yyH (yy) ← (yy) + 1 05 yy 2 bytes 12 (1) INC 30H
INC DPTR (DPTR) ← (DPTR) + 1 A3 1 byte 24 (2) INC DPTR
SUBB A, #xxH (A) ← (A) - (C) - xx 94 xx 2 bytes 24 (2) SUBB A,#30H
SUBB A, Rn (A) ← (A) - (C) - (Rn) 98 - 9F 1 byte 12 (1) SUBB A,R5
SUBB A, yyH (A) ← (A) - (C) - (yy) 95 yy 2 bytes 12 (1) SUBB A,70H
SUBB A, @Ri (A) ← (A) - (C) - ((Ri)) 96 - 97 1 byte 12 (1) SUBB A,@R0
DEC A (A) ← (A) - 1 14 1 byte 12 (1) DEC A
DEC Rn (Rn) ← (Rn) - 1 18 - 1F 1 byte 12 (1) DEC R5
DEC @Ri ((Ri)) ← ((Ri)) - 1 16-17 1 byte 12 (1) DEC @R1
DEC yyH (yy) ← (yy) - 1 15 yy 2 bytes 12 (1) DEC 30H
MUL AB (A) ← [ (A) * (B)] 7~0 A4 1 byte 48 (4) MUL AB
(B) ← [ (A) * (B)] 15~8
DIV AB (A) ← int [(A) / (B)] 84 1 byte 48 (4) DIV AB
(B) ← mod [(A) / (B)]
DA A Decimal Adjust D4 1 byte 12Addressing
(1) DA
ModesA &
08-03-2025
Instruction Set-11
 Logic Operation
Instruction Mnemonic：
CLR : Register or address to 0
CPL : Register or Address to Complement
ANL : AND operation
ORL : OR operation
XRL : Exclusive-OR operation
RL : Rotate Left
RLC : Rotate Left with Carry
RR : Rotate Right
RRC : Rotate Right with Carry
SWAP: Register A 0-3 bits 4-7 bits

08-03-2025 Addressing Modes & Instruction Set-12

 Instruction Operation Opcode Format M/C's Examples
ANL A, #xxH (A) ← (A) AND xx 54 xx 2 bytes 12 (1) ANL A,#07H

Addressing Modes &

ANL A, Rn (A) ← (A) AND (Rn) 58-5F 1 byte 12 (1) ANL A,R5

Instruction Set-13
ANL A, yyH (A) ← (A) AND (yy) 55 yy 2 bytes 12 (1) ANL A,07H
ANL A, @Ri (A) ← (A) AND ((Ri)) 56-57 1 byte 12 (1) ANL A,@R0
ANL yyH,#xxH (yy) ← (yy) AND xx 53 yy xx 3 bytes 24 (2) ANL 10H,#30H
ANL yyH, A (yy) ← (yy) AND (A) 52 yy 2 bytes 12 (1) ANL 10H,A
ORL A, #xxH (A) ← (A) OR xx 44 xx 2 bytes 12 (1) ORL A,#07H
ORL A, Rn (A) ← (A) OR (Rn) 48-4F 1 byte 12 (1) ORL A,R5
ORL A, yyH (A) ← (A) OR (yy) 45 yy 2 bytes 12 (1) ORL A,07H
ORL A, @Ri (A) ← (A) OR ((Ri)) 46-47 1 byte 12 (1) ORL A,@R0
ORL yyH,#xxH (yy) ← (yy) OR xx 43 yy xx 3 bytes 24 (2) ORL 10H,#30H
ORL yyH, A (yy) ← (yy) OR (A) 42 yy 2 bytes 12 (1) ORL 10H,A
XRL A, #xxH (A) ← (A) XOR xx 64 xx 2 bytes 12 (1) XRL A,#07H
XRL A, Rn (A) ← (A) XOR (Rn) 68-6F 1 byte 12 (1) XRL A,R5
XRL A, yyH (A) ← (A) XOR (yy) 65 yy 2 bytes 12 (1) XRL A,07H
XRL A, @Ri (A) ← (A) XOR ((Ri)) 66-67 1 byte 12 (1) XRL A,@R0
XRL yyH,#xxH (yy) ← (yy) XOR xx 63 yy xx 3 bytes 24 (2) XRL 10H,#30H
XRL yyH, A (yy) ← (yy) XOR (A) 62 yy 2 bytes 12 (1) XRL 10H,A
RL A (A)n+1 ← (A)n n=0-6 23 1 byte 12 (1) RL A
(A)0 ← (A)7
RLC A (A)n+1 ← (A)n n=0-6 33 1 byte 12 (1) RLC A
(A)0 ← (C), C ← (A)7
RR A (A)n ← (A)n+1 n=0-6 03 1 byte 12 (1) RR A
(A)7 ← (A)0
RRC A (A)n ← (A)n+1 n=0-6 13 1 byte 12 (1) RRC A
08-03-2025

(A)7 ← (C), C ← (A)0

CLR A (A) ← 0 E4 1 byte 12 (1) CLR A
CPL A (A) ← (A)' F4 1 byte 12 (1) CPL A
SWAP A (A)3-0 ←→ (A)7-4 C4 1 byte 12 (1) SWAP A
 Boolean Variable Operation
It operates on single bit
Instruction Mnemonic：

CLR : Bit to 0
SETB: Bit to 1
CPL : Bit to its Complement
ANL : Bit and C flag :AND operation

08-03-2025 Addressing Modes & Instruction Set-14

 ORL : Bit and C flag : OR operation
MOV: Bit and C flag : Move operation
JC : C flag=1 ; Jump rel
JNC : C flag=0 ; Jump rel
JB : Bit=1 ; Jump rel
JNB : Bit=0 ; Jump rel
JBC : JB ; upon C flag=1

08-03-2025 Addressing Modes & Instruction Set-15

 MOV C,bit (C) ← (bit) A2 tt 2 bytes 12 (1) MOV c,30H
MOV bit,C (bit) ← (C) 92 tt 2 bytes 24 (2) MOV 30H,C
ANL C,bit (C) ← (C) AND (tt) 82 tt 2 bytes 24 (2) ANL C,30H
ANL C,/bit (C) ← (C) AND (tt)' D0 tt 2 bytes 24 (2) ANL C,/30H
ORL C,bit (C) ← (C) OR (tt) 72 tt 2 bytes 24 (2) ORL C,30H
ORL C,/bit (C) ← (C) OR (tt)' C0 tt 2 bytes 24 (2) ORL C,/30H
CLR C (C) ← 0 C3 1 byte 12 (1) CLR C
CLR bit (bit) ← 0 C2 tt 2 bytes 12 (1) CLR 30H
CPL C (C) ← (C)' B3 1 byte 12 (1) CPL C
CPL bit (bit) ← (bit)' D2 tt 2 bytes 12 (1) CPL 30H
SETB C (C) ← 1 D3 1 byte 12 (1) SETB C
SETB bit (bit) ← 1 C2 tt 2 bytes 12 (1) SETB 30H
JC rel if(C)=0,(PC)← (PC)+2 40 rr 2 bytes 24 (2) JC next
if(C)=1,(PC)← (PC)+rel
JNC rel if(C)=1,(PC)← (PC)+2 50 rr 2 bytes 24 (2) JNC next
if(C)=0,(PC)← (PC)+rel
JB bit,rel if(bit)=0,(PC)← (PC)+3 20 tt rr 3 bytes 24 (2) JB 30H,L1
if(bit)=1,(PC)← (PC)+rel
JNB bit,rel if(bit)=1,(PC)← (PC)+3 30 tt rr 3 bytes 24 (2) JNB 30H,L1
if(bit)=0,(PC)← (PC)+rel
JBC bit,rel if(bit)=0,(PC)← (PC)+3 10 tt rr 3 bytes 24 (2) JBC 30H,L1
if(bit)=1,(PC)← (PC)+rel (bit) ← 0
08-03-2025 Addressing Modes & Instruction Set-16
 Program Branching

Conditional and Un Conditional

Instruction Mnemonic：

ACALL : 2K bytes in Memory Map

LCALL : 64K bytes in Memory Map
RET : return from Sub Routine
RETI : return from ISR

08-03-2025 Addressing Modes & Instruction Set-17

 AJMP : 2K bytes in Memory Map Jump
LJMP : 64K bytes in Memory Map Jump
JMP : @A+DPTR
SJMP : Short Jump
JZ : (A)=0 Jump
JNZ : (A)!=0 Jump
CJNE : Compare and Jump if Not Equal
DJNZ : Decrement and Jump if Not Zero
NOP : No Operation

08-03-2025 Addressing Modes & Instruction Set-18

 DJNZ Byte, Target

CLR A
MOV R2, #25
LOOP: INC A
MOV P1,A
DJNZ R2, LOOP
CJNE Dest-Byte, Source-Byte, Target
MOV A, P1
CJNE A, #25, LOOP1
SJMP FINISH
LOOP1: JNC LOOP2
MOV R2,A
SJMP FINISH
LOOP2: MOV R3, A
FINISH:
08-03-2025 Addressing Modes & Instruction Set-19
 Instruction Operation Op Code Format M/C's

Addressing Modes &

(PC) ← (PC) + 2

Instruction Set-20
AJMP addr11 2 bytes 24 (2)
(PC)10-0 ← page address
LJMP yyyzH (PC) ← yyyz 02 yy yz 3 bytes 24 (2)
SJMP rel (PC) ← (PC) + 2 80 rr 2 bytes 24 (2)
(PC) ← (PC) + rel
JMP @A + DPTR (PC) ← (A) + (DPTR) 73 1 byte 24 (2)
JZ rel if (A) = 0,(PC) ← (PC) + rel 60 rr 2 bytes 24 (2)
if (A) <> 0,(PC) ← (PC) + 2
JNZ rel if (A) = 0,(PC) ← (PC) + 2 70 rr 2 bytes 24 (2)
if (A) <> 0,(PC) ← (PC) + rel
CJNE A,yy,rr (PC) ← (PC) + 3 B5 yy rr 3 bytes 24 (2)
if (A) <> (yy), (PC) ← (PC) + rr
if (A) < (yy), (C) ← 1
if (A) > (yy), (C) ← 0
CJNE A,#n,rr (PC) ← (PC) + 3 B4 yy rr 3 bytes 24 (2)
if (A) <> #n, (PC) ← (PC) + rr
if (A) < #n, (C) ← 1
if (A) > #n, (C) ← 0
CJNE Rn,#n,rr (PC) ← (PC) + 3 B8 yy rr 3 bytes 24 (2)
if (Rn) <> #n, (PC) ← (PC) + rr |
08-03-2025

if (Rn) < #n, (C) ← 1 BF

if (Rn) > #n, (C) ← 0
CJNE @Ri,#n,rr (PC) ← (PC) + 3 B6 yy rr 3 bytes 24 (2)
if ((Ri)) <> #n, (PC) ← (PC) + rr |
if ((Ri)) < #n, (C) ← 1 B7
if ((Ri)) > #n, (C) ← 0
 Instruction Operation Opcode Format M/C's
DJNZ Rn,rr (PC) ← (PC) + 2 D8 rr 2 bytes 24 (2)
(Rn) ← (Rn) - 1 |
if (Rn) <> 0, (PC) ← (PC) + rr DF
DJNE yy,rr (PC) ← (PC) + 2 D5 yy rr 3 bytes 24 (2)
(yy) ← (yy) - 1
if (yy) <> 0, (PC) ← (PC) + rr
ACALL addr11 (PC) ← (PC) + 2 2 bytes 24 (2)
(SP) ← (SP) + 1
((SP)) ← (PC)7 - 0
(SP) ← (SP) + 1
((SP)) ← (PC)15 - 8
(PC)10 - 0 ← page address
LCALL yyyzH (PC) ← (PC) + 3 12 yy yz 3 bytes 24 (2)
(SP) ← (SP) + 1
((SP)) ← (PC)7 - 0
(SP) ← (SP) + 1
((SP)) ← (PC)15 - 8
(PC) ← yyyz
RET (PC)15 - 8 ← ((SP)) 20 1 byte 24 (2)
(SP) ← (SP) - 1
(PC)7 - 0 ← ((SP))
(SP) ← (SP) - 1
RETI (PC)15 - 8 ← ((SP)) 32 1 byte 24 (2)
(SP) ← (SP) - 1
(PC)7 - 0 ← ((SP))
(SP) ← (SP) - 1
NOP (PC) ← (PC) + 1 00 1 byte 12 (1)

08-03-2025 Addressing Modes & Instruction Set-21

 Write a program to increment a content in an
external RAM of address 9000H
MOV DPTR,#9000H
MOVX A, @DPTR
INC A
MOVX @DPTR,A

08-03-2025 Addressing Modes & Instruction Set-22

 Write a program to add an array of 10 numbers starting from address
5000H and place the result in address 6000H

MOV DPTR,#5000H
CLR C
MOV R1,#10
MOV R0,#00
MOVX A,@DPTR
MOV R2,A
DEC R1
LOOP: INC DPTR
MOV A,@DPTR
ADD A,R2
JNC HERE
INC R0
HERE: DJNZ R1, LOOP
MOV DPTR, #6000H
MOVX @DPTR, A
MOV A,R0
INC DPTR
MOV @DPTR, A
HALT
08-03-2025 Addressing Modes & Instruction Set-23