Rahman, M 22~ Annual Microelectronic Engineering Conference.

May 2004

Design and Fabrication of Tri-Gated FinFET

Mohammed R.Rahrnan

Abstract- A Tn Gated Fin Field Effect Transistor is on of l.Introduction:

the many novel devices that may be replacing planar
MOSFETs, by reducing short channel effects. The 1.1 Need for FinFET
FinFET has emerged as one of the most promising double
gate structures primarily because of its ease of The scaling of planar MOS is approaching the practical limits.
manufacturing. There are still significant challenges to With the scaling of the channel length below SOnm complex
overcome it in order to make the process available channel profiles are required to achieve desired threshold
commercially. The Tri-Gated FinFET is tri-gated meaning voltages and to eliminate short channel effects. Some of the
that the gate overlaps the top and the two sides of the FIN. proposed bulk structures for SOnm and beyond include Silicon
Three dimensionally the gate depletes three surfaces of the on nothing (SON-planar ultra thin dual gate), Vertical MOS,
FIN, which results in a higher drive current relative to a Delta Doped MOSFET, etc. In all these structures, bulk
planar MOSFET. In order to reduce current crowding in doping concentration need to be increased to suppress the
the Fin corners, we have curved the corners using oxide short channel effect; this degrades mobility, worsens sub-
etch back process. FinFETs has been built previously at threshold swing and increase parasitic junction capacitance
Rochester Institute of Technology. We have designed and [1]. Essentially, the short channel effect reflects the extent of
fabricated Tri-Gated FinFETs of various geometries. drain-bias influence on channel potential. In order to increase
Electrical test showed poor performance of the devices. gate control electrostatics, the entire channel semiconductor
Proper scrutiny of the electrical results and the SEM needs to be “brought closer to the gate” [1]. SOT (silicon on
micrographs allowed us to conclude that if LTO or Nitride insulator) technologies such as Full-Depleted, Ground-plane
is used as etch hard mask for silicon fin etch, electrical and Double gate achieve this by using a thin silicon film
results closer to that of an ideal NMOS transistor could controlled by one or more gates [1]. Researchers have shown
would be achieved. through extensive Monte Carlo simulations that multi-gated
structures are scalable to the lowest channel length for a given
Key Words: FinFET, MOSFET, SOl, Ion Implant, DIBL insulator thickness [2]. The FinFET is a dual or tri-gated
and Ballistic Transport. structure that has become one of the most important choices
for its ease
of manufacturability using well-understood Planar MOS implantation defines the BOX depth and the BOX thickness
process steps. is limited to about 0.Sum.
• If additional Si thickness is required, an epitaxial Si
1.2 Silicon-On-Insulator (SOl) Substrate layer can be grown to provide this additional
thickness. [3]
The figure 1 below shows the cross section of a SOl wafer.
From the above process steps, it is seen that the BOX height is
H ~h ~>uc~ O~ kept fairly low, and the reason for this is that the BOX is not a
good thermal conductor. Thus the heat does not dissipate
properly with thick BOX.

~jjjj~ ~ ~ :~o~ i;~tvrn~ l.3The FinFET

Figure 1. SOl Wafer The figure 2 below shows the tilted 3-D cross section of the
Fin-FET.
bne of the most common ways to manufacture SOI wafers is
by using SIMOX technology. The following process steps are
done to make a SOI wafer [3].
Drain
• The starting material is typically a (100) device quality
wafer. The wafer is first subjected to a high dose (-2 x
1O’°/cm2) oxygen (Of) ion implantation step at high enough
energy (1 50-300KeV) so the peak (projected range) of the
implant is deep within the silicon) 0.3-0.Sum). This step is
usually carried out with the wafers held at >400°C to ensure
that the silicon maintains its crystallinity during the
implantation.
• The wafers are given a post-implant anneal in N, for
sufficient time (3-5 hours) at a relatively high temperature
(1100-1175°C). This step forms a buried oxide (BOX) layer
of silicon dioxide near the peak of the implantation and
removes any many of the defects (dislocations) formed
Bulk Si
during the ion implantation step. The depth of the ion

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Rabman, M 2 2’~ Annual Microelectronic Engineering Conference, May 2004

Figure 2. 3D Tilted Cross Section of the FinFET [4] 2.1 Mathematical Modeling of the FinFET.

Reference [5] describes initial framework of the FinFET

Figure 2 above shows the 3D tilted cross section of the Fin model with given constraints and the results are applicable for
FET. The gate overlaps the fin from 3 sides. It is a type of Tn any kind of double gate MOSFET. For simplicity, the
gated MOSFET. The initial silicon doping before patterning is important results are written in the paper. I have modified a
the same as the bulk substrate as shown above in the SOl number of equations of reference 5 for simplii~’ing the models
manufacturing. Like to only symmetric Double Gate/ FinFET structure. Figure 3b
[ref 5] shows the 3D view of the FinFET showing only the
the conventional planar MOS the fin under the gate is silicon Fin and the two gates and figure 3b is a top down
externally undoped. The rest of the silicon is doped with schematic.
opposite polarity similar to a planar MOS. If the starting
substrate were p-type 100 orientation SOl, the Fin and the
source/drain would be doped with n-type dopants. The region
under the gate would remain at the doping level of the starting
material. At the assigned turn on gate voltage, channel would
be formed in three faces of the fin, which further will define
the FinFET state of operation. It has to be understood that
three surfaces are getting inverted unlike single surface
inversion of a planar MOSFET. The gate is high-doped
n+polysilicon or insitu doped SixGey which will be discussed
FI~FF.T
in the later sections. Our FinFet Gate metal was n+polysilicon.
Figure 3a. FinFET
2.Theory Schematic of the FinFET.
I ______

The FinFET is a symmetric three-gate structure. This means $

that both the front back and the top gates have the same work It.
function and are tied to the same bias, so all the three surface
channels turn on at the same time. In this section the cr~
mathematical modeling of the symmetric double gate
MOSFET/ FinFET Electrostatics are first explained which is
followed by the Design theory, Scaling effects. Mathematical
modeling for a tni-gated FinFET is still under investigation
and no journal has been published. It will be similar to that of Figure 3b.2D Top Down
a DG-FinFET and the only difference will be an addition of a In the modeling, current for the two interfaces are calculated
top transistor to the DGFinFET modeling results. The separately and added together. W or the width is the height of
modeling of the top gate in the first order will just be an the FinFET .The vertical charge distribution provides a weigh
addition of a transistor, which is the same as a planar to form a weighted sum of the contribution from the 2 currents
MOSFET, with the width of the Fin defining the width of the at the 2 surfaces [5].
planar MOSFET. Thus for simplicity, we derive the current
equations for a DG-FinFET in the next subsection. The drain current at one of the surfaces is given by

ni =1+1
( c. (J~)
S,
.~

(3)
~ ~ Wq1 ~~ + C~j
An expression for current in terms of charge is obtained as
where q1 is the normalized inversion layer charge given by
~ V~h is the quasi Fermi potential in the channel and
the current flows in the positive y direction. The inversion
charge in the channel can also be expressed by ‘Dt= ~ (1 +

q1 (~ )= q10 exp[~ U’) L

/
))~ ~ni
Integrating (4~ from source to drain, the drain current is
explicitly given by

/~fl7q~_q~
~
where Vth is the same as or kT/q.

In the original modeling of reference 5, the two gates were where qs and q~ are the normalized charge at the source and
considered to be asymmetric and thus to account for that an drain respectively. The author has modified equation (10) of
ideality factor of n1 was used. For the case of the FinFET the reference 5 to get the analytical solution for q1. Equation 6
n1 term can be reduced to equation (3) as shown below. below is an analytical solution for q~.

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Rahrnan, M 22’~ Annual Microelectronic Engineering Conference, May 2004

q1=n11n~
mvG 1
-~

T_V1 6~ This is a small sub section, which talks about the design rules
of the FinFET design. The design rule details are presented in
L ft reference 1. In this section the design rules are summarized
from reference 1
In order to solve for the qs and q~ the V~h has to be replaced
by the source and the drain voltage respectively. \4 is the Fin Thickness [1]:
threshold voltage, which is given by equation (7) below.
As channel length decreases, fin thickness and oxide thickness
must be decreased to maintain gate control, in accordance with
VT = 2VFB + + ~NAtsf[ CSI±CoX (7) scaling rules based on natural length [11 the following design
rule will have be followed.

In equation (7) t5, is the width of the Fin and ~/~B is the fenni x Length of Fin under Gate ≥ Fin Thickness (8)
potential. It can be seen that the C0~ and Cn are in series. x Fin Thickness ≥ Thickness of Gate Oxide (9)
2.2 Design Theory and Dimensions:
Fin Height [1]: Where pitch is the horizontal gap between two fins.

The height (h) of the FIN represents the channel width of a Source/Drain Resistance:
single-fin transistor as illustrated in figure 2. The current 1~
for conventional and FinFET transistor technologies (I~~ = on- Source/Drain extension resistance is a significant component
current per unit channel width) is proportional to the channel of parasitic series resistance. The cross sectional area of the
width as shown in equation 5. Thus for a single-fin FinFET source/drain extensions is determined by the FIN thickness
would be proportional to [1]. Common methods of reducing source/drain series
resistance is by raising the S/D, ex-situ doping of fin area
~I~s a. (2 x h)+ WFIN (CL is the sign of proportionality) excluding the area under the gate and silicidation of
(10) source/drain contact.

Where ‘h’ is the height of the fin and the width of the side
channels. If more fins are placed the right side of equation has 3. Designs and Fabrication:
to be multiplies by the number of FiNs. The equation becomes

1DS CL [(2 x h)] x nnns ~ is the number of Fins) + nflflWFJN FinFETs of various geometries were designed. The smallest
(11) device had a Fin Width of 0.5um and Gate Width of O5um.
FinFETs of other geometries were also included in the mask.
From the above equation it can be seen that increasing the FETs with multiple fins were also included. Below are
number of FINs can increase the drive current. fabrication process steps listed in sequence starting from Level
1 the Alignment Level.
If multiple FINs are used, the following conditions has to be
used: 1 .Starting Substrate: 100 P-type silicon wafer with BOX
thickness of 2300 and Silicon thickness of 3750.
2 Xh≥pitch (12)
2. Lithography Level 1: Alignment Marks Patterning.

3.Aligmnent marks were patterned, and finally etching the loading effect, the etch time was very different from the target
3750A silicon using reactive ion etching transferred the image etch time.
and the 2300A BOX using buffered oxide etching.
6. Resist Ash in Branson Asher.
4. Lithography Level 2: Source/Drain FIN Patterning.
7. After the Resist ash was done, a sacrificial Si02 of thickness
5. After the Level 2 was patterned, the silicon Fin, source and one l60Angstrom was grown. The Sacrificial Oxide was then
drain, masked by OiR62O positive photoresist were etched etched away using Hydrofluoric Acid Chemistry. This step
down to BOX, using DytTech Quad Reactive Ion Etching. In was done for two reasons. Firstly for rounding the corners for
order to etch the silicon completely in the unmasked area, the the Fin/Fins so that current crowding or spreading resistance
following etch recipe had to be used. effects can be prevented. The next reason was to prepare the
surface for the gate oxide.
RF Forward: l8SWatts
Pressure: l7mTorr 8. Gate oxide of S80Angstrom was grown using the Bruce Dry
SF6: 17SCCMs Oxide Furnace. For the prevention of Fixed Charges, nitrogen
CHF3: 14SCCMs annealing was done after growth step.
Etch Time: 14.5 Minutes.
9. Poly Silicon of thickness 2300Angstrom was deposited
Different pattern density mask was used while doing the using Low Pressure Chemical Vapor Deposition.
process development of this recipe, but due to severe micro

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Rabman, M 22’~ Annual Microelectronic Engineering Conference, May 2004

10. Level 3 Lithography: Gate Patterning showed very poor performance. Figure 4 below shows the
drain family of curves for one of the FinFETs.
11. After the gate was patterned, the polysilicon in the
unmasked area was etched using the Dry Tech Quad Reactive
~ no ~
Ion Etcher Etcher. The etch recipe was as follows:

RF Forward Power: 1 85Watts —

SF6: 30 SCCMs
CHF3: 30 SCCMs
Pressure: 43mTorr I v~c
Etch Time: 2 minute 10 seconds.
12. Resist Ashing in Branson Asher was done using oxygen
plasma.
I
511 111 ‘11’
13. Ion Implantation for Self-Aligned Source/Drain and Gate:

Ion-Implant of phosphorus using the Varian 350D ion Figure4: Drain Family of Curve for a NFET FinFET.
implanter was done to introduce dopants into the polysilicon
gate and source/drain. In order, to prevent channeling and A proper scrutiny of figure 4 shows that, current flows only
implant damage the implant in the Source/Drain are was done had very high Vds. The current flow decreases as the gate bias
through the 580Angstrom dry oxide. The implant conditions is increased. All the other transistors showed similar
were as follows: performance. In order to further investigate the results, we
took high magnification scanning electron micrographs of the
Implant Specie: P31 devices. Figure 5 shows the SEM micrographs:
Implant Energy: 6OKeV
Implant Dose: 1 x 1015/cm2 r”o’iaqined Rahmai
~t Wa
~ ~%.
14. Activation of the Dopant Ions.

Annealing the wafer at 1000° C for 1 5minutes in the ftirnace

activated dopant ions.

15. Oxide Etch:

Oxide in the Source/Drain area etched using Hydrofluoric

Acid base etchant.

1 6.Aluminum Deposition:

The source/drain contact area was slightly bigger than the

probe contact are. Thus a separate contact mask was not used.
To make an ohmic contact with the sour/drain 2000 Angstrom
of aluminum was deposited by evaporation using the CVC
evaporator. The base pressure of the evaporation process was
4.2 x l06 Ton.

17. Level 4 Lithography: Metal Patterning:

Aluminum in the Source/Drain and Polysilicon contact area

were masked using photoresist.

18. Aluminum Etch:

Wet Aluminum Etch was done in the unmasked areas using

phosphoric acid based chemistry. The etch time was Figure Sb: FinFET of 0.5 gate length and 0.8um Fin
47seconds, which includes a 100% over etch.
Investigation of the electrical results show that, there were
19: Sintering: large pits and holes in the silicon fin and the source drain
areas. This pit and holes came from the second level etch, that
To make the contact ohmic, the wafer was sintered in the is the etch of the Source/Drain and Fin as described in the
furnace at 450°C in Forming Gas ambient. process flow. The pits and the holes pattern got transferred in
the other levels. Another FinFET projected was conducted
4. Electrical Results and Analysis: with my project [6], which used low temperature oxide as a
hard mask to etch the silicon Fin. A SEM micrograph of the
Electrical tests were done using the Keithly 8200 other project using LTO as a hard mask after the Source/Drain
Semiconductor Parameter Analyzer. The electrical results and Fin etch is shown in figure 6.

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Rahrnan, M 22~ Annual Microelectronic Engineering Conference, May 2004

7.References:

[1] , Han Ananthan ,FinFET — Current Research Issues,

School of Electrical and Computer Engineering, Purdue
University, West Lafayette, Indiana 47907

[2]D.J Frank, S.E. Laux, and M. V. Fischetti, “Monte Carlo

Simulation of 3Onm dual Gate MOSFET: how short can Si
go?” in IEDM Tech. Dig., 1992, pp 553-556

[3]S.Wolf & R.N.Tauber, Silicon Epitaxial Film Growth and

Silicon on Insulator, Volume 1, Silicon Processing for VLSI
—~ Era,200l

Figure 6: O.Sum FiiiFET reference [6] [4] Mohamed Rahman & S.Rornmel, Discussion Note

Figure 7 below show the electrical results of the second [5] A Framework for Generic Physics Based Double-Gate
groups’ device: MOSFET Modeling, Mansun Chan 1, Yuan Taur, Chung
Hsun Lin, Jin He, Au M. Niknejad and Chenming Hu
&~
~~ [6] Process Flow and Electrical Results, Branislav Curanovic,
UL~2~ V

~a€a1
~~~zEzzzEzEEZ.
~a .

~ V_VV_VVVVVVVV~
~

~ ‘V~
‘snn V

a~
~a”.u V V —

~5E4~ ~
• :V ~

V.~t~1

Figure 7: Electrical Result of FinFET [6]

After investigating and analyzing the results we can say that

photo resist alone is not a sufficient etch mask.The other
group’s FinFET works because it is protected by a separate
hard etch mask. The Roughness caused holes and voids to be
fonned through the box. The roughness also transferred to the
Polysilicon Gate. As a result, the fin was highly resistive and
the metal short-circuited with the silicon under the BOX. This
caused Current Flow from under the Box at high Vds.
Further Field Effect due to increasing Vgs, reduced the current
flowing under the gate.

5.Conclusion:

Oir620 Resist is not sufficient to mask the silicon etch due to

its poor selectivity. This results in highly resistive Fin. We
learned that a hard mask like LTO or silicon nitride has to be
used for the silicon fin Etch.

6. Acknowledgements:

Santosh Kurinec
Branislav Curanovic
Sean Rommel
Yaser Alshehri
Jay Cabacungan
Charles Gruener
Scott Blondell
Bruce Tolleson
Entire SMFL Staff

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