Lab 09 - Routing and Post-Route Optimization
Objective : To get familiarized with the Routing and post-route optimization in Fusion
Compiler
Working Directory : /home/<samraj>/PD_LABS/FC/lab09/
Project Name : ORCA_TOP.dlib
Learning outcomes:
Perform routeability checks on a placed designwith clock trees
Apply routing options
Route secondary PG nets
Control via optimization
Perform route and post-route optimization
Analyze the design for timing with SI enabled, and perform incremental power and
crosstalk optimizations.
Task 1: Load and Check the Post-CTSdesign
Invoke Fusion Compiler from the lab_9 directory and load the post-CTS design
UNIX% cd lab_9
UNIX% fc_shell -gui -f load.tcl
The script will make a copy of the clock_opt block and open it.
To generate the timing QoR summary use the command:
report_qor -summary
Question 1: Is timing acceptable for routing?
Ans . yes but need some requriements
Task 2: Route the design
To support a more immersive and interesting lab experience, there are no step-by-step
instructions for this lab.
Instead, you are asked to open the file run.tcl in an editor (or using the FC Script
editor), and exercise the commands line by line.
We are specifically asking you not to just source the entire file, as this would defeat the
purpose. which is to understand how all the options and commands play together. If
there is an option that does not make sense, have a look at its man page.
The following sections provide additional information and comments. The sections are
ordered in such a way that you can refer to them as you go through the script.
If you like, you can diverge from the commands in run. tcl, or you Could try different
efforts, different settings, etc. (you are encouraged to experiment.)
The following section is designed to be a guide through the lab. It contains information
on the items that have to be configured and run
Pre-routing checks - Before you route the design, it is best to ensure that there are no
issues that will prevent the router from doing its job.
Question 2: Is the design ready for routing ?
Ans .yes it is ready for routing
Information: Starting 'route_auto' (FLW-8000)
Information: Time: 2023-07-19 21:09:07 / Session: 0.70 hr / Command: 0.00 hr / Memory: 2781 MB (FLW-
8100)
Generating Timing information
Design Scenario func.ss_125c (Mode func Corner ss_125c)
Estimated unitRes/unitCap :
Layer M1 : Res 2 ohm/um Cap 0.149907 ff/um
Layer M2 : Res 1.78571 ohm/um Cap 0.152807 ff/um
Layer M3 : Res 1.78571 ohm/um Cap 0.10377 ff/um
Layer M4 : Res 1.78571 ohm/um Cap 0.10376 ff/um
Layer M5 : Res 0.357143 ohm/um Cap 0.090434 ff/um
Layer M6 : Res 0.357143 ohm/um Cap 0.0904285 ff/um
Layer M7 : Res 0.0892857 ohm/um Cap 0.0888719 ff/um
Layer M8 : Res 0.0892857 ohm/um Cap 0.0880677 ff/um
Layer M9 : Res 0.0125 ohm/um Cap 0.102767 ff/um
Layer MRDL : Res 0.175 ohm/um Cap 0.107256 ff/um
Generating Timing information ... Done
Information: The net parasitics of block ORCA_TOP are cleared. (TIM-123)
Warning: Cell contains tie connections which are not connected to real PG. (ZRT-511)
Cell Min-Routing-Layer = M1
Cell Max-Routing-Layer = M9
Found antenna rule mode 4, diode mode 2:
layer M1: max ratio 1000, diode ratio {0.06 0 400 40000}
layer M2: max ratio 1000, diode ratio {0.06 0 400 40000}
layer M3: max ratio 1000, diode ratio {0.06 0 400 40000}
layer M4: max ratio 1000, diode ratio {0.06 0 400 40000}
layer M5: max ratio 1000, diode ratio {0.06 0 400 40000}
layer M6: max ratio 1000, diode ratio {0.06 0 400 40000}
layer M7: max ratio 1000, diode ratio {0.06 0 400 40000}
layer M8: max ratio 1000, diode ratio {0.06 0 400 40000}
layer M9: max ratio 1000, diode ratio {0.06 0 8000 50000}
layer MRDL: max ratio 1000, diode ratio {0 0 1 0 0}
layer CO: , diode ratio {0 0 1 0 0}
layer VIA1: max ratio 20, diode ratio {0.06 0 200 1000}
layer VIA2: max ratio 20, diode ratio {0.06 0 200 1000}
layer VIA3: max ratio 20, diode ratio {0.06 0 200 1000}
layer VIA4: max ratio 20, diode ratio {0.06 0 200 1000}
layer VIA5: max ratio 20, diode ratio {0.06 0 200 1000}
layer VIA6: max ratio 20, diode ratio {0.06 0 200 1000}
layer VIA7: max ratio 20, diode ratio {0.06 0 200 1000}
layer VIA8: max ratio 20, diode ratio {0.06 0 200 1000}
layer VIARDL: max ratio 20, diode ratio {0 0 1 0 0}
Warning: Cannot find a default contact code for layer CO. (ZRT-022)
Skipping 4 internal pins that are not physical. Set route.common.verbose_level to > 0 and run routing command
to get skipped pin names.
Info: number of net_type_blockage: 0
Found 1 voltage-areas.
When applicable Min-max layer allow_pin_connection mode will allow paths of length 3.55 outside the layer
range.
Warning: Standard cell pin LSUPX2_HVT/VDDL has no valid via regions. (ZRT-044)
Warning: Standard cell pin LSUPX1_RVT/VDDL has no valid via regions. (ZRT-044)
Warning: Standard cell pin LSUPX4_HVT/VDDL has no valid via regions. (ZRT-044)
Warning: Standard cell pin LSUPX8_HVT/VDDL has no valid via regions. (ZRT-044)
Warning: Standard cell pin LSUPX2_RVT/VDDL has no valid via regions. (ZRT-044)
Warning: Standard cell pin LSUPX1_LVT/VDDL has no valid via regions. (ZRT-044)
Warning: Standard cell pin LSUPX8_LVT/VDDL has no valid via regions. (ZRT-044)
Information: Skipping global routing as it has already been run in the global_route_opt stage of clock_opt.
(ZRT-607)
Antenna definitions are commonly supplied in a separate TCL file, specific to the technology, using the
following commands (these are the same commands used in ICC II)
define_antenna_rule
define_antenna_layer_rule
define_antenna_aréa_rule
define_antenna_accumulation_mode
define_antenna_layer_ratio_scale
In addition, there are application options that control how antenna violations are handled.Use the
report_app_options command shown in run. tcl.
To check the Antenna effect use the commands:
source -echo ../ref/tech/saed32nm_ant_1p9m.tcl
report_app_options route.detail.*antenna*
Crosstalk Prevention
Crosstalk prevention tries to ensure that timing-critical nets are not routed in parallel over long
distances.
Prevention can occur in the global routing and the track assign stages.
The current recommendation is to enable prevention during the track assigns stage only.
In order for crosstalk prevention to occur, crosstalk (or signal integrity) analysis must also be enabled.
To make post-route analysis and optimization more interesting (showing SI violations that need to be
fixed during route_opt), you can choose to do that “artificially” by not enabling SI analysis during
routing.
Routing, DRC Analysis
At this stage, we will route all signal nets that have not been routed previously.
Any signals that have been routed already (clocks, secondary PG) will not be touchedagain if they are
DRC clean.
Auto-routing runs track assignment and detail routing.
Global routing was already completed during the clock_opt final_opto stage.
Question 3: How many detail route iterations are run by default? (Hint: Review the man page for route_auto)
Ans , the number of detail route iterations to 20, you would add the following line to the routing configuration
Question 4: How do you change the default, and how do yu force the router to run through all iterations even
though the router might not see any improvements? (Hint: report_app_options *itreat*)
Ans . To change the default number of detail route iterations, you can edit the routing configuration file. The
location of the routing configuration file is typically specified in the routing.config file.
Examining Routing Design Rule Violations
Use the error browser to visualize any routing violations in the GUI that may have been left over. On
the top toolbar, select the button for the error browser.
In the popup, select zroute.err and click on Open Selected in the new window, you can select the
errors from the list, which causes the layout view to zoom to that violation.
Signal Integrity
Signal integrity analysis should be turned on before routing. This will instruct the extraction engine to
extract cross-coupling capacitances, and instruct the router to perform timing analysis with delta
delays using these coupling capacitances. This is important when performing timing-driven routing.
For this lab, if you left SI analysis off before auto-route, turn it on afterwards to see the SI effects, and
to allow Sl-related violations to be fixed during route_opt.
For better correlation with PrimeTime, you should also enable timing window analysis, as shown in
the script.
Post-Route Optimization
For best correlation with PrimeTime, you should enable PT delay calculation, as well as StarRC
fusion extraction.
For timing analysis, you can also use path-based analysis, which is much more accurate at this stage of
the design.
Post-route optimization is performed using route_opt, which performs timing, logical drc, area, and
(optionally) CCD and power optimization.
There are application options, you have to set to enable CCD and Power optimization.
