iPD: An Open-source intelligent

Physical Design Toolchain

Xingquan Li, Simin Tao, Shijian Chen, Zhisheng Zeng, Zhipeng Huang, Hongxi
Wu, Weiguo Li, Zengrong Huang, Liwei Ni, Xueyan Zhao, He Liu, Shuaiying Long,
Ruizhi Liu, Xiaoze Lin, Bo Yang, Fuxing Huang, Zonglin Yang, Yihang Qiu,
Zheqing Shao, Jikang Liu, Yuyao Liang, Biwei Xie, Yungang Bao, and Bei Yu

Jan. 23 2024
01 Introduction

02 iPD Design Mode

03 iPD Toolchain
 Chip Design Flow
System Architectural
Functional Design Logic Synthesis Tech Mapping
Specifications Design
module conv;
reg [31:0] m[0:8192]; 
reg [12:0] pc; X Y
reg [31:0] acc; 
reg[15:0] ir;

always
begin D
ir = m[pc];
if(ir[15:13] == 3b’000)
pc = m[ir[12:0]];
else if (ir[15:13] == 3’b010)
acc = -m[ir[12:0]];
...

Sign-off
Package and Test Fabrication Layout Processing Physical Design
Verification

Timing, Power, DRC,

ERC, LVS
 Challenges and Chances
⚫ Challenges
⚫ Moore's Law
⚫ Gap between academic and industrial
⚫ Innovation more difficult
⚫ Design rules are evolving

⚫ Chances

Open-source AI
 Open-source EDA Tools
Design Module Design Step Some Commercial Tools Some Open-source Tools iEDA
HLS HLS Stratus Catapult Prime LegUp GAUT PandA FCUDA XLS
Logic Simulation VCS Xcelium QuestaSim Verilator GHDL FreeHDL TkGate
Simulation FineSim/Hspice/Custo
Circuit Simulation Spectre NGSpice mixedsim GnuCap Qucs XICE
Verification mSim ModelSim
Debug Verdi/SpyGlass Indago/litmus Veloce
Logic Synthesis Yosys ABC LLDHL UNIVR iLS
Logic Synthesis Design Compiler Genus EPFL-LS-Lib
Tech Map Oasys-RTL ABC iMap
DFT DFT DFT Compiler Modus Tessent Max Fault
Formal Formal Formality/CDC JasperGold
Partition PartitionMgr METIS KaHyPar MPPart iNO
OpenRoad
Floorplan OpenRoad Parquest iFP
TritonMacroPlacer
PDN Fusion Compiler OpenPDN iPDN
ICC2 RePlace
Placement DreamPlace Graywolf Capo iPL
Physical Design Prime ECO Innovus Calibre OpenDP
CTS Xtop/Xtime DesignEnhancer TritonCTS iCTS
Timing OPT TritonSizer Gate-Sizing iTO
FastRoute CUGR BoxRouter/FG
Routing Qrouter NTHU-Route iRT
TritonRoute Dr.CU R/ORGE
ECO OpenRoad-eco iECO
STA PrimeTime Tempus OpenSTA OpenTimer iSTA
RCX StarRC Quantus OpenRCX SPEF-Extractor iRCX
Signoff PowerPro/mPo
Power OpenRoad-pp iPA
PrimePower/redhawk Voltus/Joules wer
IR Drop PDNSim IREDGe iIR
DRC ICV Klayout iDRC
Magic
Physical Verification Antenna Pegasus Calibre OpenRoad-ant
LVS Netgen
Validation Validation Validator
MPL
Layout Synthesis RET/ILT Calibre
Mask Generation
 A Promising Open-source Precedent
⚫ OpenROAD: No Humans, 24 Hours
⚫ Efabless-OpenLane: RTL2GDS Digital Flow

From “Andrew B. Kahng, The OpenROAD Project: Today and Beyond, 2022”
 Our Motivation
⚫ Open-source EDA situation
⚫ Most existing open-source EDA tools only support one algorithmic approach. For complex EDA
systems, a basic consensus is that no algorithm can perform best for any case.
⚫ Additionally, existing open-source EDA tools face challenges in reliability, extendibility, ease-of-use.
These situations discourage contributors and users from open-source projects.
⚫ Besides supporting chip design, a more important objective of open-source EDA tools is to provide a
EDA tool R&D platform for EDA researchers and tool developers.
⚫ Most open-source EDA tools are developed and maintained by some professors and students in
academia. Initially, the code for some tools often comes from research papers.

⚫ The motivation of iPD

⚫ The iPD project aims to attract diverse academic disciplines, and foster collaboration, and bridge the
gap between industry and academia, and facilitate the development of EDA design methodologies
⚫ To support various algorithmic solutions, the iPD needs to be highly extendable and has a solid EDA
foundation and evaluation system, and providing long-term support.
⚫ iPD is designed to construct open-source EDA tools and algorithm sets, with the aim of designing
more extensible EDA tools at minimal cost.
01 Introduction

02 iPD Design Mode

03 iPD Toolchain
 EDA Decomposition
⚫ physical design -> multiple tools -> sub-tools -> steps -> algorithms
Modules Tools Sub-tools Steps Algorithms
Logic compiling Scheme 1
RTL design Initial placement
Logic optimization Assign cell to region
Simulation Greedy
Tech mapping Global placement
/Verification Cell respreading
Floorplan Post global Tetris
Logic placement
Placement Align cell to row
synthesis Abacus: Dynamic
CTS Legalization programming
Reorder cell in a row
Formal
Digital Routing Quadrable
EDA Detail placement Spread cell in a row programming
Physical Design optimization
design Linear
STA Buffering Refinement programming

Sign-off Power analysis Local search

Check legality
Filler method
Parasitic extraction
Physical
verification EM / IR Scheme 2
DRC / ERC
Layout
synthesis LVS
…… …… …… …… ……
 EDA Integration
⚫ Valuable solutions are designed to address the key problems;
⚫ Solutions are integrated to form algorithms for each step;
⚫ Multiple steps are integrated to form subtools;
⚫ Subtools are combined to form the basic version of the tool;
⚫ For different design requirements, functional extensions can
be made at different levels.
 EDA Tool Software Structure
⚫ A decoupled EDA tool structure:
⚫ To reduce development costs, iPD is based on the Functional Module
open-source EDA infrastructure “iEDA”; iEDA-
iEDA-Inferface Initial_placer
Operator
⚫ Data and function are separated; global_placer
iPL Solver
⚫ EDA tool is a hierarchical algorithm set, with a plug- post_global_placer
Config API
and-play mode; legalizer
Analyzer

⚫ All tools in iPD have the same structure. Functional Module detail_placer
Evaluator

⚫ iPL (placement tool in iPD) buffer_inserter Reporter

Database
⚫ iPL utilizes iEDA’s database, operator, manager, (Wrapper)
filler_inserter
Utility
and interface to organize data and algorithms. checker
DB-API iEDA-
⚫ iPL mainly includes the iPL-database and functional evaluator Manager
iEDA-Database
modules. grid_manager
Tool

⚫ Users can configure tool functions and parameter Input Output topo_manager Data

flows through the config files, and obtain outputs by (.v/.lef/.def/.lib/.sdc) (.v/.def)

API.
01 Introduction

02 iPD Design Mode

03 iPD Toolchain
 iPD Toolchain
RTL ⚫ Netlist-to-GDS II
Logic Synthesis ⚫ 10 tools，and other 5 tools are R&Ding.
Netlist
Logic Compiler
⚫ Design, Analysis, Verification
Physical Design
Logic Optimization
Netlist Optimization iNO ⚫ Number of Codes
Technology Map
Floorplanning iFP
⚫ >0.3M lines (exclude 3rd party and history）
Formal Power Delivery Network iPDN

Placement iPL
Analysis Functional Module
Clock Tree Synthesis iCTS iEDA-Inferface Initial_placer iEDA-
RC Extraction
global_placer Operator
Static Timing Analysis Timing Optimization iTO Solver
iSTA iPL post_global_placer
Config API Analyzer
iPA Power Analysis Routing iRT legalizer
Evaluator
IR Drop Engineering Change Order Functional Module detail_placer
buffer_inserter Reporter
Electromigration Filler Database
filler_inserter Utility
(Wrapper)
Sign-off checker
Physical Verification iEDA-
DB-API
iDRC Design Rule Check evaluator Manager
GDS II iEDA-Database
grid_manager Tool
Electronic Rule Check
Input Output topo_manager Data
(.v/.lef/.def/.lib/.sdc) (.v/.def)
Layout vs. Schematic
 Floorplan (iFP) & Power Delivery Network (iPDN)
Flow

Input Key
Data
Metrics
DIE Area 1.5 × 1.5 mm^2 IO Cell & Pad
Init layout
DIE Utili 0.166554

Plan IO cell 1.16 × 1.15

Core Area
cm^2
Tap Cell
Core Utili 0.279541
Place macro Macro Cell
#IO Pin 110

Place phy cell #Instance 297504

#Net 311869
Endcap Cell
PDN pin（>= 32）=
Pin
2893
M1、M2、M7、
PDN
Output M8、M9、AP
 Placement (iPL)
Flow ◼ Min Wirelength Model
min 𝑊 𝒗
Input 𝒗
𝑠. 𝑡. 𝜌𝑏 𝒗 ≤ 𝜌0 , ∀𝑏 ∈ 𝐵
Build PL data where 𝑣 is cell location，𝑊 𝒗 is wirelength，
(grid/topo) 𝜌𝑏 𝒗 is the area density in 𝑏 ∈ 𝐵, 𝜌0 is density thredhold.
HPWLex ( v) = max xi - x j
Init/global i, jÎe
placement 𝑾(𝒗) æ æ æ x öö æ æ -x ööö
LSEex = g çç ln ç å exp ç i ÷÷ + ln çå exp ç i ÷÷÷÷
Post global è è iÎe è g øø è iÎe è g øø ø
placement 1 1
𝐷 𝒗 = ෍ 𝐷𝑖 𝑥, 𝑦 = ෍ 𝑞𝑖 𝜓𝑖 𝑥, 𝑦
2 2
𝑣∈𝑉 𝑣∈𝑉
Check/Legalization
𝝆𝒃 (𝒗) ∇ ∙ ∇𝜓 𝑥, 𝑦 = −𝜌 𝑥, 𝑦 ,
ෝ ∙ 𝜓 𝑥, 𝑦 = 𝟎,
𝒏 (𝑥, 𝑦) ∈ 𝜕𝑅
Detailed
placement ඵ 𝜌 𝑥, 𝑦 = ඵ 𝜓 𝑥, 𝑦 = 0.
𝑅 𝑅

Filler Instace
min 𝑓 𝑣 = 𝑊 𝒗 + 𝜆 σ∀𝑏∈𝐵 𝝆𝒃 (𝒗)
𝒗

Output
• Nesterov Method or Conjugate Gradient
 Placement (iPL)
Flow Key parameter config
Basic Summary
Input iFP.def, iFP.v
Input Wirelength
output iPL_result.def, iPL.v
wl_detail_report.txt
Whether to enable max
is_max_length_opt
wirelength optimization
Build PL data
(grid/topo) max_length_constraint set max wirelength constraint

Whether to enable timing

is_timing_aware_mode
opt
Init/global ignore net whose pin
ignore_net_degree
placement number > k Instance density
num_threads set number of CPU thread

Post global [BUFFER] Set the number of using max

max_buffer_num buffer
placement
[BUFFER] buffer_type Set available buffer name

[GP-Wirelength]
Timing
Check/Legalization min_wirelength_force_ba
r
Control wirelength range

[GP-Density]
Set target density
target_density

Detailed [GP-Density] bin_cnt_x

Set the number of horizontal
Bin
Congestion
placement Set the number of vertical
[GP-Density] bin_cnt_y
Bin

[LG]
Set instance spacing (/site) Design rule violation
Filler Instace global_right_padding
violation_detail_report.txt
[DP]
Set instance spacing (/site)
global_right_padding

Output [Filler] min_filler_width Set min width of filler (/site)

 Clock Tree Synthesis (iCTS)
Flow

Input

Clock distrib

Cluster

Clock net gen

Clock net
routing

Timing analysis
and opt

Output
 Clock Tree Synthesis (iCTS)
Flow
Timing Power Violation
• Latency (max delay) • Buffering • Fanout
Input
• Skew • Wirelength • Capacitance
• Slew (transition)

Clock distrib

Cluster

Clock net gen

Clock net
routing

Timing analysis
and opt

Output
 Routing (iRT)
Flow

input

PA（pin access）

RA（resource
assignment）

GR（global
routing）

TA（track
assignment）

DR（detail
routing）
⚫ Optimization metrics: wirelength, timing, congestion, DRC
VR（violation ⚫ Optimization operations: Global routing: Track allocation: Detailed routing
repair）
⚫ Routing algorithms: Pattern routing, A* routing, Steiner tree, Non-linear
programming, Integer programming
output
 Routing (iRT)
Flow

input

PA（pin access）

RA（resource Layout resource/congestion

assignment）

GR（global
routing）

first iteration routing result final routing result

TA（track
assignment）

DR（detail
routing）

VR（violation
repair）

output
Pin Access Wirelength and via Design rule check
 Design Rule Check (iDRC)
Flow Support DRC Rules:
• Cut Different Layer Spacing
input
• Cut EOL Spacing
• Cut Enclosure
Divide region
• Cut Enclosure Edge
• Cut Spacing
Read rule
• Metal Corner Filling Spacing
• Metal EOL Spacing
Check rule
• Metal JogToJog Spacing
• Metal Notch Spacing
Generate DRC
• Metal Parallel Run Length
Spacing
Report DRC
• Metal Short
• MinHole
output DRC
• MinStep Visulization
• Minimal Area
 Static Timing Analysis (iSTA)
FLow 𝑇𝑐𝑜𝑚𝑏
0/1 D Q Comb. D Q
input

FF1 data path FF2

𝑇𝐹𝐹1 𝑇𝑐𝑙𝑘−𝑞
Read timing lib clk clk
𝑇𝐹𝐹2
buf1
Build timing graph
Clock clock path
source
buf2
Calculate delay
（cell and net）

Timing path
propogation 𝑻𝑭𝑭𝟏 + 𝑻𝒄𝒍𝒌−𝒒 + 𝑻𝒄𝒐𝒎𝒃 + 𝑻𝒔𝒆𝒕𝒖𝒑 − 𝑻𝑭𝑭𝟐 − 𝑻 = 𝑻𝒍𝒂𝒕𝒆
𝒔𝒍𝒂𝒄𝒌 ≥ 𝟎 Setup Constraint

Timing analysis 𝒆𝒂𝒓𝒍𝒚

and report 𝑻𝑭𝑭𝟏 + 𝑻𝒄𝒍𝒌−𝒒 + 𝑻𝒄𝒐𝒎𝒃 − 𝑻𝒉𝒐𝒍𝒅 − 𝑻𝑭𝑭𝟐 = 𝑻𝒔𝒍𝒂𝒄𝒌 ≥ 𝟎 Hold Constraint

output
 Static Timing Analysis (iSTA)
FLow Feature
Support hierarchy netlist
input and def
Basic setup/hold analysis
Support NLDM/Elmore
Read timing lib
Support CCS model
Support high-level net
Build timing graph delay model
Support sdf mark

Calculate delay OCV

（cell and net）
AOCV
pt/ista ratio value
Timing path POCV
propogation Consider IRDrop analysis
mean 1.11
on multi-voltage domain variance 0.00095
Timing analysis Hierarchy analysis
and report
median 1.107
Crosstalk analysis maximum 1.5404
output clock gate analysis minimum 0.9035
Latch analysis
 Timing Optimization (iTO)
DRV report ⚫ Fix timing design rule
Flow Key parameter config violation
Input iPL.def, iCTS.def ⚫ Max cap/Max slew/Max
input
output
iTO_setup_result.def, wirelength/Max fanout
iTO_hold_reslut.def

setup_slack
setup slack value
⚫ Fix hold time
_margin
Electronical
Evaluation hold_slack_
hold slack value
⚫ Fix setup time
margin

max_buffer Setup report ⚫ Cell sizing

Area ratio of inserted buffer
_percent
Timing analysis max_utiliza
⚫ Buffer Insertion
Core utilization
tion

DRV_insert
⚫ Load Insertion
Available buffer for optimizing DRV
Buffer/load location
_buffers
Locate vio path ⚫
setup_inser
Available buffer for optimizing setup
t_buffers

hold_insert
Available buffer for optimizing hold
_buffers
Opt vio path
number_pa
The number of times that WNS is
sses_allowe
allowed continuously decrease when
d_decreasin
opt setup
g_slack
Legal cell For setup, a wire network is not
rebuffer_m
location ax_fanout
optimized for buffer insertion when
its fanout exceeds this value

For setup, fanout is reduced by

split_load_
inserting a buffer when fanout is
output min_fanout
greater than this value

Hold report
 Power Analysis (iPA)
API Description
Flow
buildGraph Build iPW graph data
structure
input readVCD Parse the VCD file
buildSeqGraph Build timing subgraph
Read timing lib checkPipelineLo
op Detect PipeLine loop

Build power levelizeSeqGrap Grade timing

graph h subgraph
propagateToggl Propagate Toggle and
eSP SP data on the graph
Data mark
Calculate Toggle calcLeakagePow Calculate the leakage
er power
Toggle and SP calcInternalPow Calculate internal
⚫ Evaluate power before / during / after the
Propagation er power physical design process
calcSwitchPower Calculate switching
Calculate and power ⚫ Average model
report power
analyzeGroupPo
wer Analyze power data ⚫ Timing window (coming soon)
output reportPower Output power report ⚫ VCD parser
⚫ Report/API
 iFlow: A Chip Design Flow
⚫ iFlow: supporting different EDA tools, PDKs, designs
RTL

iFlow
Verification
Implementation ├── build_iflow.sh
Synthesis/DFT Formal ├── foundry
PDK
Simulation ├── log
iPD Physical Design
RCX
├── report
├── result
STA
├── rtl
Signoff IP
Power
IR Drop ├── scripts
├── tools
Tapeout PV EDA
└── work
Package
PCB &Test

Chip design flow

 Example Design: ysyx-04-01
⚫ RTL：ysyx(一生一芯)-04
⚫ PDK：28nm
⚫ Area：1.5mm × 1.5 mm
⚫ Power：dynamic = 317mW，leakage =
29 mW
⚫ Freq.：200MHz
⚫ Scale：>1.5M Gates
Floorplan PDN Placement
⚫ Features：11 pipelines with cache，IP：
UART、VGA、PS/2、SPI、SDRAM、 2
PLLs，support Linux

CTS Routing DRC

 Example Design: gcd
⚫ RTL：gcd
⚫ PDK：skywater 130nm
⚫ Area：0.15mm × 0.15 mm

Floorplan PDN Placement

CTS Routing DRC

 Example Design: from other users
⚫ gcd & APU

gcd, skywater 130nm APU, skywater 130nm

Area：0.15mm × 0.15 mm Area：0.45mm × 0.45 mm
 Conclusions
⚫ iPD design mode:
⚫ Decomposition and integration
⚫ Unified software structure
⚫ iPD toolchain: from netlist to GDS EDA tool, include
⚫ Floorplan and power deliver network
⚫ Macro placement and standard cell placement
⚫ Clock tree synthesis
⚫ Routing and design rule check
⚫ Timing analysis and optimization
⚫ Power analysis
 Future Works
⚫ Upcoming EDA tools:
⚫ Technology mapping (iMAP)
⚫ Parasitic extraction (iRCX)
⚫ IR drop analysis (iIR)
⚫ AI model:
⚫ Metric prediction
⚫ Design space exploration
⚫ Development tool:
⚫ Process data visualization
Thanks

Bei Yu
[email protected]