322 Linear Integrated Circuits

shown in Fig. 8.20. The clocked flip-flop +Vcc

acts as binary divider to the timer
output. The output frequency in this case RA 4
will be one half that of the timer. The J
7
advantage of this circuit is of having JK-FF
output of 50% duty cycle without any Ra
3 CK -oOutput
restriction on the choice of RA and Rg 555
5 K
Example 8.2
Refer Fig. 8.15. For RA = 6.8 kl, Rp= 3.3 2 H 0.01 uF
kQ andC = 0.1 uF, calculate (a) tHGH
(b) tLow (c) free running frequency
(d) duty cycle, D. Fig. 8.20 Symmetrical waveform generator
Solution
(a) By Eq. (8.11)
tHCH =0.69 (6.8 k2 + 3.3 k2) (0.1 uF) = 0.7 ms
(b) By Eq. (8.12)
trow =0.69 (3.3 k2) (0.1 uF) =0.23 ms

1.45
(c) f= =1.07 kHz
(6.8 k2) + (2) (3.3 k2)](0.1 uF)
(d) D = Low RR
T R + 2Rg
3.3 k2
=0.25 or, 25%
6.8 k2 +2(3.3 ksQ)

Applications in Astable Mode

FSK Generator
In digital data communication, binary code is transmitted by shifting a carrier frequency
between two preset frequencies. This type of transmission is called frequency shift
(FSK) technique. A 555 timer in astable mode can be used to generate FSK signal.keying The
circuit is as shown in Fig. 8.21. The standard digital data input frequency is 150 Hz. When
input is HIGH, transistor Q is off and 555 timer works in the normal astable mode of
operation. The frequency of the output waveform given by Eq. (8.1) can be rewritten as
1.45
fo = (8.18)
(R + 2Ry)C
In atele-typewriter using a modulator-demodulator (MODEM), a frequency between 1070
Hz to 1270 Hz is used as one of the standard FSK signals. The components RA and Rp and
the capacitor C can be selected so that f, is 1070 Hz.
 9
PHASE-LOCKED LOOP
INTRODUCTION
9
systemns. Electronic
The phase-locked loop (PLL) is an important building block of linearwas used for radar
phase-locked loop (PLL) came into vogue in the 1930s when it
PLI, in discrete
synchronisation and communication applications. The high cost of realizing
PLLs are available as
form limited its use earlier. Now with the advanced IC technology,
control is used today in
inexpensive monolithic ICs. This technique for electronic frequency
FM communication sys
satellite communication systems, air borne navigational systems,
and important applications are
tems, computers etc. The basic principle of PLL, different 1Cs
discussed.
.2 BASIC PRINCIPLESK
T'his feedback system consists f.
Phe basic block schematic of the PLL is showWn in Fig. 9.1.
1. Phase detector/comparator
2. A low pass filter
3. An error amplifier
Controlled Oscillator (VC0).
4. A Voltage at a set frequency f. called fvo
The Vco is a free running multiv1brator ana operates
n external timing capacitor and 9n
running freguency. This frequency 15 deverteu side by applying a dc control voltago
external resistor. It can also be shtea vo euner
frequency deviation is directly proportional to the de
an appropriate terminal of the IC. The Voltage Controlled Oscillator" or, in short, VCO.
and hence it is called to
control voltage
signal v, of frequency f, is applied the PLL, the phase detector compares
If an input signal to that of the output v, of the VCOy If the
frequency of the incoming an error voltage u, is generated. The
the phase and frequency and/or phase, phase
two Signals differ in and produces the sum f, + f) and difference f. - f)
a multiplier
detector is basically
output. The high frequency component (, t f) is removed by the low pass
Components at its component is amplified and then applied as
V, to VCO!
flter and theThe signal
difference frequency
v, shifts the VCo frequency in a direction to reduce control voltage
the frequency
afd fo. Once this action starts, we say that the signal is in the capture
between f.
difference
 328 Linear Integrated Circuits Phase-Locked Loop 329

Phase V
Low-pass Am
9.3 PHASE DETECTOR/COMPARATOR
detector filter A
Input f, The phase detection is the most important part of the PLL SYstem. There are two
types of
phase detectors used, analog and digital.
Analog Phase Detector
VCO The principle of analog phase detection using switch type phase detector is shown in Fig.
9.3(a). An electronic switch S is opened and closed by signal coming from VCO (normally a
Fig. 9.1 Block schematic of the PLL
square wave) as shown in Fig. 9.3 (b). The input signal is. therefore. chopped at a repetition
rate determined by VCO frequency. Figure 9.3 (c) shows the input signal v., assumed to be in
range. The VCO continues to change frequency till its output frequency is exactly the same
as the input signal frequency. The circuit is then said to be locked. Once locked the output Electronic switch

frequency f, of VCO is identical to f, except for a finite phase difference o. This phase V,. Input S v
Output
difference
f. and
o generates a corrective control voltage v, to shift the VCOfrequency from f to signal
thereby maintain the lock. Once locked, PLL tracks the frequency changes of the input
signal. Thus. a PLL goes through three stages (i) free running, (ii) capture and (iii) locked 9Chap
or tracking. )
Figure 9.2 shows the capture transient. As capture starts, a small sine wave appears. This v,. Drive
(from VCo)
is due to the difference frequency between the VCO and the input signal. The de
component (a)
of the beat drives the VCO towards the lock. Each successive cycle causes the VCO
frequency
to move closer to the input signal frequency. The difference in frequency becomes smaller and
a large dc component is passed by the filter, shifting the VCO frequency further. The
continues until the VCO locks on to the signal and the difference process
frequency is dc. VCO output
The low pass filter controls the capture range. If VCO frequency is far
away, the beat
frequency will be too high to pass through the filter and the PLL will not respond. We say that
the signal is out of the capture band. However, once locked, the
filter no longer restricts the (b) !
PLL. The VCO can track the signal well beyond the capture band.
Thus tracking range is
always larger than the capture range. Error voltage
Sorte of the important definitions in relation to PLL are: shift
oPhase positive
Loch-in Range: Once the PLL
is locked, it can track frequency outpu
-0 (c) |
changes in the incoming signals. r Unlocked
The range of frequencies over
which the PLL can maintain lock Error voltage
zero
with the incoming signal is called 0=90
the lock-in range or tracking range. Locked
The lock range is usually expressed Capture iransient (d)!
as a percentage of fo the VCo Input f in range
frequeney.
Capture Range: The range of Fig. 9.2 The capture transient
frequencies over which the PLL can acquire lock with an input signal is called the
0=180* Error voltage
negative
range. This parameter is also expressed as capture
Pull-in time: The total time taken by the percentage of f.
PLL to establish lock is called pull-in
(e)

depends on the initial phase and frequency time. This

difference between the two signals as well as on Basic scheme (b) VCO output waveform. Input and output
the oyerall loop gain and loop filter characteristics. detector for PLL (a)
Fig. 9.3 Phase waveform (hatched) of phase detector for (c) o = 0 (d) o =90° (e) o = 180°
 Phase-Locked Loop 331
330 Linear Integrated Circuits
In this way, the output
voltage waveform u. in Fig. 9.4 (b) is
phase (0 = 0) with VCO output U. Since the switch S is closed only when VCO output is rhe average value of the phase obtained.
detector output u. can be calculated
positive, the output waveform , willbe half sinusoids (shown hatched). Similarly, the output as,
waveform for = 90° and Ù= 180° is shown in Fig. 9.3 (d, e). This type of phase detector is (v)a =[(area A) +(are 1A)]
called a half wave detector, since the phase information for only one-half of the input waveform
is detected and averaged. The output of the phase comparator when filtered through a low p+Vcc
pass filter gives an error signal which is the average value of the output waveform shown by
dotted line in Fig. 9.3 (c, d, e).
R R |
It may be seen that the error voltage is zero when the phase shift between the two inputs
is 90°. So, for perfect lock, the VcO output should be 90° out of phase with respect to the V
input signal.
Analysis
A phase comparator is basically a multiplier which multiplies the input signal (, = V, sin
2n f.t) by the VCO signal (v, = V, sin (2n f,t + ). Thus the phase
comparator output is, VCO
U = KVV, sin (2r f) sin (2r f + ) (9.1) Output
where K is the phase comparator gain (or attenuation constant) and ¢ is the phase shift Chap
between the input signal and the VCO output. Equation 9.1 can be simplified as,
U, = KV,Ya
2 fcos(2nft - 2rft - )- cos (2nft+2rfd +)) (9.2)
when at lock, that is, f = fo
0
Then v, = AYYo
2 [cos(-¢)- cos(2 rx 2ff +)] (9.3)
This shows that the phase comparator output
term (KV, VJ2) cos owhich varies as a function contains
a double frequency term and a dc
of
signals. The double frequency term is eliminated byphase
o, that is, cos between the two
the low pass filter and the dc signal is
applied to the modulating input terminal of a VCO. It can be seen that in
state (f = f), the phase shift should be 90° (cos 90° = 0), the perfect locked Fig. 9.4 (a) Phase de ector for IC PLL
that is, U, = 0. in order to get zero error signal,
There are two problems associated with the switch
type phase detector:
1. The output voltage u, is proportional to the input
since it makes phase detector gain and the loopsignal amplitude V. This is undesirable
+1

amplitude. gain dependent on the input signal 37 41 5

2. The output is proportional to cos

and not proportional to making it non-linear.
Both these problems can be eliminated by
is, converting the input to a constant limiting the amplitude of the input signal, that
comparison with square wave input amplitude square wave. A circuit
is shown in Fig. 9.4 (a). This is awhich performs phase (ot
used as full-wave switching phase balanced
pair Q,Q. Transistors Ra- anddetector. Here the input signal is applied to the modulator 21 3r 41

differential
VCO output. The input signal v, andQ5-Q6 are two sets of SPDT switches activated
the VCO output v, are assumed to be high by the
switch the transistors in Fig. 9.4 (a) fully on or enough to
high during the time 0 to (7-0), off. In Fig. 9.4 (b) when v, and u, both are
transistors
through Q and 3. This gives an output voltage and are driven on and cúrrent Ir flows
2 4
U, = -Ip R,
Next for the period (7- 0) for I, when u, (9.4)
driven on resulting in an output voltage is high and v, is low, transistors Q, and Q, are output waveforms for balanced modulator circuit of Fig. 9.4 (a)
diagram of input and
Fig. 9.4 (b) Timing
(9.5)
 Linear Integrated Circuits Phase-Locked Loop 333
332

shown in Fig. 9.5 (c). It can be

20 seen dc output
R,0+(-I;R,) x( - o) =I;R, -1) +hat the maximum dc output voltage
oCCurs when the phase
difference is t
voltage

bocause the output of the gate remains Slope=conversion gain K,

[Since I; = 2/4] igh throughout. The slope of the curve
TC
oives the conversion ratio k, of the phase
= K,(0
output
/2) (9.6) detector. So, the conversion ratio K, for
a supply voltage Vcc = 5 V is,
Phase difference
detector between f, and f
K, = = 1.59 V/rad (9.7) (c)

Another type of digital phase detector Fig. 9.5 (c) DC output voltage versus phase
phase difference cuve
+I,R,
is an edge-triggered phase detector as
of shown in Fig. 9.6 (a). The circuit is an
R-S flip-flop made by NOR gates, such as CD 4001. This circuut is useful when f. (incoming
Compor T/4 3r/4 5r/4
signal) and f VCOoutput) are both pulse waveforms with duty cycle less than 50 per cent.
as shown
Phase difference The output of the R-S flip-flop changes its state on the leading edge of f and f, f, is Chap
R in Fig. 9.6 (b). The variation of de output voltage vs phase difference between f, andlocking
shown in Fig. 9.6 (c). This type of detector has better capture tracking inand the case of
characteristics as the dc output voltage is linear upto 360° compared to 180°
Fig. 9.4 (C) Output dc voltage versus input phase difference of balanced modulator Exclusive-OR detector.
full wave switchiry phase detector Digital phase detector is also available in independent monolithic IC fornm. A typical ex
characteristics which is linear
ample is MC4344/4044. This IC gives input/output transfer
where K, is the phase angle-to-voltage trans er coefficient or, the
phase detector. This linear relationship betv een v, and is depictedconversion ratio of the upto 4I radians or 720°.
in Fig. 9.4 (c).
.2 Digital Phase Detector 14 co 4001
3
Figure 9.5 (a) shows the digital type XOR (Exclusive-OR) phase
4070 Quad 2-input XOR gate. The output of the XOR gate is detector. It uses CMOS type output
inputs signals f or , is high. This type of letector is used whenhigh when only one of the
both the input signals are f
square waves. The input and output wave orms for f. f, are shown in Fig. 9.5 (b). In this
figure, f, is leading f, by degrees. The variation of de output
voltage with phase difference R Output

f 2
co 4001 (b)
(a)
fvcofo
Vc Vut Slope=conversion gain K,
4070
(a)
V=Output 2r 31

Phase difference between f, andf.

27
(c)
(b)
Fia, 9.5 (a) detector using CD4001, Quad 2-input NOR gate (b) Input and
Exclusive-0R phase detector (b) Input and outout Edge-triggered phase (c) dc output voltage vs phase difference o
waveforms Fig. 9.6 (a) output waveforms
342 Linear Integrated Circuits
Phase-LOcked Loop 343
The
once captured, it willhold on till the signal frequency goes beyond the lock-in range. In order
to increase the ability of lock-in range, large capture range is required. However, a large obtainedmultiplication factor can be
by selecting a proper Input
capture range will make the PLL more susceptible to noise and undesirable signal. Hence scaling factor N of the counter. Phase
LPF Amplifier
f comparator
a suitable compromise is often reached between these two opposing requirements of the Frequency multiplication can also
be obtained by using PLL in its
4fN
(VCO control voltage) ,(r/2)K,A harmonic locking mode. If the input +N
V Slope = 1/K,
signal is rich in harmonics e.g. Network VCo
square wave, pulse train etc.. then (Freq.divider)
f,-Af
VCO can be directly locked to the Output PLL
n-th harmonic of the input signal f,= Nf,
f f,tAfe f+Af
without connecting any frequency Fig. 9.12 Frequency multiplier using IC PLL
divider in between. However, as the
2Af=capture amplitude of the higher order harmonics becomes less, effective locking may not take place
range for high values of n. Typically n is kept less than 10.
</2)K,A
The circuit of Fig. 9.12 can also be used for frequency division. Since the VCO output (a
-2Af, =Lock-in range square wave) is rich in harmonics, it is possible to lock the m-th harmonic of the VCO output
with the input signal f The output f, of VCO is now given by
9Ch
Fig. 9.11 PLL lock-in range and capture range
(9.43)
m
capture range. Many a times the LPF band-width is first set for a large value for initial
acquisition of signal, then once the signal is captured, the band-width of LPF is
substantially. This will minimize the interference of undesirable signals and noise. reduced 9.7.2 Frequency Translation'
A schematic for shifting the frequency of anoscillator by a small factor is shown in Fig. 9.13.
97 PLL APPLICATIONS It can be seen that a mixer (or multiplier) and a low pass filter are connected externally to
The output from a PLL system can be obtained either as the the PLL. The signal f, which has to be shifted and the output frequency f, of the vCo are
difference of
voltage signal v,(t) corresponding applied as inputs to the mixer. The output of the mixer contains the sum and
to the error voltage in the feedback loop, or as a f f). The
frequency signal at VCO output terminal.
The voltage output is used in frequency discriminator f, and f. However, the output of LPF contains only the difference signal When PLL is
application whereas the frequency translation or offset frequency f << ) is applied to the phase comparator.
output is usd in signal conditioning, frequency synthesis or clock recovery in locked state,
Consider the case of voltage output. When PLL is locked to an input applications.
voltage v,(t) is proportional to f.-f). If the input frequency is varied frequency, the error
signal, U, will also vary in order to maintain the lock. Thus the as in the case of FM (9.44)
frequency discriminator which converts the input frequency changes voltage output serves as a frequency f, by f,.
In the case of frequency output, if the input to voltage changes. Thus, it is possible to shift the incoming
signal is comprised of many frequency
components corrupted with noise and other disturbances, the PLL can be made to lock,
selectively on one particular frequency component at the input. The output of
then regenerate that particular frequency VCO would
(because of LPF which gives output for beat
frequency) and attenuate heavily other frequencies. LPF (-
Phase
comparator LPF Amplifier
VCO output thus can be Multiplier
regenerating or reconditioning a desired frequency signal (which is weak and buried used for
in noise)
Input ((,+1)
out of many undesirable frequency signals. f, Offset freq. f,
Some of the typical applications of PLL are discussed
now. VCo

9.71 Frequency Multiplication/ Division

Figure 9.12 gives the block diagram of a Output PLI
network is inserted between the VCO frequency multiplier using PLL. A divide by v f,=f,+f,
state, the VCO output frequency f, is output and the phase comparator input. In the
given by, locked Fia. 9.13 PLL USed as a
frequency translator

I, =Nf, (9.42)
344 Linear Integrated Circuits
Phase-Locked Loop 345

9.7.3 AM Detection transmission is called frequency shift keving (FSK)techniaue The binarv
using a PSh demodulator at the data can be
end. The 565 PLL is very useful asretrieved
A PLL may be used to
demodulate AM signals as
Phase
shift
Multiplier
(phase LPF demodulator. Pigure 9.15 shows FSKreceiving a
demodulator using PLL for tele-typewriter sIgnalsFShot
detector) Demodulated 1070 Hz and 1270 Hz. As the signal appears at
frequency and tracks it between the two frequenciesthewith
90°
shown in Fig. 9.14. The PLL AM
input
output input. the loop locks to the input
is locked to the carrier a corresponding de shilt at the
frequency of the incoming
output. A three stage ilter removes the carrier component and the output signal Is made
VCO logic compatible by a voltage
AM signal. The output of PLL
output
comparator.
VCO which has the same SUMMARY
frequency as the carrier, but
Fig. 9.14 PLL Used as AM demodulator
unmodulated is fed to the
1. A phase locked loop consists of a phase detector. low pass flter, amplifier and a VCO
multiplier. Since VCO output is always 90° out of phase with the incoming AM signal under in feedback loop.
the locked condition, the AM input signal is also shifted in phase by 90° before being fed to 2. The important characteristics of a PLL are: lock-in range, capture range and
the multiplier. This makes both the signals applied to the multiplier in same phase. The time.
pull-in
output of the multiplier contains both the sum and the difference signals, the demodulated 3. The lock-in range is usually greater than the capture range. The capture range depends
output is obtained after filtering high frequency components by the LPE. Since the PLL upon the LPF characteristics.
responds only to the carrier frequencies which are very close tothe VCO output, aPLL AM
detector exhibits a high degree of selectivity and noise immunity which is not possible with 4. The phase detectors are of two types: analog and digital. The phase detector is basically Cha
conventional peak detector type AM modulators. a multiplier.
5. The frequency of VCO can be set by an external capacitor and resistor. The output
9.7.4 FM Demodulation frequency f, of VCO is compared with the incoming signal f When f, = f, the PLL is
said to be locked.
If PLL is locked to a FM signal, the VCO tracks the
instantaneous frequency of the
signal. The filtered error voltage which controls the VCO and maintains lock with the input
6. The low pass filter may be passive or active type. The LPF controls the capture range
input and lock range of PLL.
signal is the demodulated FM output. The VCO transfer characteristics 7. Signetics SE/NE 560 series - 560, 561, 562. 564, 565 and 567 are monolithic PLLs. All
of the demodulated output. Since, VCO used in IC PLL is determine the linearity
highly linear, it is possible to the blocks of a PLL are also available as independent ICs and can be interconnected
realize highly linear FM demodulators. to make a PLL

9.7.5 Frequency Shift Keying (FSK) Demodulator 8. The PLLs are used as frequency multiplier, divider, AM and FM demodulator. FSK
demodulator etc.
In digital data communication and computer
of a carrier frequency which is shifted peripheral, binary data is transmitted by means REVIEW QUESTIONS
between two preset frequencies. This type of data
RC ladder filter 9.1. List the basic building blocks of a PLL.
pull-in-time.
9.2. Define capture range, lock-in range and range"?
9.3. Which is greater Capture range' or Lock-in PLLs?
R. C, 9.4. What the major difference between digital and analogoperation
10 k2 VCO and explain its
0.001 uF 0.02 uF! 0.02 uF0.02 uF0.02uF +5 V 9.5. Give the block diagram of IC 566 to a VCo
FSK 0.01 uF
8
T10 A Output 9.6. What the range of modulating input voltage applied
i10 k2
9.7. List the applications of PLL.
2 7 10 k2 10 k2
Input OHR digital data operation
detector and explain its
(1070-1270 565 6
R R
at 150 Hz
9.8. Draw the circuit of a PLL AM
Hz) 5 741
3 4
30 k2
PROBLEMS
frequency if the supplv voltos
1
-5 V
600 2
600 2 0.05 uf 9.1. In the VO0 of Fig. 9.7 calculate the change in output= 6.8 k2, C = 75 pF.R, = 15 LO
is varied between 9 Vand 11 V. ASSume Va l2 V, T
Comparator
and R, = 100 k. t oek signal requency f, = 10 kHz. vCo
oen
9.2 Determine the de control voltage the voltage to frequency transfer coefficient of
running frequency is 10.66 kHz and
Fig. 9.15 FSK
demodulator VCO is 6600 Hz/V.