UNIT 4 LoC 2

Machine Instructions: Machine Instructions are commands or

programs written in machine code of a machine (computer) that it can recognize and execute.
 A machine instruction consists of several bytes in memory that tells the processor to
perform one machine operation.
 The processor looks at machine instructions in main memory one after another, and
performs one machine operation for each machine instruction.
 The collection of machine instructions in main memory is called a machine language
program.
Machine code or machine language is a set of instructions executed directly by a computer’s
central processing unit (CPU). Each instruction performs a very specific task, such as a load, a
jump, or an ALU operation on a unit of data in a CPU register or memory. Every program
directly executed by a CPU is made up of a series of such instructions.
The general format of a machine instruction is

[Label:] Mnemonic [Operand, Operand] [; Comments]

 Brackets indicate that a field is optional

 Label is an identifier that is assigned the address of the first byte of the instruction in which
it appears. It must be followed by “:”
 Inclusion of spaces is arbitrary, except that at least one space must be inserted; no space
would lead to an ambiguity.
 Comment field begins with a semicolon “ ; ”
Example:

Here: MOV R5,#25H;load 25H into R5

Machine instructions used in 8086 microprocessor

1. Data transfer instructions– move, load exchange, input, output.
 MOV: Move byte or word to register or memory .
 IN, OUT: Input byte or word from port, output word to port.
 LEA: Load effective address
 LDS, LES Load pointer using data segment, extra segment .
 PUSH, POP: Push word onto stack, pop word off stack.
 XCHG: Exchange byte or word.
 XLAT: Translate byte using look-up table.
2. Arithmetic instructions – add, subtract, increment, decrement, convert byte/word and
compare.
 ADD, SUB: Add, subtract byte or word
 ADC, SBB: Add, subtract byte or word and carry (borrow).
 INC, DEC: Increment, decrement byte or word.
 NEG: Negate byte or word (two’s complement).
 CMP: Compare byte or word (subtract without storing).
 MUL, DIV: Multiply, divide byte or word (unsigned).
 IMUL, IDIV: Integer multiply, divide byte or word (signed)
 CBW, CWD: Convert byte to word, word to double word
 AAA, AAS, AAM ,AAD: ASCII adjust for add, sub, mul, div .
 DAA, DAS: Decimal adjust for addition, subtraction (BCD numbers)
3. Logic instructions – AND, OR, exclusive OR, shift/rotate and test
 NOT: Logical NOT of byte or word (one’s complement)
 AND: Logical AND of byte or word
 OR: Logical OR of byte or word.
 XOR: Logical exclusive-OR of byte or word
 TEST: Test byte or word (AND without storing).
 SHL, SHR: Logical Shift rotate instruction shift left, right byte or word? by 1or CL
 SAL, SAR: Arithmetic shift left, right byte or word? by 1 or CL
 ROL, ROR: Rotate left, right byte or word? by 1 or CL.
 RCL, RCR: Rotate left, right through carry byte or word? by 1 or CL.
4. String manipulation instruction – load, store, move, compare and scan for byte/word
 MOVS: Move byte or word string
 MOVSB, MOVSW: Move byte, word string.
 CMPS: Compare byte or word string.
 SCAS S: can byte or word string (comparing to A or AX)
 LODS, STOS: Load, store byte or word string to AL.
5. Control transfer instructions – conditional, unconditional, call subroutine and return from
subroutine.
 JMP: Unconditional jump .it includes loop transfer and subroutine and interrupt
instructions.
 JNZ: jump till the counter value decreases to zero. It runs the loop till the value stored in
CX becomes zero
6. Loop control instructions-
 LOOP: Loop unconditional, count in CX, short jump to target address.
 LOOPE (LOOPZ): Loop if equal (zero), count in CX, short jump to target address.
 LOOPNE (LOOPNZ): Loop if not equal (not zero), count in CX, short jump to target
address.
 JCXZ: Jump if CX equals zero (used to skip code in loop).
 Subroutine and Interrupt instructions-
 CALL, RET: Call, return from procedure (inside or outside current segment).
 INT, INTO: Software interrupt, interrupt if overflow.IRET: Return from interrupt.
7. Processor control instructions-
Flag manipulation:
 STC, CLC, CMC: Set, clear, complement carry flag.
 STD, CLD: Set, clear direction flag.STI, CLI: Set, clear interrupt enable flag.
 PUSHF, POPF: Push flags onto stack, pop flags off stack.

What is an instruction set in a computer?

An instruction is a set of codes that the computer processor can understand. The code is usually
in 1s and 0s, or machine language. It contains instructions or tasks that control the movement of
bits and bytes within the processor.
Example of some instruction sets −
 ADD − Add two numbers together.
 JUMP − Jump to designated RAM address.
 LOAD − Load information from RAM to the CPU.
Types of Instruction Set
Generally, there are two types of instruction set used in computers.
Reduced Instruction set Computer (RISC)
A number of computer designers recommended that computers use fewer instructions with
simple constructs so that they can be executed much faster within the CPU without having to
use memory as often. This type of computer is called a Reduced Instruction Set Computer.
The concept of RISC involves an attempt to reduce execution time by simplifying the
instruction set of computers.
Characteristics of RISC
The characteristics of RISC are as follows −
 Relatively few instructions.
 Relatively few addressing modes.
 Memory access limited to load and store instructions.
 All operations done within the register of the CPU.
 Single-cycle instruction execution.
 Fixed length, easily decoded instruction format.
 Hardwired rather than micro programmed control.
A characteristic of RISC processors’ ability is to execute one instruction per clock cycle. This is
done by overlapping the fetch, decode and execute phases of two or three instructions by using a
procedure referred as pipelining.
Complex Instruction Set Computer (CISC)
CISC is a computer where a single instruction can perform numerous low-level operations like a
load from memory and a store from memory, etc. The CISC attempts to minimize the number of
instructions per program but at the cost of an increase in the number of cycles per instruction.
The design of an instruction set for a computer must take into consideration not only machine
language constructs but also the requirements imposed on the use of high level programming
languages.
The goal of CISC is to attempt to provide a single machine instruction for each statement that is
written in a high level language.
Characteristics of CISC
The characteristics of CISC are as follows −
 A large number of instructions typically from 100 to 250 instructions.
 Some instructions that perform specialized tasks and are used infrequently.
 A large variety of addressing modes- typically from 5 to 20 different modes.
 Variable length instruction formats.
  Instructions that manipulate operands in memory.
Example
For performing an ADD operation, CISC will execute a single ADD command which will
execute all the required load and store operations.
RISC will execute each operation for loading data from memory, adding values and storing data
back to memory using different low-level instructions.

Instruction Cycle:A program residing in the memory unit of a computer

consists of a sequence of instructions. These instructions are executed by the processor by
going through a cycle for each instruction.

In a basic computer, each instruction cycle consists of the following phases:

1. Fetch instruction from memory.

2. Decode the instruction.
3. Read the effective address from memory.
4. Execute the instruction.
Input-Output Configuration

In computer architecture, input-output devices act as an interface between the machine and the
user.

Instructions and data stored in the memory must come from some input device. The results are
displayed to the user through some output device.

The following block diagram shows the input-output configuration for a basic computer.

o The input-output terminals send and receive information.

o The amount of information transferred will always have eight bits of an alphanumeric
code.
o The information generated through the keyboard is shifted into an input register 'INPR'.
o The information for the printer is stored in the output register 'OUTR'.
o Registers INPR and OUTR communicate with a communication interface serially and
with the AC in parallel.
o The transmitter interface receives information from the keyboard and transmits it to
INPR.
o The receiver interface receives information from OUTR and sends it to the printer
serially.

Design of a Basic Computer

A basic computer consists of the following hardware components.

 1. A memory unit with 4096 words of 16 bits each
2. Registers: AC (Accumulator), DR (Data register), AR (Address register), IR (Instruction
register), PC (Program counter), TR (Temporary register), SC (Sequence Counter), INPR
(Input register), and OUTR (Output register).
3. Flip-Flops: I, S, E, R, IEN, FGI and FGO

Note: FGI and FGO are corresponding input and output flags which are considered as control
flip-flops.
1. Two decoders: a 3 x 8 operation decoder and 4 x 16 timing decoder
2. A 16-bit common bus
3. Control Logic Gates
4. The Logic and Adder circuits connected to the input of AC.

What are Instruction Formats?

Instruction includes a set of operation codes and operands that manage with the
operation codes. Instruction format supports the design of bits in an instruction. It
contains fields including opcode, operands, and addressing mode.
The instruction length is generally preserved in multiples of the character length, which
is 8 bits. When the instruction length is permanent, several bits are assigned to opcode,
operands, and addressing modes.
The function of allocating bits in the instruction can be interpreted by considering the
following elements −

 Number of addressing modes

 Number of operands
 Number of CPU registers
 Number of register sets
 Number of address lines
The figure displayed the general IA-32 (Intel Architecture- 32 bits) instruction format. IA-
32 is the instruction format that can Intel’s most outstanding microprocessors. This
instruction format includes four fields, such as opcode field, addressing mode field,
displacement field, and immediate field.
 The opcode field has 1 or 2 bytes. The addressing mode field also includes 1 or 2
bytes. In the addressing mode field, an instruction needs only one byte if it uses only
one register to generate the effective address of an operand.
The field that directly follows the addressing mode field is the displacement field. If an
effective address for a memory operand is computed using the displacement value,
then it uses either one or four bytes to encode. If an operand is an immediate value,
then it is located in the immediate field and it appears either one or four bytes.

Addressing Modes
An instruction contains an operation field, an address field, and a mode field. The operation field
indicates what operation is to be performed, for example, addition, subtraction, multiplication,
etc. The mode field indicates how the memory address of the operand, which is to be used in an
operation, is determined. To understand the various types of addressing modes, it is important to
understand how the computer deals with instruction. The instruction cycle of a computer goes
through the following three phases:

 Fetch the instruction from the memory

 Decode the instruction

 Execute the instruction

Types of Addressing Modes

The various types of addressing modes are discussed below:

Implied mode

In this mode, the instruction contains an indirect definition of the operand. An example of an
implied mode instruction is CMA (complement accumulator). Here, the operand (complement) is
implicitly specified in the instruction.
Immediate addressing mode

In this mode, the instruction contains both the opcode and the operand. It can be said that an
instruction that uses the immediate addressing mode contains an operand field in place of an
address field. The operation, as well as the operands, are mentioned in the instruction. An
example of immediate addressing mode instruction is ADD 10. Here, ADD, which is the
operation, and 10, which is the operand, are specified.

Register mode

In this mode, the instruction specifies a register. This register stores the operand. An example of
register mode instruction is:

AC = AC + [R]

This will add the operand stored at register R to the operand stored in the accumulator.

Register indirect mode

In this mode, the instruction specifies a register. This register stores the effective address of the
operand. An instruction that uses register indirect addressing mode is:

AC = AC + [[R]]

Here, the contents which reside in the memory location specified by the register R will be added
to the contents of the accumulator.

Direct addressing mode

In this mode, the instruction specifies an address. This address is the address of the operand. An
example of a direct addressing mode instruction is:

AC = AC + [X]

This will add the operand stored at address X with the operand stored in the accumulator. This
mode is also referred to as absolute addressing mode.

Indirect addressing mode

In this mode, the instruction specifies an address. The memory location specified by the address
contains the address of the operand. An example of an indirect addressing mode instruction is:
 AC = AC + [[X]]

This will add the operand stored at the address specified by the memory location X with the
contents of the accumulator.

Auto-increment/decrement mode

In this mode, the instruction specifies a register which points to a memory address that contains
the operand. However, after the address stored in the register is accessed, the address is
incremented or decremented, as specified. The next operand is found by the new value stored in
the register.

Relative address mode

In this mode, the contents of the address field are added to the constant stored in the program
counter. The result of the addition gives the address of the operand. For example, suppose the
address field contains 850, and the program counter contains 20, then the operand will be at
memory location 850 + 20 = 870.

Indexed addressing mode

In this mode, the address of the operand is determined by adding the contents of the address field
and the contents of the index register.

Base register addressing mode

In this mode, the address of the operand is determined by adding the contents of the address field
and the contents of the base register.

Applications of Various Addressing Modes

The applications of various addressing modes are as follows:

 Immediate addressing mode: Used to set an initial value for a register. The value is usually a
constant
 Register addressing mode/direct addressing mode: Used to implement variables and access
static data
 Register indirect addressing mode/indirect addressing mode: Used to pass an array as a
parameter and to implement pointers
 Relative addressing mode: Used to relocate programs at run time and to change the execution
order of instruction
 Index addressing mode: Used to implement arrays
 Base register addressing mode: Used to write codes that are relocatable and for handling
recursion
 Auto-increment/decrement addressing mode: Used to implement loops and stacks

Purpose of Addressing Mode

The addressing modes serve the following purposes:

 To decrease the number of bits contained in an instruction’s address field

 To provide users with programming versatility by providing facilities such as counters, pointers,
indexing, and program relocation

Conclusion

The addressing mode is one of the fields in an instruction. This field determines how and where
an operand is fetched from the memory. The various types of addressing modes are:

 Implicit addressing mode

 Immediate addressing mode

 Direct addressing mode

 Indirect addressing mode

 Register addressing mode

 Register indirect addressing mode

 Auto-increment/decrement addressing mode

 Relative addressing mode

 Indexed addressing mode

 Base register addressing mode

Introduction to Input-Output Interface
Input-Output Interface is used as an method which helps in transferring of
information between the internal storage devices i.e. memory and the external
peripheral device . A peripheral device is that which provide input and output for
the computer, it is also called Input-Output devices. For Example: A keyboard
and mouse provide Input to the computer are called input devices while a
monitor and printer that provide output to the computer are called output
devices. Just like the external hard-drives, there is also availability of some
peripheral devices which are able to provide both input and output.

Input-Output Interface

In micro-computer base system, the only purpose of peripheral devices is just to

provide special communication links for the interfacing them with the CPU.
To resolve the differences between peripheral devices and CPU, there is a
special need for communication links.
The major differences are as follows:
1. The nature of peripheral devices is electromagnetic and electro-mechanical.
The nature of the CPU is electronic. There is a lot of difference in the mode
of operation of both peripheral devices and CPU.
2. There is also a synchronization mechanism because the data transfer rate of
peripheral devices are slow than CPU.
3. In peripheral devices, data code and formats are differ from the format in the
CPU and memory.
4. The operating mode of peripheral devices are different and each may be
controlled so as not to disturb the operation of other peripheral devices
connected to CPU.
There is a special need of the additional hardware to resolve the differences
between CPU and peripheral devices to supervise and synchronize all input
and output devices.

Functions of Input-Output Interface:

1. It is used to synchronize the operating speed of CPU with respect to input-

output devices.
2. It selects the input-output device which is appropriate for the interpretation of
the input-output device.
3. It is capable of providing signals like control and timing signals.
4. In this data buffering can be possible through data bus.
5. There are various error detectors.
6. It converts serial data into parallel data and vice-versa.
7. It also convert digital data into analog signal and vice-versa.

Interrupts
The interrupt is a signal emitted by hardware or software when a process or an
event needs immediate attention. It alerts the processor to a high-priority
process requiring interruption of the current working process. In I/O devices one
of the bus control lines is dedicated for this purpose and is called the Interrupt
Service Routine (ISR).
When a device raises an interrupt at let’s say process i, the processor first
completes the execution of instruction i. Then it loads the Program Counter
(PC) with the address of the first instruction of the ISR. Before loading the
Program Counter with the address, the address of the interrupted instruction is
moved to a temporary location. Therefore, after handling the interrupt the
processor can continue with process i+1.
While the processor is handling the interrupts, it must inform the device that its
request has been recognized so that it stops sending the interrupt request
signal. Also, saving the registers so that the interrupted process can be restored
in the future, increases the delay between the time an interrupt is received and
the start of the execution of the ISR. This is called Interrupt Latency.
Software Interrupts:

A sort of interrupt called a software interrupt is one that is produced by software

or a system as opposed to hardware. Traps and exceptions are other names for
software interruptions. They serve as a signal for the operating system or a
system service to carry out a certain function or respond to an error condition.
A particular instruction known as a “interrupt instruction” is used to create
software interrupts. When the interrupt instruction is used, the processor stops
what it is doing and switches over to a particular interrupt handler code. The
interrupt handler routine completes the required work or handles any errors
before handing back control to the interrupted application.

Hardware Interrupts:

In a hardware interrupt, all the devices are connected to the Interrupt Request
Line. A single request line is used for all the n devices. To request an interrupt,
a device closes its associated switch. When a device requests an interrupt, the
value of INTR is the logical OR of the requests from individual devices.
The sequence of events involved in handling an IRQ:
1. Devices raise an IRQ.
2. The processor interrupts the program currently being executed.
3. The device is informed that its request has been recognized and the device
deactivates the request signal.
4. The requested action is performed.
5. An interrupt is enabled and the interrupted program is resumed.
Handling Multiple Devices:
When more than one device raises an interrupt request signal, then additional
information is needed to decide which device to be considered first. The
following methods are used to decide which device to select: Polling, Vectored
Interrupts, and Interrupt Nesting. These are explained as following below.
1. Polling: In polling, the first device encountered with the IRQ bit set is the
device that is to be serviced first. Appropriate ISR is called to service the
same. It is easy to implement but a lot of time is wasted by interrogating the
IRQ bit of all devices.
2. Vectored Interrupts: In vectored interrupts, a device requesting an
interrupt identifies itself directly by sending a special code to the processor
over the bus. This enables the processor to identify the device that
generated the interrupt. The special code can be the starting address of the
ISR or where the ISR is located in memory and is called the interrupt vector.
3. Interrupt Nesting: In this method, the I/O device is organized in a priority
structure. Therefore, an interrupt request from a higher priority device is
recognized whereas a request from a lower priority device is not. The
processor accepts interrupts only from devices/processes having priority.
Processors’ priority is encoded in a few bits of PS (Process Status register). It
can be changed by program instructions that write into the PS. The processor is
in supervised mode only while executing OS routines. It switches to user mode
before executing application programs.

I/O Program Controlled Transfer vs DMA

Transfer
In this article, we will discuss the overview of Modes of transfer and mainly our
focus will be on the difference between I/O Program Controlled Transfer vs
DMA Transfer. Let’s discuss it one by one.
Prerequisite – Modes of Transfer in detail
Modes of Transfer
The CPU executes the I/O instructions & accepts the data temporarily but
finally, the source/ destination will be any memory unit. There are various
modes in which data transfer could take place between CPU & I/O devices.
Data transfer to & from peripherals can be handled in one of the 3 given modes
as follows.
1. Programmed I/O
2. Interrupt — Driven I/O
3. Direct Memory Access (DMA)
Let’s discuss them one by one.
1. Programmed I/O:
In program-controlled I/O, the processor program controls the complete data
transfer. So only when an I/O transfer instruction is executed, the transfer
could take place. It is required to check that device is ready/not for the data
transfer in most cases. Usually, the transfer is to & from a CPU register &
peripheral. Here, CPU constantly monitors the peripheral. Here, until the I/O
unit indicates that it is ready for transfer, the CPU wait & stays in a loop. It is
time-consuming as it keeps the CPU busy needlessly.

2. Interrupt—Driven I/O:
To overcome the disadvantage of Programmed I/O,i.e., keeping CPU busy
needlessly, Interrupt — Driven I/O is used. In this approach, when a
peripheral sends an interrupt signal to the CPU whenever it is ready to
transfer data. This indicates that the I/O data transfer is initiated by the
external I/O device. The processor stops the execution of the current
 program & transfers the control to interrupt the service routine when
interrupted. The interrupt service routine then performs the data transfer.
After the completion of data transfer, it returns control to the main program to
the point it was interrupted.

3. DMA — Direct Memory Access:

DMA transfer is used for large data transfers. Here, a memory bus is used
by the interface to transfer data in & out of a memory unit. The CPU provides
starting address & number of bytes to be transferred to the interface to
initiate the transfer, after that it proceeds to execute other tasks. DMA
requests a memory cycle through the memory bus when the transfer is
made. DMA transfers the data directly into the memory when the request is
granted by the memory controller. To allow direct memory transfer(I/O), the
CPU delays its memory access operation. So, DMA allows I/O devices to
directly access memory with less intervention of the CPU.
Difference between I/O Program Controlled Transfer & DMA Transfer
Here we will discuss the difference between I/O Program Controlled
Transfer vs DMA Transfer:
S.No I/O Program Controlled
. Transfer DMA Transfer

It is software control data It is hardware control data

1.
transfer transfer

2. Data transfer speed is slow Data transfer speed is fast.

CPU is involved in the CPU is not involved in the

3.
complete transfer. complete transfer.

Extra hardware is not DMA controller is required for

4.
required. data transfer.
S.No I/O Program Controlled
. Transfer DMA Transfer

Data is routed through the Data is not routed through the

5. processor, during the data processor, during the data
transfer. transfer.

6. Used for small data transfer. Used for large data transfer.

I/O Channels and its types

I/O Channel is an extension of the DMA concept. It has ability to execute I/O
instructions using special-purpose processor on I/O channel and complete
control over I/O operations. Processor does not execute I/O instructions itself.
Processor initiates I/O transfer by instructing the I/O channel to execute a
program in memory.
Program specifies – Device or devices, Area or areas of memory, Priority, and
Error condition actions
Types of I/O Channels :
1. Selector Channel :
Selector channel controls multiple high-speed devices. It is
dedicated to the transfer of data with one of the devices. In selector
channel, each device is handled by a controller or I/O module.
2. 2. Multiplexer Channel :
Multiplexer channel is a DMA controller that can handle multiple
devices at the same time. It can do block transfers for several
devices at once.

Two types of multiplexers are used in this channel:

1. Byte Multiplexer –
It is used for low-speed devices. It transmits or accepts characters.
Interleaves bytes from several devices.
2. Block Multiplexer –
It accepts or transmits block of characters. Interleaves blocks of bytes from
several devices. Used for high-speed devices.