UNIT-1

Single-Stage Integrated-Circuit
Amplifiers
Lecture 1

Kuenzang Thinley
Electronics & Communication Engineering
Department (ECED)
College of Science and Technology
[email protected]

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 Content
1. IC Design Philosophy
2. Comparison of the MOSFET and the BJT
3. The Basic Gain Cell
4. IC Biasing- Current Source, Current-Mirrors, and Current-
Steering Circuits
5. High-Frequency Response-General Considerations
6. The common-Source and common-emitter Amplifier with
active loads
7. High-Frequency Response of the CS and CE Amplifier
8. The common-Gate and common-base Amplifiers with active
loads
9. The Cascode Amplifier

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 IC Design Philosophy
• Constraints, opportunities & features of the IC design philosophy.
• Resistors
• To minimize the chip area, large and even moderate-size
resistors are to be avoided.
• Transistors can be made small and cheaply, and the use of
transistors in preference to resistors is appreciated.
• As a result, the classical biasing arrangement, is abandoned
in IC amplifiers, rather constant-current sources are
implemented with transistors operating in the active mode
biasing.
• The collector and drain resistors in amplifiers are replaced
with constant-current sources that have much higher
incremental resistance.

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 IC Design Philosophy
• Constraints, opportunities & features of the IC design philosophy.
• Capacitors:
• Chip-area considerations make it impossible to fabricate
large-valued capacitors such as those employed for signal
coupling and bypass in discrete-circuit amplifiers.
• Therefore, IC amplifiers are all direct coupled.
• Small-size capacitors, in the picofarad and fraction-of-a-
picofarad range, are easy to fabricate in IC technology.
• Such capacitors can be combined with MOS amplifiers and
MOS switches to realize a wide variety of analog and digital
signal-processing functions.

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 Review On BJT & MOSFET
1. MOSFET:

I D → independent → VDS → saturation

VDS  VOV VGS  Vt

IG = 0

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 Review On BJT & MOSFET
1. MOSFET: Saturation Region Operation
RG 2
VG = VDD
( RG1 + RG 2 )
VDS = VDD − I D ( RS + RD )

VGS = VG − I D RS

1 W
I D = nCox (VGS − Vt ) 
2

2 L 
W
g m = nCox (VGS − VTh )
L

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 Review On BJT & MOSFET
1. MOSFET: Small Signal Operation
1 W
I D = nCox (VGS − Vt ) 
2

2 L 

vout
Av = = − g m ( RD ) Av =
vds
= − g m ( RD || ro ) ro =
VA
vgs vgs ID
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 Review On BJT & MOSFET
2. BJT:  R2 
VTh = VCC
 R1 + R2 
VTh − V BE
IB =
RTh + (  +1) RE
 VTh − V BE 
IC =   
R
 Th + (  + 1 ) R E 

(  + 1)   ,  R E RTh
VTh − V BE
IC =
RE

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 Review On BJT & MOSFET
2. BJT: Small Signal Operation
vout I C RC
Av = = −gmR C =
vin VT
I C  RC 
 Av =  (P , Saturation)
VT

Limitation for gain increase

• Power increases
• Going out of active region

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 The Basic Gain Cell of IC
The CS and CE Amplifiers with Current-Source Loads (Active Loaded)
• The basic gain cell in an IC amplifier is a common source (CS) or
common-emitter (CE) transistor loaded with a constant-current source

Avo = − g m r0 Intrinsic gain (A0) Avo = − g m r0

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 The Intrinsic Gain (A0)
BJT MOSFET

Avo = − g m r0 Avo = − g m r0
W ID
IC VA g m = nCox VOV gm =
gm = r0 = L VOV 2
VT IC
g m = 2nCox W L I D
VA r0 = VA I D = VA' L I D
A0 =
VT
VA 2VA' L
A0 = =
VOV 2 VOV
VOV = 0.15V − 0.3V
• The intrinsic gain realized in a MOSFET fabricated in a modern short
channel technology is only 10 V/V to 40 V/V, an order of magnitude
lower than that for a BJT.
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 The Intrinsic Gain (A0)

VA' 2 ( nCox )(WL )

A0 =
ID
The plot confirms that the
gain increases as the bias
current is lowered. The
gain, however, levels off at
very low currents. The
MOSFET enters the
subthreshold region of
operation , where it
becomes very much like a
BJT with an exponential
current–voltage
A0  I D ( Lower ), g m  characteristic.
• Less ability to drive capacitive loads, and
thus a decrease in bandwidth
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 IC Biasing: MOS Current Source

W
g m = nCox (VGS − VTh )
L
1 W
I D = nCox (VGS − Vt ) 
2
I 2 L 

( I 0 − I D )  0, VD , VG 

( I 0 − I D ),  0, VD , VG 

2I D
VGS = VTh +
W
nCox
Diode connected NMOS L

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 IC Biasing: MOS Current Mirror

1 W  
I = ID2 = nCox   (VGS − Vt ) 
2

2  L 2  

(W L )2 • Related them by the aspect ratios of the

I D2 = I0 transistors. In other words, the relationship
(W L )1 between them is solely determined by the
current gain or geometries of the transistors.
current transfer ratio

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 IC Biasing: MOS Current Mirror

1 W 
I = ID2 = nCox   (VGS − Vt ) 
2

2  L 2  

(W L )2
I D 2 = I ref
(W L )1
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 IC Biasing: MOS Current Mirror

 1  1
 =  + RC
 gm  0

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 IC Biasing: MOS Current-Steering Circuit

(W L )5
I5 = I 4
(W L )4
I 4 = I3
VD 5  VDD − V0V 5
(W L )2 (W L )3
I2 = I0 I3 = I0
(W L )1 (W L )1
VD 2 ,VD 3  −VSS + VGS 1 − VTh
VD 2 ,VD 3  −VSS + VOV 1
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 Small Signal Model of MOS Current-Mirror Circuit
Small signal for M1

1 1
rin = r01
g m1 g m1

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 Small Signal Model of MOS Current-Mirror Circuit

Combining Small signal for M1 & M2

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 Small Signal Parameter of Current Mirror
Small-signal parameters of the current mirror, that is, 𝑅𝑖𝑛, 𝐴𝑖𝑠,
and 𝑅𝑜.

1 1 g m 2 vgs g m 2  ii g m1
Rin = r01 Ais  =
g m1 g m1 ii ii

gm2 (W L )2
Ro = r02 Ais  Ais =
g m1 (W L )1

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 IC Biasing: BJT Current Source

IC
I B1 IB2

V BE1  V BE 2 = V BE
I REF = 2I B + I C

IC  2
I REF = 2 + I C = 1 +  I C
  

I REF = I 0
VCC − V BE
I = I REF =
R

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 IC Biasing: BJT Current Source

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 Increasing the Gain of Basic Cell Gain

Av = g m r0
How to increase the basic cell gain

• gm should not change

• Raise the output resistance

• Passes the current gain (gmro) right

through
• Must have low, ideally zero input
impedance and current gain of unity
• High output resistance (current buffer)

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 Common Gate as Current Buffer

r0 + RL
Rin = ,  g m r0  1
1 + g m r0

1 RL 1
Rin = + r0 = , Rin =
g m g m r0 gm
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 Common Gate as Current Buffer

Rout = r0 + Rs + g m r0 Rs

Rout = r0 + (1 + g m r0 ) Rs
g m r0  1, Rout = r0 + g m r0 Rs
Observation
• Common gate amplifier if g m Rs  1
transform the source resistance
Rs to the output by multiplying it
by the intrinsic gain.
Rout = g m r0 Rs

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 Common Gate as Current Buffer
Impedance transformation properties of the common-gate
amplifier

Rout = r0 + (1 + g m r0 ) Rs

1 RL
Rin = +
g m g m r0

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 Common Source with Degeneration

Rout = r0 + (1 + g m r0 ) Rs

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 Cacsode Current Source : MOS

Properties
I. Transistor (M1 & M2) should be in saturation region.
II. M1 is called cascoded device or output device & M2 as
degenerating device.(Source of the cascode device is connected
to drain of the degenerating device (allowable topology))

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 Cacsode Current Source : MOS

Rout = r01 + (1 + g m1r01 ) r02

Rout = g m1r01r02

g m = 2nCox W L I D

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 Cacsode Current Source : BJT

Rout = r01

Rout = r01 + (1 + g m1r01 ) RE r 1

Rout = r01 + (1 + g m1r01 ) r02 r 1

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 MOSFET as Current Soures
• A MOSFET behaves as a current source when it is operating in the
saturation region.
• An NMOSFET draws current from a point to ground (“sinks current”),
whereas a PMOSFET draws current from VDD to a point (“sources
current”).

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 MOS ( P & N) Type Casode

N-type casodes current source

P-type casodes current source

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 Cascode Amplifier

Av = − g m1ro1
Rout = r01 + (1 + g m1r01 ) r02
Av = −Gm Rout
CS MOS amplifier

Cascode MOS amplifier

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 Cascode Amplifier

iout = g m 2 vin
g m 2 vin
iout
Gm = = gm2
vin

Cascode MOS amplifier

AV = − g m 2  r01 + (1 + g m1r01 ) r02 

AV = − g m 2 r02 .g m1r01
Rout = r01 + (1 + g m1r01 ) r02
AV = − A 2
0

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 Cascode Amplifier

g m 2 vin

1
RX = r01
gm

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 Cascode Amplifier
For the cascode amplifier shown canculate the gain

I out
Gm = = gm2
vin

Rout = RD  r01 + (1 + g m1r01 ) r02 

Av = −Gm Rout

(
Av = − g m 2 RD  r01 + (1 + g m1r01 ) r02  )
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 Cascode Amplifier with Current-Source Load

cascode amplifier
with resistor load cascode amplifier with
(
Av = − g m 2 RD  r01 + (1 + g m1r01 ) r02  ) current-source load

(
Av = − g m 2 r03  r01 + (1 + g m1r01 ) r02  )
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 Cascode Amplifier with Cascode Load

cascode amplifier with

current-source load
cascode amplifier with
(
Av = − g m 2 r03  r01 + (1 + g m1r01 ) r02  ) cascode load

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 Cascode Amplifier with Cascode Load

Gm = g m 2
Rout = R1 R2
(
Rout = r03 + (1 + g m3r03 ) r04  r01 + (1 + g m1r01 ) r02  )
Av = −Gm Rout
( r + (1 + g r ) r
AV = − g m 2 03 m 3 03 04  r01 + (1 + g m1r01 ) r02  )
AV  − g ( g r r g
m2 m 3 03 04 r r
m1 01 02 )
1 1 2
AV  − ( g m r0 ) = − A0
2

2 2
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 Cascode Current Mirror

(W L )2
I D 2 = I ref
(W L )1  =0
if   0 → I ref  I D 2

(W L )2 (1 + 2VDS 2 )
I D 2 = I ref
(W L )1 (1 + 1VDS1 )
Issues with basic current (W L )2 (1 + VDS 2 )
I D 2 = I ref
mirror circuit (W L )1 (1 + VDS1 )
1. Moderate output impedance
2. Drain current changes with voltage VDS

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 Cascode Current Mirror

(W L )2 (1 + VDS 2 )
I D 2 = I ref
(W L )1 (1 + VDS1 )
Can obtain ideal case if only

VDS 2 = VDS 1 → I ref = I D 2

VGS 1 = VGS 2
Since gate and drain are shorted in M1

VDS 1 = VGS 1 = VGS 2

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 Cascode Current Mirror

Vb = VGS 3 + VDS 2
 VDS 2 = Vb − VGS 3
If we want VDS 2 = VDS 1
VDS 1 = Vb − VGS 3
 VGS 1 = Vb − VGS 3
 Vb = VGS 1 + VGS 3

 Vb  VTh + 2 VGS − VTh 

We can achieve VDS1= VDS2 if Vb is equal to above equation.

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 Cascode Current Mirror
We can achieve Vb by using two diode connected device
in series

Vb = VGS 1 + VGS 3

VGS 1 + VGS 3 = VGS 0 + VGS 1

VGS 3 = VGS 0
Vb = VGS 0 + VGS 1

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 Cascode Current Mirror

I ref = I D1 , I out = I D 2
(W L )2 (W L )2
ID2 = I D1 = I ref
(W L )1 (W L )1
if L1 = L2 = L

W2 W2
ID2  I ref I out  I ref
W1 W1

W3
W3 W1 I out  I ref VGS 3 = VGS 0
= W0
W0 W1

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 Cascode Current Mirror

Rout = r03 + (1 + g m3r03 ) r02

Rout = g m3r03r02

Limited Output range

Wilson MOS Current Mirror

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 Cascode Current Mirror

Mofified Wilson MOS Current Mirror

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 Cascode Current Mirror
Vt = 0.6V , nCox = 160  A / V 2 , VA = 10V , I ref = 20  A
L = 1 m,W1 = W4 = 4 m,W2 = W3 = 4 m,

1. Calculate output current

2. Calculate the voltages at M2 & M3
3. What is the lowest voltage at the output
for which current source operation
possible?
4. What are the values of gm and ro of M2
&M3
5. Compute the output resistance of the
circuit

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