IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO.

2, FEBRUARY 2013 719

RRAM Crossbar Array With Cell Selection Device:

A Device and Circuit Interaction Study
Yexin Deng, Peng Huang, Bing Chen, Student Member, IEEE, Xiaolin Yang, Bin Gao, Student Member, IEEE,
Juncheng Wang, Lang Zeng, Gang Du, Jinfeng Kang, and Xiaoyan Liu

Abstract—The resistive random access memory (RRAM) cross-

bar array has been extensively studied as one of the most
promising candidates for future high-density nonvolatile memory
technology. However, some problems caused by circuit and device
interaction, such as sneak leakage paths, result in limited array
size and large power consumption, which degrade the array per-
formance significantly. Thus, the analysis on circuit and device
interaction issue is imperative. In this paper, a simulation method
is developed to investigate the critical issues correlated with the
interaction between devices and the circuit. The simulations show
that a large off/on ratio of resistance states of RRAM is ben-
eficial for large readout margin (i.e., array size). The existence
of the selector connected in series with an RRAM device can
eliminate the need for high Ron resistance, which is critical for
the array consisted of only RRAM cells. The readout margin is
more sensitive to the variation of Ron and is determined by the
nonlinearity of the I–V characteristics of RRAM, whereas the
nonlinear characteristics of the selector device are beneficial for
a larger readout margin. An optimal design scheme for turn-on Fig. 1. Device and circuit interaction issues in RRAM crossbar array. Dif-
voltage and conductance of the selector is proposed based on the ferent cell structures, device and circuit characteristics, and their impacts on
simulation. system performance should be comprehensively investigated.
Index Terms—Crossbar, leakage path, memory array, nonlin-
earity, readout margin, resistive random access memory (RRAM), with its intrinsic drawbacks of purely passive RRAM crossbar
selection device, selector. array architecture, such as parasitic leakage paths in unselected
I. I NTRODUCTION cells and series interconnect resistance, the purely passive
crossbar array will get a limited signal swing, which means the

W ITH the increasing demand for high-density, low-

power, high-speed, and low-cost nonvolatile memory
(NVM) technology, alternative memory technologies beyond
array size may be reduced and adding a large sensing circuit
is necessary. Furthermore, power dissipation and reliability
problem may become serious with the increase in the array
20-nm node [1] have been extensively studied. Among the size. To solve these problems, a selection device connected in
candidates of the next-generation NVM technology [2]–[9], series with the memory device, such as a diode (resulting in a
resistive random access memory (RRAM) has become a 1D1R structure), a transistor (resulting in a 1T1R structure), or
competitive candidate and has been widely studied in re-
a selector (resulting in a 1S1R structure), is introduced, as has
cent years due to excellent scalability, fast switching speed,
been reported in recent years [19]–[22]. Other methods such as
simple device structure, multibit storage and 3-D architec-
complementary resistive switching have been also investigated
ture potential, and good compatibility with complementary
[23], [24].
metal–oxide–semiconductor technology [10]–[15].
To understand the RRAM crossbar array thoroughly, differ-
To realize high-density and low-power storage, an RRAM
ent factors including different memory cell structures, device
crossbar structure was introduced for memory circuit applica-
characteristics, circuit characteristics, and the system perfor-
tion and has been studied in recent years for its simple array
mance should be comprehensively considered, as shown in
architecture and 3-D application potential [16]–[18]. However,
Fig. 1. Considering the interaction between the circuit and
devices, the device and circuit characteristics can be optimized
Manuscript received August 24, 2012; revised October 17, 2012; accepted
November 27, 2012. Date of publication December 24, 2012; date of cur- through design and fabrication process to achieve high system
rent version January 18, 2013. This work was supported in part by Na- performance.
tional Key Basic Research Program (NKBRP), i.e., 973 Program under Grant Many literature works have discussed about RRAM crossbar
2011CBA00600. The review of this paper was arranged by Editor G. Jeong.
The authors are with the Key Laboratory of Microelectronic Devices and array, but most of them were from a circuit’s point of view
Circuits, Institute of Microelectronics, Peking University, Beijing 100871, [25]–[27]. Only some of them worked on the circuit and de-
China (e-mail: [email protected]; [email protected]). vice interaction issues [28]–[32]. However, most of them are
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. based on a simplified circuit model and using a linear resistor
Digital Object Identifier 10.1109/TED.2012.2231683 to represent an RRAM device, which may draw inaccurate
0018-9383/$31.00 © 2012 IEEE
720 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 2, FEBRUARY 2013

conclusion due to too much simplicity used in the analysis. A In the equation, g1 and g2 represent the conductance of Ron
detailed and comprehensive analysis focused on the device and and Roff , and α is the nonlinear factor in the high-resistance
circuit interaction is still lacking, particularly considering the state, which can represent the nonlinear characteristics of
RRAM device and selection device variation and their impacts RRAM I–V curves. With a larger nonlinear factor α, the I–V
on circuit performance. curves may be more similar to the exponential function and
In this paper, the impacts of variation of RRAM device and become steeper. It should be noted that the model predictions
selection device characteristics on the crossbar array perfor- can be fitted well with the measured I–V curves of the high-
mance based on a circuit simulation are addressed. The device and low-resistance states of both bipolar and unipolar RRAM
characteristics and correlated analytical models of RRAM and devices [30].
selection devices will be described in Section II. The cross- When we consider the selection device, a diode, a selector,
bar array architecture and read/write operation modes will be and a transistor may be used for the RRAM crossbar array.
also discussed in this part. In Section III, we mainly discuss However, due to the intrinsic drawback of more than 8F2 cell
the impacts of selected cell position and the data patterns size, the 1T1R structure cannot be scaled down to an ideal size
of the memory cells on the circuit performance. We investi- compared with other structures [20]. Thus, we mainly discuss
gated the worst case scenario of selected cell and data patterns the more promising 1S1R and 1D1R structures in this paper.
for different read and write operation modes. The simulation The 1D1R structure is used for unipolar RRAM, whereas the
setup is also summarized in this part. According to the worst 1S1R structure is used for bipolar RRAM. The selector is
case scenario, the impacts of the device characteristics of actually a device with bidirectional diode I–V characteristics
RRAM and selector devices on the circuit performance are and has been extensively studied in recent years [20], [35]–[37].
discussed in Section IV. The variation of high/low resistance Considering that the selector is actually a bidirectional diode
and nonlinear characteristics of RRAM and the variation of and the similar I–V characteristics of high- and low-resistance
resistance, turn-on voltage, and nonlinear characteristics of states of bipolar and unipolar RRAM devices, we can mainly
selection device and their impacts on the read operation are discuss the 1S1R structure because the I–V curves of the 1D1R
investigated. structure can be obtained simply by using only one polarity of
the 1S1R structure and the discussion may be similar.
For a selector, we can use the function to fit the I–V curves
II. D EVICE AND C IRCUIT S TRUCTURE
as follows:
A. Device Characteristics and Analytical Device Model
For selector : I = g × exp ((V − Von ) × β) . (3)
The RRAM device structure is usually a resistive switching
layer sandwiched between two electrodes. The resistance of the
In the equation, g represents the conductance of the selector,
device can be changed by applying voltage on the electrodes, Von is the turn-on voltage of the selector, and β is the nonlinear
which induce resistance change of the resistive switching layer factor of the selector.
between a high-resistance state Roff and a low-resistance state
According to the measured data [20], I–V curves can be
Ron . The transition process from a high-resistance state Roff to fitted using the analytical model of RRAM and selector devices,
a low-resistance state Ron is called SET process, whereas from as shown in Fig. 2(a) and (b). The simulated I–V curves using
Ron to Roff , it is called RESET process. In most RRAM devices,
the analytical device model can fit the experimental data well.
an electrical forming process is necessary to achieve reversible Then, the I–V curves of a 1S1R memory cell can be simulated,
resistive switching between Ron and Roff . The switching modes as shown in Fig. 2(c). The current of low-resistance state is
may be classified into two modes, i.e., unipolar and bipolar
strongly constrained by the selector when the applied voltage
modes. Unipolar switching mode means the switching direction is lower than the turn-on voltage in the 1S1R structure, as
depends on the amplitude of the applied voltage but not on
compared with the structure without the selector.
the polarity of the applied voltage. Thus, SET/RESET can occur
at the same polarity. If unipolar switching can symmetrically
occur at both positive and negative voltages, it is also referred B. RRAM Crossbar Array Architecture
as a nonpolar switching mode. Bipolar switching mode means
The crossbar array is composed of bit lines and word lines,
the switching direction depends on the polarity of the applied
voltage. Thus, SET can only occur at one polarity and RESET and the memory cell is positioned at the cross points of bit
lines and word lines, as shown in Fig. 3(a). The inset shows the
can only occur at the reverse polarity. In this paper, the study
memory cell structure, the selection device is in series with the
mainly focused on the bipolar RRAM due to the superior
memory performance to unipolar devices. RRAM device, and the memory resistance is the total resistance
of the two devices.
In order to accomplish the circuit simulation, the analytical
Due to the leakage paths in the crossbar array, some prob-
models of RRAM and selector devices are developed. In an
RRAM device, Ron and Roff can be fitted well with the function lems such as output signal degradation, programming failure,
and crosstalk problem may happen in the array, as shown
as follows [30]:
in Fig. 3(b). During read operation, the leakage paths in the
For Ron : I = g1 × V (1) unselected cell will degrade the output signal and make it hard
to distinguish the resistance states of the memory cells. There-
For Roff : I = g2 × sinh (α × V ). (2) fore, the selection device is used to annihilate this problem.
DENG et al.: RRAM CROSSBAR ARRAY WITH CELL SELECTION DEVICE 721

Fig. 4. Schematic of the crossbar array circuit. The memory cell, interconnect
resistance, and Rsense are shown in the figure. V1 and V2 represent the voltage
applied on the unselected word lines and bit lines. The unselected cells can be
divided into three groups as B1, B2, and B3. The memory cells in the same
group share the same resistance state, whereas in different groups, they can be
different.

During the write operation, the voltage drop on the interconnect

caused by the leakage path may cause the voltage drop on
the selected cell insufficient to write successfully. Moreover,
the crosstalk disturbance may cause some reliability problems
Fig. 2. Fitted I–V curves and experimental data from [20] of (a) RRAM and such as misprogramming and electric stress-induced retention
(b) selector based on the analytical device model. The simulated I–V curves failure. All these problems will degrade the performance of the
can fit the data well. (c) Simulated I–V curves of a 1S1R memory cell. The crossbar array and have to be investigated in detail.
current of low-resistance state is strongly constrained by the selector device in
the 1S1R cell compared with the case without the selector. In order to understand these device and circuit interaction
issues in the RRAM crossbar array, a circuit simulation is used
in this paper. The analytical model is put into the circuit using
Verilog-A, whereas the SPICE simulation is used to study the
performance of the array.

C. Read and Write Operations

The crossbar memory array is schematically shown in Fig. 4.
In the circuit, Vdd represents the voltage source that is applied
on the selected word line. The selected bit line is grounded.
All the unselected word lines and bit lines are set to be V1 and
V2 , respectively, as shown in Fig. 4. Different bias methods
can be used to read or write the selected memory cell in the
array, such as 0 (for read operation only), floating, 1/2 V, and
1/3 V methods [34], which corresponds to different bias modes
applied on unselected word lines V1 and bit lines V2 . In 0,
floating, and 1/2 V methods, all the unselected word lines and
bit lines are set to be grounded, floating, and half of the voltage
value of the selected word line, respectively. All the unselected
word lines and bit lines are set to be 1/3 and 2/3 of the voltage
value of the selected word line in the 1/3 V method.
To guarantee a successful write operation, the voltage drop
on the RRAM of the selected cell must be larger than the
Fig. 3. (a) Schematic of the RRAM crossbar array. (Inset) Cell structure at
each cross point of bit lines and word lines. The memory cell is composed switching voltage, whereas the voltage drop on the unselected
of RRAM and a selection device. (b) Schematic of the leakage paths in the cell should be lower than the switching voltage to avoid
crossbar array. The current from (pink arrow) the voltage source may flow misprogramming.
into (green arrows) the selected cell and (red arrows) the unselected cells. The
current flowing into the unselected cells may cause output signal degradation During the read operation, to make sure that the reading
and crosstalk problem. process is nondestructive, the voltage drop on all the RRAM
722 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 2, FEBRUARY 2013

devices should be lower than the switching voltage. Current

difference ΔI, which is obtained by reading Ron and Roff , is
then sensed by connecting all the bit lines to sense amplifiers
(SAs), which act as current-to-voltage converters, and thus, the
resistance states can be detected this way. An example of an
SA is a simple current mirror or an operational amplifier with a
feedback resistor to sense the current. (The design of SAs is not
part of this paper, and the peripheral sensing circuits are not in-
cluded in the simulation.) Due to the existence of parasitic leak-
age current paths distorting the real signal and the additional
degradation caused by the parasitic interconnect resistance, the
voltage difference (ΔV or readout margin) diminishes, and
thus, the signal-to-noise ratio is degraded. The degradation will
become much more serious when the array size increases, and
then the array size may be constrained by the degradation of
the readout margin. Therefore, in a certain array with a limited Fig. 5. Schematics of the worst case data pattern during read and write
operations. The worst case for different resistance states of the selected cell
size, a larger readout margin means a potential for a larger array may be different. In the write operation, the worst case is when all the cells are
size under certain device and circuit characteristics. To maintain in Ron , whereas in the read operation, the worst case is different under different
the readout margin when the array size increases (or to enlarge bias modes.
the readout margin in a certain array size), device and circuit
investigate this issue, we divide the unselected cells into three
characteristics need to be optimized, which will be discussed
groups, as shown in Fig. 5. All the cells in the same group share
later in this paper.
the same resistance state, but the resistance state of the cells in
Moreover, the input resistance (i.e., Rsense , as shown in
different groups can be different.
Fig. 4) of the SAs should be considered. We assume that
During the write operation, the worst case data pattern is the
the input resistance Rsense of the SAs is the same for all
case that all the cells are in low-resistance state, as shown in
conditions, and the readout voltage is detected from Rsense . The
Fig. 5. In this case, the leakage current may be the largest,
transresistance Rtran of the SAs has to be considered. However,
resulting in the largest degradation of the access voltage on the
in practice, Rtran must be within a certain range for the speed,
selected cell.
area, and power considerations, and the maximum array size is
During the read operation, the worst case scenario is the case
also directly related to the properties of SAs. All these problems
in which the readout margin is the smallest. In our simulation,
will make the discussion too complicated; hence, in this paper,
it means that the voltage drop on Rsense is the largest when
we only detect the voltage difference (ΔV or readout margin)
the selected cell is in high-resistance state and is the smallest
on Rsense . The Rsense in the following simulation is set to
when the selected cell is in low-resistance state. The worst
be 2 kΩ. The interconnect resistance between two adjacent
case data patterns are different under different bias methods, as
junctions is 2.8215 Ω for a 4F2 crossbar structure according
shown in Fig. 5. Although this three-group division method is
to the International Technology Roadmap for Semiconductors
a simplification method, the extreme condition can be outlined.
for 22-nm technology node [33].
More detailed analysis on data pattern can be found in [32].
Based on the worst case scenario, the performance of dif-
III. W ORST C ASE D ISCUSSION ferent bias modes is obtained. For different bias modes, we
can find that the 1/3 V method gets a better performance at
A. Worst Case Selected Cell maintaining the readout margin as the array size increases using
The location of the selected cell will strongly influence the circuit simulation. In the following part of this paper, all the
write and read operations. Readout margin and access voltage simulation work is based on the 1/3 V bias method and the
dropped on the selected cell can be different with different data patterns are set to be the worst case discussed above.
locations of the selected cells during read and write operations, The array size is set to be 128 × 128, and the memory cell is
respectively. We find that the worst case scenario of the selected 1S1R structure. All the voltage shown in the figures represents
cell during read and write operations is the one that is located the voltage applied on the selected word line during read
at the farthest corner from the word- and bit-line sources, as operation and is set to be 2 V, if it is not stated in advance.
shown in Fig. 4. In this case, the voltage dropped on the selected All the simulation parameters are listed in Table I.
cell is the smallest during write operation and the readout
margin is the smallest during read operation. All the following IV. D EVICE C HARACTERISTICS VARIATION
discussions are based on this worst case scenario.
A. RRAM Device Characteristics Variation
Based on the analytical model we described earlier, the
B. Worst Case Data Pattern
variation of the RRAM I–V characteristics can be simulated.
Different data patterns of the unselected cells strongly in- As shown in Fig. 6, the RRAM I–V curves vary with the
fluence the write and read operation performance. In order to increase in the conductance of Ron (g1 ) and Roff (g2 ) and the
DENG et al.: RRAM CROSSBAR ARRAY WITH CELL SELECTION DEVICE 723

TABLE I
S IMULATION PARAMETERS U SED IN T HIS PAPER

Fig. 6. Variation of the RRAM I–V curves as the variation of the Ron and
Roff characteristics in the analytical model. The impact of the increase in the
conductance of Ron (g1 ) and Roff (g2 ) and the nonlinear factor α of Roff is
simulated. The increase in the conductance of different resistance states results
in a larger current at a constant voltage, whereas the I–V curves become steeper
with a larger nonlinear factor α.

nonlinear factor α of Roff , which can represent the main I–V

characteristics of RRAM.
First, we focus on the impact of conductance variation on
the read operation. We change the conductance of Ron (g1 ) and
Fig. 7. Readout margin as a function of the conductance of Ron (g1 ) and
Roff (g2 ), and the corresponding variation of the readout margin Roff (g2 ). The red region means a larger readout margin, and the white region
ΔV is shown in Fig. 7. The variation range of the conductance means a zero or below zero readout margin. It shows that a higher Roff and a
of Ron and Roff is considered based on the fitted experiment lower Ron are needed for a larger readout margin. In a circuit with the selection
device, a lower Ron is preferred, whereas a higher Ron is preferred in a circuit
data as aforementioned. The red region means a larger readout without the selection device [30]. Furthermore, the optimization of Ron is more
margin, and the white region (also part of the dark blue region in efficient as the impact of variation of Ron is much stronger than that of Roff .
the upper figure, which is hard to distinguish, hence we make it
white in the lower figure) means that the readout margin in this ratio of Roff and Ron . As shown in Fig. 7, the impact of
region is 0 or below zero. This is because the worst case for the variation of the conductance of Ron is much stronger than that
Ron or Roff of the selected cell is different. Under a common of Roff . Therefore, it is more efficient to optimize the resistance
condition, the detected voltage of Ron may be larger than that of Ron than that of Roff to get a larger readout margin in this
of Roff , which results in a positive readout margin. However, condition.
when the resistance of Ron increases, the readout margin may The nonlinear characteristics of RRAM I–V curves may
become zero or even below zero due to the different worst case be beneficial for read operation according to [31]. However,
for Ron and Roff of the selected cell. Thus, a too large resistance in an array with a selection device, the effect of nonlinear
of Ron may be unacceptable for read operation. According to characteristics should be discussed in detail. As shown in Fig. 8,
[30], a large resistance of Ron may be beneficial for low leakage the normalized readout margin gets smaller when the nonlinear
current and low power consumption in the purely passive array. factor α of Roff increases. The nonlinear characteristics may be
However, the selection devices in the crossbar array strongly beneficial for leakage current constraining, but the increase of it
constrain the leakage current; hence, the impact of resistance may result in a lower Roff and Ron ratio and the effect is more
of Ron on constraining leakage current is weak. Thus, a lower obvious at a higher reading voltage, as shown in Fig. 8. This is
resistance of Ron is preferred when the selection device is used because the I–V curve of Ron is constant and the increase in
in the circuit. Furthermore, the results show that a lower Ron nonlinear factor α causes the I–V curve of Roff to be steeper;
resistance and a higher Roff resistance are beneficial for a large hence, the resistance ratio of Roff and Ron becomes smaller.
readout margin, which reflects the need for a large resistance Therefore, the nonlinear characteristics of Roff are detrimental
724 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 2, FEBRUARY 2013

Fig. 8. Normalized readout margin as a function of the nonlinear factor α of

Roff . A larger nonlinear factor α may get a smaller readout margin, and the Fig. 10. Readout margin as a function of the turn-on voltage Von and
effect is more obvious when a larger read voltage is applied. The nonlinear nonlinear factor β of the selector. An optimal point can be obtained for turn-on
characteristics of Roff may be detrimental to the readout margin. voltage Von , whereas a larger nonlinear factor β may result in a larger readout
margin.

leakage current cannot be efficiently constrained, also resulting

in a small readout margin. For the conductance of the selector,
a similar variation trend of I–V curves to the turn-on voltage is
shown in Fig. 9; hence, an optimal point may be also obtained
(not shown here). The explanation of the phenomenon is also
the same as the analysis of turn-on voltage.
For the nonlinear characteristics, a larger nonlinear factor β
may result in a larger readout margin, as shown in Fig. 10. This
may be attributed to the larger on/off ratios of the selector as
Fig. 9. Variation of the turn-on voltage Von , conductance g, and nonlinear nonlinear factor β increases, as shown in Fig. 9. Therefore, an
factor β of the selector device and its impact on the I–V curves using the optimized turn-on voltage Von and conductance g and a higher
analytical model described earlier. The variation of turn-on voltage Von and
conductance g shares the similar variation trend of I–V curves, whereas the nonlinear factor β are beneficial for a larger readout margin
increase in nonlinear factor β results in steeper I–V curves. (i.e., array size).
Based on the method aforementioned, different experiment
to the readout margin in this condition. However, due to the data of different RRAM devices and selectors can be fitted
analytical model we used, the nonlinear characteristics of Ron by the analytical model and the circuit performance can be
are not discussed here. Because of the metallic conduction obtained using the simulation method. Then, the optimization
mechanism in low-resistance state, the I–V curves of Ron are of the device and circuit characteristics can be accomplished
linear in many cases. Therefore, the discussion here may be based on the simulation results.
useful for the understanding of the general cases. However, the discussion about device characteristics here
is only based on the readout margin (i.e., array size). The
B. Selection Device Characteristics Variation performance of the circuit, such as speed, power consumption,
and reliability issues, should be considered comprehensively,
The characteristics of the selection device have strong impact which is our ongoing work.
on the performance of the crossbar array. In this part, we will
discuss the variation of the characteristics of the selector and its
V. C ONCLUSION
impact on the read operation.
As shown in Fig. 9, the variation of the I–V characteristics An analysis of device and circuit interaction in an RRAM
of the selector is obtained using the analytical model aforemen- crossbar array considering the variation of RRAM/selector I–V
tioned. The variation of turn-on voltage Von , conductance g, and characteristics and their impacts on readout margin (i.e., array
nonlinear factor β results in a different variation trend of I–V size) has been conducted using the developed circuit simulation
curves. method. The existence of the selector eliminates the need for
The impact of the variation of the selector characteristics high Ron resistance, whereas a large Roff and Ron ratio is
on the readout margin is shown in Fig. 10. The impact of still needed for a large readout margin. The readout margin is
the variation of turn-on voltage Von and nonlinear factor β more sensitive to the variation of Ron . An optimal value can be
on the readout margin is shown in the figure. For the turn- obtained for the turn-on voltage and conductance of the selector
on voltage, an optimal point can be obtained, which means to get a larger array size. The nonlinearity of the RRAM may be
that an optimized value of the turn-on voltage of the selector detrimental to a large readout margin, whereas the nonlinearity
can be found under certain device and circuit characteristics. of the I–V curves of the selector is beneficial for a large readout
When the turn-on voltage is too high, the voltage drop on margin. This paper may provide a simulation method and a
the selected cell may be reduced, and thus, the Roff and Ron guideline for device and circuit design and optimization of an
ratio of RRAM at that voltage may be too small, resulting in a RRAM crossbar array from a circuit and device interaction
small readout margin. When the turn-on voltage is too low, the point of view.
DENG et al.: RRAM CROSSBAR ARRAY WITH CELL SELECTION DEVICE 725

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726 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 2, FEBRUARY 2013

Peng Huang received the B.S. degree from Xidian Lang Zeng received the Ph.D. degree in micro-
University, Xi’an, China, in 2010. He is currently electronics from Peking University, Beijing, China,
working toward the Ph.D. degree in the Institute of in 2012.
Microelectronics, Peking University, Beijing, China. He is currently a Postdoctoral Associate in the
Institute of Microelectronics, Peking University.

Bing Chen (S’11) received the B.S. degree from

Sichuan University, Chengdu, China, in 2008. He is
now a Ph.D. candidate of the Institute of Microelec-
tronics, Peking University, Beijing, China.
Gang Du received the Ph.D. degree in micro-
electronics from Peking University, Beijing, China,
in 2002.
In 2003, he joined the Institute of Microelectron-
ics, Peking University, where he was promoted as a
Professor in 2012.

Xiaolin Yang received the B.E. degree from

Huazhong University of Science and Technology,
Wuhan, China, in 2010. He is currently working
toward the master’s degree in the Institute of Micro-
electronics, Peking University, Beijing, China.

Jinfeng Kang received the Ph.D. degree in solid-

state electronics from Peking University, Beijing,
China, in 1995.
He is currently a Full Professor in the School
Bin Gao (S’08) received the B.S. degree in physics of Electronics Engineering and Computer Science,
in 2008 from Peking University, Beijing, China, Peking University.
where he is currently working toward the Ph.D.
degree in microelectronics.

Juncheng Wang received the B.S. degree in micro- Xiaoyan Liu received the Ph.D. degree in micro-
electronics in 2011 from Peking University, Beijing, electronics from Peking University, Beijing, China,
China, where he is currently working toward the in 2001.
Ph.D. degree. She is currently a Professor in the Institute of
Microelectronics, Peking University.