iL a Digital Logic: Next Topic : Addition of two numbers in the signed-magnitude system Bonrgoctasesin|G Sis: i Digital Logic Pye. The addition of two numbers in the signed-magnitude system follows the rules of ordinary arithmetic. If the signs are the same, we add the two magnitudes and give the sum the common sign. If the signs are different, we subtract the smaller magni- tude from the larger and give the difference the sign of the larger magnitude. For example, (+25) + (-37) = —(37 — 25) = —12is done by subtracting the smaller mag- nitude, 25, from the larger magnitude, 37, and appending the sign of 37 to the result. This is a process that requires a comparison of the signs and magnitudes and then per- forming either addition or subtraction. The same procedure applies to binary numbersiL a Digital Logic: Next Topic : Addition of two numbers in the Pea Gene (salsa leo Bonrgoctasesin| GS Sass: Digital Logic loa PET} the rule for adding numbers in the signed-complement system does not require a comparison or subtraction, but only addition. The procedure is very simple and can be stated as follows for binary numbe The addition of two signed binary numbers with negative numbers represented in signed-2's-complement form is obtained from the addition of the two numbers, includ- ing their sign bits. A carry out of the sign-bit positiDigital Logic eye Numerical examples for addition follow: + 6 00000110 = 6 11111010 +13 00001101 +13 00001101 +19 00010011 +7 00000111 + 6 00000110 — 6 11111010 =13 11110011 =13 11110011 = 7 11111001 =19 11101101 Note that negative numbers must be initially in 2’s-complement form and that if the sum obtained after the addition is negative, it is in 2’s-complement form. For example, —7 is represented as 11111001, which is the 2s complement of +7. In each of the four cases, the operation performed is addition with the sign bit included. Any carry out of the sign-bit position is discarded, and negative results are automatically in 2’s-complement form.Digital Logic lea rey Numerical examples for addition follow: + 6 00000110 — 6 11111010 +13 00001101 +13 00001101 +19 00010011 + 7 00000111 + 6 00000110 — 6 11111010 =13 11110011 =13 11110011 —7 11111001 -19 11101101iL a Digital Logic: Next Topic : SSR ar) Addition of aco in the 1s Complement system Bonrgoctasesinae isha Loge a oe ) CASE ECC as ahi aes re oS ace ae or ia | aes Cy a ot)Saas) = POW + © foo) f —O051900 in eee mea SY | fon? S Of Ope 13 ee ee anee =3 CD 4 -a)e-s were ra ie s 79) oe KoR eee) mo oe AAT | ree > Ane a 2a ened tye re rei an H1oll F ofoo] an aon ord| tT alia aon fore oT al en ee Reeda ere ae Co te al odo) van Crey Fle tte Pa San LE atop Ola aa i ee Fi A oe ee) naeGO Classes The following examples illustrate the addition of 1’s and 2’s complement num- bers for a word length of n = 8: 1. Add —-11 and —20 in 1’s complement. +11 = 00001011 +20 = 00010100 taking the bit-by-bit complement, —11 is represented by 11110100 and —20 by 11101011 11110100 (-11) 11101011 +(-20) (1) 1011111 1 (end-around carry) 7 ' in 1S Gmp Rep. 11100000 = -31L——a by a =I Gang —Lo jn 2/5 Comp azi Ua a AER YT ESTES , i nce one aren” meer Fed eae CATO eee2. Add —8 and +19 in 2’s complement +8 = 00001000 complementing all bits to the left of the first 1, -8, is represented by 11111000 11111000 (-8) 00010011 +19 00001011 = +11 t_ (discard last carry)CES brat nay 404 GO Classes Aone foto a -009 )0090 Se Siey one aE a) Cine Ms eae emt T 31) (Coen ee ane eal )facets! ane Nembeas Eig im a1) ae dae ery Me wa onan eel5 0) in re BY UCD anDyiel neaan Sp £07 susey os Saas _ fase Ren oe ey ore Se ee Ocn) NVAsal 4 ) ay ea isoO} )) rome ; rer cane, Nea ae \ ae ae Taeee COR Wan oP fs Ago ee a oe | aeiL a Digital Logic: G Next Topic : Se Subtraction of two een faate Pea Gene (salsa leo Bonrgoctasesin|S Sst: yr tte aC kare Subtraction of two signed binary numbers when negative numbers are in 2’s-complement form is simple and can be stated as follo Take the 2’s complement of the subtrahend (including the sign bit) and add it to the minuend (including the sign bit). A carry out of the sign-bit position is discardedee eT Te Sn 7 ee ren) maa ea lie + a eewe eer) a” onan al Ge (ein SD OLED) Qe cccissesin assesinIl} 00 mal a] A ayia) aw akc eKEee oT a —F. ello 8 & fae) O0loo ,— JOl/pD ty)-Ca) 910d +o) JoSb —-Y > J] [00 A —4F;, [orl{ “ Te ar , Re eee aT Qloo ‘ ara enCIC Signed Nombor ees Comp Rep aac Ap i ea ea an a) eat) hep >Subtraction of two signed binary numbers when neg form is simple and can be stated as follows: ative numbers are in 2’s-complement Take the 2’s complement of the subtrahend (including th minuend (including the s ign bit) and add it to the n bit). A carry out of the sign-bit position is discarded. This procedure is adopted because a subtraction operation can be changed to an addi- tion operation if the sign of the subtrahend is changed, as is demonstrated by the following relationship: (A) ~ (+B) = (4A) + CB); (+A) — (-B) = (+A) + (+B). But changing a positive number to a negative number is easily done by taking the 2’s complement of the positive number. The reverse is also true, because the complementLS eases | Digital Logic eed egative number in complement form produces the equivalent positive number. To this, consider the subtraction (—6) — (—13) = +7. In binary with eight bits, this operation is written as (11111010 — 11110011). The subtraction is changed to addition by taking the 2’s complement of the subtrahend (13), giving (+13). In binary, thi: 11111010 + 00001101 00000111. Removing the end carry, we obtain the correct answer: 00000111 (+7). (i a Digital Logic : Next Topic : Subtraction of two numbers in the Tea @senye) (else ees BonrgoctasesinO0Oo)]00 A U- ve G ne ar) rm a Fo t Te eae Oo]%o Seen Od l00 ny el ei Ce eeaa eon ne S : a i es enka in (a aoe a on ws Ww ] (axe) _ Od|o} Ox CerLS eases | Ue Digital Logic Re rey ~~ ~~ WN) a my It is worth noting that binary numbers in the signed-complement system are added and subtracted by the same basic addition and subtraction rules as unsigned numbers. Therefore, computers need only one common hardware circuit to handle both types of rithmetic. This consideration has resulted in the sig em being used in virtually all arithmetic units of compute: mmer must interpret the results of such addition or subtraction differently, depending on whether it is assumed that the numbers are signed or unsigned.——————— eee UES 7 ce CTA ee (D No re Aasition of Sve © Nam 2 eae Se) a aR Yo ae* Unsigned variables use unsigned binary (normal power-of-2 place values) to represent numbers 128 64 32 1 #8 4 #2 414 * Signed variables use the 2’s complement system (Neg. MSB weight) to represent numbers