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UNIT-I: THE 8086 MICROPROCESSOR, covering all listed topics in paragraph format:

1. Introduction to 8086

The Intel 8086 is a 16-bit microprocessor introduced by Intel in 1978. It marked the beginning of
the x86 architecture, which later became the foundation of most modern PCs. The 8086 has a
20-bit address bus, which allows it to access 1 MB of memory (2²⁰ bytes). It operates at a clock
speed between 5 MHz to 10 MHz and has a 16-bit data bus, which means it can process 16 bits
of data simultaneously. The 8086 supports pipelining using a 6-byte instruction queue, which
increases execution speed. It uses segmented memory to separate code, data, and stack
areas, making memory management flexible and efficient.

2. Microprocessor Architecture

The architecture of the 8086 microprocessor is split into two main units:

●​ Bus Interface Unit (BIU): This unit is responsible for fetching instructions from memory,
reading/writing data, and calculating the physical address. It includes the instruction
queue (6 bytes), segment registers (CS, DS, SS, ES), and the instruction pointer (IP).
●​ Execution Unit (EU): This unit decodes and executes instructions fetched by the BIU. It
contains the Arithmetic and Logic Unit (ALU), general-purpose registers (AX, BX, CX,
DX), pointer registers (SP, BP), index registers (SI, DI), flag register, and control logic.
The EU cannot directly access memory; it must request the BIU.​

3. Addressing Modes

Addressing modes define how operands are accessed in memory or registers. The 8086
supports several addressing modes:

1.​ Immediate Addressing: Operand is specified in the instruction (e.g., MOV AX, 05H).
2.​ Register Addressing: Operand is a register (e.g., MOV AX, BX).
3.​ Direct Addressing: Memory address is directly specified (e.g., MOV AX, [1234H]).
4.​ Register Indirect Addressing: Memory address is held in a register (e.g., MOV AX,
[BX]).
5.​ Based Addressing: Uses base register (BX or BP) plus a displacement.
6.​ Indexed Addressing: Uses index register (SI or DI) plus a displacement.
7.​ Based-Indexed Addressing: Combines base and index registers (e.g., MOV AX,
[BX+SI]).
8.​ Relative Addressing: Used in control transfer instructions like JMP, with the offset
relative to current IP.​
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4. Instruction Set and Assembler Directives

The 8086 instruction set is rich and categorized into:

●​ Data transfer instructions: MOV, XCHG, IN, OUT, etc.

●​ Arithmetic instructions: ADD, SUB, MUL, DIV, INC, DEC.
●​ Logical instructions: AND, OR, XOR, NOT, TEST.
●​ Control transfer instructions: JMP, CALL, RET, INT, IRET.
●​ String instructions: MOVS, LODS, STOS, SCAS, CMPS.
●​ Bit manipulation and shift instructions: SHL, SHR, ROL, ROR.

Assembler Directives are not executable but tell the assembler how to process the code.
Examples include:

●​ DB, DW, DD – Define byte, word, and double word

●​ SEGMENT, ENDS – Define start and end of a segment
●​ ASSUME – Informs assembler about segment usage
●​ ORG – Sets the starting offset

5. Assembly Language Programming

Assembly language allows programmers to write instructions in symbolic form (mnemonics)

rather than binary. It provides control over hardware and is used for writing efficient, low-level
programs. A typical assembly program includes defining segments, declaring variables, and
writing code using mnemonics. Programs must include directives like .MODEL, .DATA, .CODE,
and use instructions properly within a procedure, ending with RET or INT 21H.

6. Modular Programming

Modular programming involves dividing a large program into small, manageable modules or
procedures. Each module performs a specific task and can be compiled separately. In 8086,
procedures are used to achieve modularity. These are defined using PROC and ENDP directives.
Modular programming improves program organization, debugging, testing, and reusability of
code.

7. Linking and Relocation

Linking combines multiple object files into one executable. It resolves references between
separately compiled modules. Relocation allows a program to be loaded into any memory
location by adjusting address references. The 8086 supports relocation through its segmented
memory system, where logical addresses are converted to physical addresses using
segment:offset combination (e.g., physical address = segment × 16 + offset).
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8. Stacks

The stack is a portion of memory used for temporary storage. It operates in a Last-In-First-Out
(LIFO) manner. The stack is accessed using the SP (Stack Pointer) and SS (Stack Segment)
registers. Instructions like PUSH, POP, CALL, and RET use the stack. For example, when a
subroutine is called, the return address is pushed to the stack, and retrieved during return.

9. Procedures

A procedure is a set of instructions grouped together to perform a specific task. It can be

invoked using the CALL instruction and exited using RET. Procedures can be near (within the
same segment) or far (different segment). They help in code reusability and modular
programming. Example:

asm
CopyEdit
MYPROC PROC
; procedure code
RET
MYPROC ENDP

10. Macros

Macros are reusable code snippets defined using the MACRO directive and substituted inline
during assembly. Unlike procedures, macros do not use CALL and RET, thus avoiding overhead.
However, they increase code size. Example:

asm
CopyEdit
PRINT_MSG MACRO
MOV AH, 09H
INT 21H
ENDM

Whenever PRINT_MSG is used, the macro code is expanded in place.

11. Interrupts and Interrupt Service Routines (ISRs)

Interrupts are events that cause the microprocessor to pause its current task and execute a
predefined subroutine (ISR). The 8086 supports 256 interrupt types, each associated with a
4-byte entry in the Interrupt Vector Table (IVT). Interrupts are of two types:
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●​ Hardware Interrupts: Triggered by external devices (e.g., keyboard).

●​ Software Interrupts: Triggered by instructions like INT.​
Common interrupts include:
●​ INT 21H: DOS function calls
●​ INT 10H: Video services​
ISRs are routines that handle interrupts and must end with IRET.

12. Byte and String Manipulation

The 8086 offers specialized instructions for string operations, which work with the SI, DI, and
CX registers:

●​ MOVSB, MOVSW: Move byte/word from source to destination.

●​ LODSB, LODSW: Load byte/word from string into accumulator.
●​ STOSB, STOSW: Store accumulator into string.
●​ CMPSB, CMPSW: Compare source and destination bytes/words.
●​ SCASB, SCASW: Scan a string for a value in AL/AX.​
These can be combined with the REP prefix to repeat operations based on CX. For
example, REP MOVSB copies a block of bytes.

UNIT-II: 8086 SYSTEM BUS STRUCTURE,

1. 8086 Signals

The Intel 8086 microprocessor uses a variety of signals to communicate with memory, I/O
devices, and other components. These signals are categorized as:

●​ Address/Data Lines (AD0–AD15): These are time-multiplexed and used to send

addresses during the first part of a bus cycle and data during the second part.
●​ Address Lines (A16–A19): These lines carry the higher 4 bits of the 20-bit address.
●​ Control Signals: These include RD (Read), WR (Write), ALE (Address Latch Enable),
DT/R (Data Transmit/Receive), and DEN (Data Enable), used for data and address flow
control.
●​ Status Signals (S0, S1, S2): Provide information about the current operation.
●​ Interrupt Signals: Include INTR (Interrupt Request), NMI (Non-Maskable Interrupt), and
INTA (Interrupt Acknowledge).
●​ Clock and Reset: CLK provides timing to synchronize operations, while RESET
initializes the processor.
●​ MN/MX (Minimum/Maximum mode): Decides how control signals are
managed—internally (min) or with external bus controller (max).
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2. Basic Configurations

The 8086 can be configured in two modes:

●​ Minimum Mode: Used for single-processor systems. The processor generates all
necessary control signals internally. Ideal for simple designs.
●​ Maximum Mode: Designed for multiprocessor environments. The 8086 relies on an
external bus controller (Intel 8288) to generate control signals. This mode supports
co-processors and other CPUs, enabling multitasking or distributed processing.

3. System Bus Timing

System bus timing defines how data and instructions move across the buses during read/write
cycles. Each bus cycle consists of at least four clock periods:

●​ T1: The processor places the address on the bus and asserts ALE.
●​ T2: The control signal (RD or WR) is activated.
●​ T3: Data is transferred (read or write) from memory or I/O device.
●​ T4: The bus is idle or prepared for the next operation.​
Wait states (Tw) may be added between T3 and T4 if a slow device is involved.

4. System Design Using 8086

Designing a microprocessor system involves connecting the 8086 to memory and I/O devices
through buses and control logic. Key components include:

●​ Latch (e.g., 74LS373): Used to separate address from the multiplexed AD0–AD15 lines.
●​ Transceiver (e.g., 74LS245): Allows bidirectional data flow between CPU and
memory/I/O.
●​ Decoder (e.g., 74LS138): Selects memory or I/O devices based on address.
●​ Clock generator (8284): Provides synchronized clock pulses.​
Designers must ensure proper address decoding, control signal timing, and data
routing.
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5. I/O Programming

Input/output programming involves interacting with external devices using software. The 8086
supports:

●​ Isolated I/O: Uses IN and OUT instructions with a separate 64K I/O address space.
●​ Memory-mapped I/O: Uses regular memory instructions to access I/O devices. Devices
are assigned memory addresses.​
I/O programming involves polling (checking device status in a loop) or interrupts (device
signals processor when ready), depending on application requirements.

6. Introduction to Multiprogramming

Multiprogramming is a technique where multiple programs share CPU time and memory.
Although the 8086 doesn’t support true multitasking, it can implement multiprogramming using
software techniques. By storing the state of one program (register values, stack) and switching
to another, the CPU can give the illusion of concurrent execution. It improves CPU utilization
and response time in systems with frequent I/O operations.

7. System Bus Structure

The system bus is a group of wires that carry data, addresses, and control signals between the
processor, memory, and I/O devices. It has three main parts:

●​ Address Bus: Carries the address of the memory or I/O device (8086 has 20-bit
address bus, so it can access 1MB memory).
●​ Data Bus: Transfers actual data (16-bit in 8086).
●​ Control Bus: Carries control signals like read/write, interrupt requests, and clock pulses.​
This shared bus structure ensures coordinated communication in a
microprocessor-based system.

8. Multiprocessor Configurations

Multiprocessor systems use multiple processors to perform tasks in parallel, improving speed
and reliability. In 8086 maximum mode:

●​ One 8086 can act as the master, while others are slaves.
●​ Communication occurs over the system bus.
●​ Control signals and arbitration logic determine which processor accesses memory or I/O
at a given time.​
Shared memory or message-passing techniques manage inter-processor
communication and resource allocation.
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9. Coprocessor

A coprocessor is an additional processor that works alongside the main CPU to handle
specialized tasks. The Intel 8087 is the coprocessor for the 8086 and performs complex
arithmetic operations, especially floating-point calculations. The 8086 identifies coprocessor
instructions through a special escape opcode (ESC), and the 8087 executes them concurrently.
This parallelism enhances computational efficiency, particularly in scientific and engineering
applications.

10. Closely Coupled and Loosely Coupled Configurations

●​ Closely Coupled Systems: Multiple processors share the same memory and are tightly
integrated with a common clock and bus. Communication is fast and synchronization is
easier, but complexity and cost increase.
●​ Loosely Coupled Systems: Each processor has its own memory and communicates
via messages over a bus or network. These systems are more flexible and fault-tolerant,
commonly used in distributed computing environments.

11. Introduction to Advanced Processors

After the 8086, Intel introduced more advanced processors with enhanced capabilities:

●​ 80286: Introduced protected mode and better memory management.

●​ 80386: A 32-bit processor supporting multitasking and virtual memory.
●​ 80486: Integrated math coprocessor (FPU) and pipelining for faster execution.
●​ Pentium series: Introduced superscalar architecture and parallel instruction execution.​
Advanced processors provide improved speed, multitasking, power efficiency, and
support for modern operating systems, far surpassing the 8086 in terms of architecture
and performance.

H
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UNIT - III: I/O INTERFACING

1. Memory Interfacing and I/O Interfacing

Memory interfacing refers to connecting RAM or ROM to the 8086 microprocessor so it can read
from or write to memory locations. This requires address decoding to ensure that specific
address ranges access particular memory chips. Control signals like RD and WR are used to
manage data transfer. I/O interfacing allows the microprocessor to interact with peripheral
devices such as switches, LEDs, displays, or sensors. The 8086 supports two types of I/O
interfacing: Isolated I/O, where separate instructions (IN and OUT) are used to access I/O ports
with a separate address space; and Memory-Mapped I/O, where I/O devices are treated as
memory locations, allowing regular memory instructions to be used.

2. Parallel Communication Interface

Parallel communication transfers multiple bits of data simultaneously across multiple data lines.
The Intel 8255 Programmable Peripheral Interface (PPI) is widely used for parallel data
communication with 8086. It has three 8-bit ports (Port A, Port B, and Port C) that can be
configured for input or output in different modes. It is particularly useful for applications that
require fast data transfer, such as controlling displays, motors, or sensors. Mode 0 is basic I/O,
Mode 1 provides handshaking, and Mode 2 allows bidirectional data transfer. Proper
programming of the control word register allows flexible I/O control.

3. Serial Communication Interface

In serial communication, data is sent one bit at a time through a single data line. The Intel 8251
USART (Universal Synchronous/Asynchronous Receiver Transmitter) is used to manage
serial communication with the 8086. It supports both synchronous (with a clock) and
asynchronous (without clock) modes. Serial communication is slower than parallel but suitable
for long-distance and low-pin applications like modem interfaces, RS232 connections, and
inter-computer communication. Data framing, baud rate control, and status checking are
handled by the 8251 chip.

4. D/A and A/D Interface

The 8086 microprocessor can only process digital data. To interface with the analog world,
Digital-to-Analog Converters (DACs) and Analog-to-Digital Converters (ADCs) are used.
DACs (like DAC0808) convert digital data from the microprocessor into corresponding analog
voltage or current. ADCs (like ADC0804 or ADC0809) take analog input (like from a temperature
sensor) and convert it into digital format for processing by the microprocessor. Control signals
like Start Conversion (SC), End of Conversion (EOC), and Output Enable (OE) are used during
the A/D conversion process.
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5. Timer

Timers are essential for tasks that require accurate time delays or counting events. The Intel
8253/8254 Programmable Interval Timer has three independent 16-bit counters and can be
used in applications like generating time delays, producing waveforms, or counting pulses. Each
counter can operate in six different modes, such as interrupt on terminal count, hardware
retriggerable one-shot, or square wave generator. It is clocked by an external clock signal and
controlled using control words programmed by the CPU.

6. Keyboard/Display Controller

The Intel 8279 is a special-purpose chip designed to handle keyboard and display interfacing. It
relieves the CPU from the tasks of scanning and refreshing. The chip can scan up to 64-key
keyboards and control up to 16-digit 7-segment LED displays. It handles key debouncing, key
code generation, and provides FIFO buffers for storing keystrokes. For display, it continuously
refreshes the display using time-multiplexing without CPU intervention, making it efficient for
digital clocks, calculators, and embedded displays.

7. Interrupt Controller

Interrupts allow devices to get the processor’s attention asynchronously. The Intel 8259
Programmable Interrupt Controller (PIC) manages multiple interrupt sources and prioritizes
them. It supports eight interrupt inputs and can be cascaded to handle up to 64 interrupts. It
sends an interrupt request (INTR) to the CPU and receives an interrupt acknowledge (INTA)
in response. It supports programmable priority levels, masking of interrupts, and vectoring
(providing the address of the interrupt service routine). It is essential for responsive systems
handling multiple I/O devices.

8. DMA Controller

The Direct Memory Access (DMA) technique allows peripherals to directly read/write memory
without CPU involvement, increasing data transfer efficiency. The Intel 8237 DMA Controller is
commonly used with the 8086 for this purpose. It allows block data transfer between I/O and
memory. The controller takes over the system buses during transfer and signals the CPU via
HOLD and HLDA pins. Modes include block, demand, and single transfer, which are useful for
high-speed devices like hard drives and sound cards.

9. Programming and Applications

Programming for I/O interfacing includes writing assembly routines to configure and control
interface devices like the 8255, 8279, or 8253. Programs involve setting control words,
reading/writing ports, and managing handshaking. Applications may include automation,
measurement systems, and communication devices. The programs typically involve initializing
devices, polling or using interrupts to handle data, and storing or displaying results. Efficient I/O
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programming enables responsive and robust embedded systems.

10. Case Studies

●​ Traffic Light Control: A common application where the 8086, in conjunction with 8255
and timers, controls Red, Yellow, and Green LEDs in a sequence with time delays. This
simulates a real traffic light system.
●​ LED Display Interface: Uses 8255 to control LED matrices or 7-segment displays by
sending appropriate patterns to illuminate segments or pixels.
●​ LCD Display Interface: LCDs require control signals (RS, RW, EN) and data input. The
microprocessor sends commands (like clear, display on) and characters to display. LCDs
can show alphanumeric messages and are widely used in embedded systems.
●​ Keyboard Display Interface: Using 8279, a keyboard is scanned and inputs are stored
in FIFO. The same chip controls display output, allowing the creation of interactive
embedded systems.
●​ Alarm Controller: Interfaces sensors with the microprocessor to detect faults or
abnormal conditions (like smoke or heat). When triggered, it can activate an alarm using
a relay, buzzer, or siren. Interrupts can be used to signal the CPU immediately when
danger is detected.

Unit IV | Part A: MICROCONTROLLER – 8051

1. Architecture of 8051

The 8051 microcontroller, developed by Intel, is an 8-bit microcontroller widely used in

embedded systems. It has a Harvard architecture, meaning separate memory for program and
data. The 8051 consists of 128 bytes of internal RAM, 4KB of ROM (on-chip), two 16-bit timers,
four parallel I/O ports (each 8-bit wide), a full-duplex serial port, and five interrupt sources. It has
an 8-bit ALU, a program counter, a stack pointer, and several special function registers (SFRs)
to manage internal operations. The crystal oscillator is usually 11.0592 MHz, making it
compatible with standard baud rates.

2. Special Function Registers (SFRs)

SFRs are registers used to control internal operations of the 8051. These include:

●​ ACC (Accumulator) and B register for arithmetic.

●​ PSW (Program Status Word) for flags.
●​ SP (Stack Pointer), DPTR (Data Pointer) for addressing.
●​ TCON, TMOD for timer control.
●​ SCON, SBUF for serial communication.
●​ IE, IP for interrupts.
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●​ Port registers: P0, P1, P2, P3.​

These are memory-mapped to the upper 128 bytes of the internal RAM (addresses 80H
to FFH).

3. I/O Pins, Ports and Circuits

The 8051 has 4 I/O ports (P0 to P3), each 8-bit wide. These ports can be programmed as input
or output:

●​ Port 0 (P0) is open-drain and requires external pull-up resistors.

●​ Port 1 (P1) is used for general I/O.
●​ Port 2 (P2) is also used for I/O or as high byte of address bus.
●​ Port 3 (P3) has alternate functions like RxD, TxD, INT0, INT1, T0, T1, WR, and RD.​
Each pin uses a latch and buffer system to control input/output behavior. Proper logic
levels and direction settings are crucial for interfacing.

4. Instruction Set

The 8051 instruction set is classified into:

●​ Data transfer instructions (MOV, XCH, PUSH, POP),

●​ Arithmetic instructions (ADD, SUBB, INC, DEC),
●​ Logical instructions (ANL, ORL, XRL, CLR, CPL),
●​ Branching instructions (SJMP, LJMP, AJMP, JC, JNC),
●​ Bit manipulation instructions (SETB, CLR, MOV C).​
The instruction set is simple and optimized for control-based applications. Instructions
range from 1 to 3 bytes in size and vary in execution cycles.

5. Addressing Modes

8051 supports the following addressing modes:

●​ Immediate: Operand is given in the instruction (e.g., MOV A, #25H).

●​ Register: Operand in a register (e.g., MOV A, R0).
●​ Direct: Address of operand is directly given (e.g., MOV A, 30H).
●​ Indirect: Uses registers (e.g., MOV A, @R0).
●​ Indexed: Used for accessing look-up tables in code memory (e.g., MOVC A, @A+DPTR).​
Understanding these modes is crucial for efficient assembly programming.
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6. Assembly Language Programming

Assembly programming in 8051 involves:

●​ Initializing ports, timers, and peripherals.

●​ Using labels, instructions, and assembler directives (e.g., ORG, END, DB, DW).
●​ Writing control loops using JMP, CALL, RET, etc.​
Programs should be efficient, with well-defined comments and structure. Examples
include LED blinking, counter, keypad reading, and serial data handling.

Part B: INTERFACING MICROCONTROLLER

7. Programming 8051 Timers

The 8051 has two timers: Timer 0 and Timer 1, each of 16 bits. They can work in different
modes (Mode 0, 1, 2, 3):

●​ Mode 1: 16-bit timer mode

●​ Mode 2: 8-bit auto-reload​
Timers are initialized using TMOD and controlled via TCON. They can be used for delay
generation, waveform creation, and clock event timing.

8. Serial Port Programming

Serial communication is handled using SCON and SBUF registers. 8051 supports full-duplex
communication using UART. Mode 1 (8-bit UART) is the most common. The baud rate is set
using Timer 1 in auto-reload mode. For example, to transmit "A", we write to SBUF and wait for
the TI (Transmit Interrupt) flag.

9. Interrupts Programming

8051 has five interrupt sources: two external (INT0, INT1), two timers (T0, T1), and one
serial. The IE (Interrupt Enable) and IP (Interrupt Priority) registers are used to configure
them. Interrupts can be used to execute a routine when an event occurs, such as keypress,
timer overflow, or incoming data, improving program efficiency.

10. LCD and Keyboard Interfacing

LCDs (e.g., 16x2) are interfaced using data lines (D0-D7) and control lines (RS, RW, EN).
Commands (clear, shift, cursor) and data (characters) are sent through ports. Keyboards
(typically 4x4 matrix) are scanned by sending rows low and reading columns. Debouncing and
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scanning logic are implemented in software.

11. ADC, DAC and Sensor Interfacing

ADC interfacing allows analog signals (from sensors) to be converted to digital values readable
by the 8051. ADC0804 is a commonly used chip, interfaced via 8255 or ports. DACs convert
digital values from 8051 to analog output, useful for generating audio signals or voltage levels.
Sensors like temperature, light, or motion sensors are used with ADCs to provide input to the
microcontroller system.

12. External Memory Interface

The 8051 can be connected to external program or data memory when internal memory is
insufficient. Port 0 and Port 2 are used for address/data multiplexing. The ALE signal is used to
latch the lower address byte. External RAM or ROM chips like 6264 (RAM) or 2764 (EPROM)
are commonly used.

13. Stepper Motor and Waveform Generation

Stepper motors are used in precise motion control applications. The 8051 can control a
stepper motor by sending a sequence of pulses to the driver circuit (ULN2003 or L293D).
Proper timing and direction control are handled in code. For waveform generation, timers and
DACs are used to produce square, triangular, or sine waves. This is useful in signal generation
or testing applications.